phyCORE-PXA255

Kit CD

  • phyCORE-PXA255 Tool-CD

Module Connector

PHYTEC Order Number: VB082

Other Documents

Visit Intel/Marvell PXA255 Product Summary Page to find data sheets, manuals, erratas, application notes, etc...

  • Intel/Marvell PXA255 Data Sheet
  • Intel/Marvell PXA255 Reference Manual

FAQ

phyCORE-PXA255

LPT-to-JTAG Interface for ARM (JA-001, JA-001-PXA)

Question:

 I have trouble communicating with a parallel port JTAG interface. What should I try?

 Answer:

 1.    The BIOS settings for the Parallel port should be one of the following: ECP, EPP or PS/2 Bi-directional.

 2.    In Windows XP: make sure to turn off the parallel port plug and play scanning "feature". This feature of Windows XP will interrupt parallel port communications between the PC and LPT-to-JTAG interface. This will yield what looks like sporatic communications. Turning of the autoscan "feature" may be turned off for the parallel port in the WINXP registry…….

 3.    The parallel cable connecting the PC parallel port and the LPT-to-JTAG interface MUST be IEEE1284 compliant. If the cable is not marked with the IEEE1284 text, then it is not compliant.

 4.    In Windows XP/2000, the parallel port dialog checkbox entitled "Enable Legacy Plug and Play" should be checked. This setting is located in the Control Panel à System à Hardware à Device Manager à Ports à Printer Port (LPTx) dialog. You must reboot your PC after this setting to take effect.

 5.    Make sure to turn off any applications which may be trying to access the printer port (such as a Print Manager) before running software to debug with LPT-to-JTAG interface.

 6.    Also beware that some laptops, in particular some of the IBM Thinkpads, do not implement a standard parallel port even though they claim they do. If you encounter this problem on a laptop and have access to a desktop machine, it is best to try the experiment on the desktop in order to rule out other issues.

phyCORE-PXA255: Display example

Question:

How do I use the example “Phytec_PXADisplay”? I open the platform builder project but a popup window states that there are some configurations not supported and will be grayed. I’m using Platform Builder 4.2.

Answer:

This error is most likely caused by the BSP not being integrated in the platform builder. As a result, the links to the PHYTEC specific items are not there yet.

 

phyCORE-PCA255: SD/MMC and compact flash card driver

Question:

How do I activate SD/MMC and compact flach cards? Since autodetect is not connected (J31 open) how should I make system aware of card presence? I’ve added support for SDMMC cards in platform builder.

Answer:

Our BSP for PXA255 only supports the Core Slot. This core slot does not support hot plugging of cards. But, what you may do is create a static registry entry for the MMC card driver:

 

REGEDIT4
 
[HKEY_LOCAL_MACHINE\Drivers\BuiltIn\sdmmc]
"HDEVICE"=dword:00042390
"IClass"=hex(7):\
     7b,41,33,32,39,34,32,42,37,2d,39,32,30,43,2d,34,38,36,62,2d,42,30,45,36,2d,\
     39,32,41,37,30,32,41,39,39,42,33,35,7d,00,7b,41,34,45,37,45,44,44,41,2d,45,\
     35,37,35,2d,34,32,35,32,2d,39,44,36,42,2d,34,31,39,35,44,34,38,42,42,38,36,\
     35,7d,00,00,00,00,00,00
"Profile"="SDMMC"
"FSD"="fatfs.dll"
"Ioctl"=dword:00000004
"Order"=dword:00000000
"FriendlyName"="SDCard/MMC Block Driver"
"Dll"="sdmmc.dll"
"Prefix"="DSK"
[HKEY_LOCAL_MACHINE\System\StorageManager\Profiles\SDMMC]
"Name"="SD/MMC Card"
"Folder"="Storage Card"

 

Here as well as the applicable driver must be included and loadable as module/file.

The same applies for compact flash:

 

REGEDIT4
 
[HKEY_LOCAL_MACHINE\Drivers\BuiltIn\PCMCIA]
"Dll"="PCMCIA.dll"
"IClass"=hex(7):\
     7b,36,42,45,41,42,30,38,41,2d,38,39,31,34,2d,34,32,66,64,2d,42,33,33,46,2d,\
     36,31,39,36,38,42,39,41,41,42,33,32,7d,3d,50,43,4d,43,49,41,20,43,61,72,64,\
     20,53,65,72,76,69,63,65,73,00,00,00,00

 

Make sure to check that the required driver files are present in the current image.

 

phyCORE-PXA255: Documentation of the CPLs’

Question:

Where can I find the documentation of the CPLs’ to be able to write the IDE controller drivers for the Evaluation board?

Answer:

See the attached PLD project file. Please also refer to section 5.3 in the Carrier Board manual: ftp://ftp.phytec.de/pub/Products/phyCORE-PXA255/Manuals/Hardware%20Manual/l-668e_1.pdf

 

phyCORE-PXA255: GPIO5 signal

Question:

Is there a connector on the baseboard besides X17 where I can attach to Signal GPIO_5?

Answer:

There is no other connector besides X17 that has this signal.

 

phyCORE-PXA255: CF access and write time

Question:

I am interested in finding CF access and write time. I would like to know a rough estimate on PHYTEC modules as far as speed that can be accessed and written CF cards. We are targeting Read/Write 11Mbps.

Answer:

MMC cards run at max. 2-4MBps in real life/applications. The transfer rate of standard SD cards can not be achieved on the phyCORE module because only one of the 4 data lines on the PXA255 is supported. On a PXA270 there are 4 data lines supported. When using CF cards it is not possible to specify exact transfer rates because the external circuitry and the design and components on the PCMCIA interface play an important role. I was once told that the practical access time is set to around 0.5 -1 microsecond for reading and writing in order to support a wide range of PCMCIA and CF cards. If the PXA255 would be using the bus interface for only PCMCIA and CF card operation then a data transfer rate of 2-4 MByte/s could be achieved. However, the PXA255 also has to execute programs, access Ethernet, USB and the LCD which all use the same bus interface. So if an application requires a high data throughput for CF cards then the system must be configured to match the specific type of CF card with its timing and the CF card interface must get a high priority within the system (which is possible in WinCE for example). Furthermore, no other slow devices should be within the memory area of the PCMCIA channel that is used to access the CF card. This is because the slowest device determines the timing for the entire PCMCIA channel.

 

phyCORE-PXA255: Reload UBoot

Question:

Is it possible to reload the UBoot code in FLASH? I want to add some basic functionality to the UBoot code and reload it onto the board.

Answer:

Yes. We include a JTAG to parallel adapter that allows you to connect your host PC to the PXA255 target system. Using the JFlash.exe tool, you can load/reload the UBoot boot loader.

 

phyCORE-PXA255: Downloading Linux

Question:

I have issues downloading the Linux kernel and filesystem.

Answer:

Be sure to set the server and client IP to be within your network. Pay attention to the note on Page 4 of the QuickStart, noting to user to be sure to enter IP address specific to your own TFTP server (Linux machine) and PXA255.

 

phyCORE-PXA255: CPU frequency

Question:

How can I adjust CPU’s frequency?

Answer:

The only entry that has something to do with CPU speed that I am aware of is:

            #define CFG_CPUSPEED 0x141

Probably it’s sufficient to adjust this value to your desired setting. It might be helpful to look at the PXA270 user’s manual for more details on registers needed to adjust CPLU frequency. There is a program called “dvfm” that could also be used to adjust the frequency. However this requires certain kernel patches which I am unsure if they are available for the PXA255.

 

phyCORE-PXA255: View bus transactions

Question:

Are there pins available for attachment of a logic analyzer to view the bus transactions to the on-board SDRAM?

Answer:

The on-board SDRAM is connected to the PXA255 controller’s address and data bus. All address and data lines are available on the phyCORE-PX255 Molex Connectors. Some of the control signals (Chip Select, RAS/CAS etc) are not routed to these pins. From the phyCORE Molex connector all address/data bus lines are routed to line driver ICs on the phyCORE-PXA255 Baseboard. From there, they are routed to the GPIO expansion board. Please refer to Section 17 in the manual ftp://ftp.phytec.de/pub/Products/phyCORE-PXA255/Manuals/Hardware Manual/l-657e_0.pdf

 

phyCORE-PXA255: WinCE BSP driver support

Question:

Can I get more information about WinCE driver support?

Answer:

WinCE 4.2 (Sigma) for the "phyCORE-XScale/PXA255 Development Kit":

    • Ethernet (required for boot of phyCORE-PXA255 target hardware)
    • LAN and DHCP Server (otherwise the Bootloader will search infinitely for a DHCP Server)
    • Display drivers for Sharp LQ084V1DG21 and compatible LCD displays (640x480, 8- and 16-bit color depth)
    • Audio Output (WM9712 Audio Controller supporting AC97 Audio Codecs)
    • USB Devices (e.g. Mice, Keyboard, Memory Stick)
    • Philips ISP1362 USB-OTG Controller
    • WM9xxx Touch Controller
    • Serial Interfaces (FFUART, BTUART)
    • PCMCIA (PC Card)
    • Max 7301 I/O Expander
    • Compact Flash / PC Card external memory
    • SD / MMC external memory
    • Active Sync
    • Media Player
    • Internet Explorer
    • Telnet Server
    • Network Utilities (ping ...)
    • Support for SMB / Redirector
    • Registry Flush tool
    • Standard Shell including AYGShell API Set
phyCORE-PXA255: ELinOS switching clock speed

Question:

Does ELinOS support switching the processor clock speed?

Answer:

Yes, ELinOS supports switching the processor clock if CPU clock change is enabled in the Kernel Configuration inside of ELK. This can be done by

      sh-2.05a# echo 400000 > /proc/sys/cpu/0/speed

      Changing CPU frequency to 398 Mhz (PXbus=196Mhz).

      sh-2.05a#

for example.

 

phyCORE-PXA255: Sleep modes

Question:

Which of the PXA low-power sleep modes does it support ?

Answer:

There are no low-power sleep modes supported at the moment.

 

phyCORE-PXA255: GNU C library and ELinOS

Question:

The PXA255 is using an old version of the GNU C library (2.5.5). Is there an updated kit that uses a 2.3.X library?

Answer:

The PXA-CD is only intended for demo. We suggest you to use ELinOS for further development. It is available for purchase at http://www.sysgo.com/

 

phyCORE-PXA255: Pin assignments

Question:

What is the layout of the pads that connect the two 160 pin connectors on the PCM-988-PXA expansion board?

Answer:

Please refer to the Carrier Board manual for GPIO expansion bus pin assignment ftp://ftp.phytec.de/pub/Products/phyCORE-PXA255/Manuals/Hardware%20Manual/l-668e_1.pdf

 

phyCORE-PXA255: WinCE booting without DHCP

Question:

We need a WinCE Image for pC-PXA255 which does not require a DHCP connection for WinCE to boot after its been successfully downloaded. Do you have such an image?

Answer:

Yes, Please contact support@phytec.de and request EBOOT_release_eng_dhcp.nb0. You can download this bootloader after you have installed the EBOOT_release_eng.nb0

 

phyCORE-PXA255: Loading UBoot Bootloader

Question:

How do I load U-Boot Bootloader to my phyCORE-PXA255?

Answer:

For downloading the U-Boot Bootloader please refer to the instructions for loading the E-Boot: ftp://ftp.phytec.de/pub/Products/phyCORE-PXA255/LAN-031e_3.pdf (see section 2.1 and 2.2) for more detail.

1. Please find the u-boot bin file on the tools CD under Linux. Copy the U-Boot file "u-boot_102.bin from the XScale tool CD to the same directory as jflash.exe, this should be on your hard drive ... pC-PXA255\WinCE
2. Connect JA-001-PXA to PC / PCM-990 at connector x29 on the phyCORE-PXA255 development board.
3. Power up the PCM-990.
4. Open the command-line Window, change to the J-Flash directory.
5. Make sure the U-Boot bin file is located in the same directory.
6. In the command line, type:
prog.bat u-boot_102.bin
7. The flash-programming should start.

You can also find the source for the U-boot in the folder "U-boot" on the same tools CD.

phyCORE-PXA255: Typo in Schematic ver. 1220.1

Question:

I have schematics versions 1220.1 for XScale Development board for phyCORE-PXA255. There is no dot indicating a node where J9, J15, and J14 seem to connect. Is this a typo?

Answer:

Yes. This issue is resolved in phyCORE-PXA255 Development Board (PCM-990) PCB version 1220.2.

phyCORE-PXA255: NSSTXD (pin 70) and NSSPSFRM (pin 80) Signals

<font size="4">Problem:</font>

I have a phyCORE-PXA255. I am looking at the schematics version 1219.1, which indicates that pin NSSPTXD/GPIO[83] connects to pin 80, and pin NSSPSFRM/GPIO[82] connects to pin 79. This does not seem correct. I have to swap these signals to get it to work.

<font size="4">Solution:</font>

Please double-check the PCB version of your phyCORE-PXA255 module. It should be version 1219.3, which corrects this issue.

pin NSSPTXD/GPIO[83] connects to pin 79
pin NSSPSFRM/GPIO[82] connects to pin 80

Schematics version 1219.1 is probably the wrong version of the schematics for your module, you need version 1219.3. please contact <font color="#006699">support@phytec.de</font> for this request.

JTAG header connector

Question:

We need to interface to X2, an ARM-JTAG connector pads on the i.MX31 board. Do you supply a connector/cable for this interface?

Answer:

We have the header connectors to be populated at X2 on the SBC module. We also have an adapter cable that converts the non-standard 2.0mm pitch at X2 to a more standard 2.54mm male connector. However, my recommendation is to access the JTAG header connector on the Carrier Board at X6.

phyCORE-PXA255: Loading Linux Image

 

<font size="4">Problem:</font>

Today I was loading Linux kernel to the PXA – 255 board. I got everything correct up to section 2.3 of pdf LAN - 032e (Downloading the Linux Kernel and File System). After typing tftpboot a3000000 phyImage for downloading, I got message
Kernel panic: VFS: Unable to mount root FS on IF: 02

After this I can’t go further ahead erasing the flash memory area i.e. erase 1:1-8

What will the reason for this?

<font size="4">Solution:</font>

Could you please print your environment variables by entering "printenv" in the command line of your console window
as follows:
PCM022> printenv

Here is an example of U-boot configuration on my module that I just tested and it works just fine:

PCM022> printenv
bootdelay=3
baudrate=115200
serverip=192.168.3.10
ipaddr=192.168.3.11
netmask=255.255.255.0
ethaddr=00:50:C2:3B:A9:64
bootargs=root=/dev/mtdblock2 rw ip=192.168.3.11:192.168.3.10:192.168.3.11:255.255.255.0::eth0: mem=64M console=ttyS0,115200n8 ide0=0xf6000000,0xf6000800 ide1=0xf7000000,0xf7000800
filesize=1d0133
bootcmd=tftpboot=a3000000 phyImage
stdin=serial
stdout=serial
stderr=serial
****************

Please configure your settings just like mine with the exception of your IP addresses.
If you have "autostart=yes" please change this with the following commands:
PCM022> setenv autostart [ENTER]
PCM022> saveenv

 


phyCORE-PXA255: Installing Programs on WinCE

 

Question:

I recently purchased the Basic development kit for the phyCORE XScale/PXA255 (KPCM-022-2010EI-B), went through the installation instructions to install the CE 4.2 runtime included with the kit, and successfully installed the OS. Now that the board is up and running (can telnet to the device) how do I install any programs that I have developed?

Answer:

You can use Active-Sync from MS to download applications and also an USB-Stick. Connect via a Null-Modem Cable to the FF-UART at the PCM-990 with your PC. Get Active Sync from Microsoft and install it. Start Active-Sync and during the connect procedure, start "repllog.exe" out of the Windows Directory at the PCM-022 under Windows CE.

 
Attention : The "repllog.exe" program is hidden. You have to enable show hidden files in the View Menu of the Explorer.

 

phyCORE-PXA: Jtag Prob (JA-001-PXA)

Question:

 

Can I use the Jtag Prob (JA-001-PXA) for debugging? 

Answer:

 

PHYTEC recommends several Jtag emulators that work with the phyCORE-PXA270:

1) The macraigor Raven or USB jtag is a good low cost option: http://www.macraigor.com/raven.htm

2) BDI2000 is the other option but more expensive: http://www.abatron.ch

3) Our winCE tool partner uses the EPI Majic-LX probe for debugging, it is expensive but can be used on various hardware. This probe can be accessed using an ethernet cable, or a serial cable. It is provided with an os-less application that can perform write and read from various flash devices, usefull when you want to dump the content of the strataflash. This EPI probe can also be used under platform builder 5.0 for debugging drivers or windows CE Kernel, by using hardware break points. http://www.epitools.com/products/probes.php

 

Linux

Mit welchen Tools kann ich unter Linux graphische Anwendungen erstellen?

Für das phyCORE- i.MX31 kann sowohl OpenGL, als auch QT verwendet werden, für das phyCORE-i.MX27 - zurzeit nur QT. Für das phyCORE- PXA270 steht X-Server zur Verfügung.

Windows Embedded CE

Add BSP to catalog

Question:

I am unable to add the BSP to catalog. I used the “Manage Catalog Features” dialog but there’s no new features added in catalog. The same thing happens when we use CEC editor.

Answer:

Click the “import” button. It doesn’t appear automatically. A selection menu will appear in which you can select the .CEC file. Browse to the folder where the BSP was unpacked to and select the file “phytec_pxa.cec”. The “Manage Catalog Features” should show “phytec.pxa.cec”. If you close this dialog, in the right window of the platform builder, a tree with “Third Party/BSPs/Phytec_PXA” should appear. If this is not the case, you might not have the full version of the platform. There has been issues reported when using the evaluation version.

 

Fragen und Antworten zu ähnlichen Produkten

LPT-to-JTAG Interface for ARM (JA-001, JA-001-PXA)

Question:

 I have trouble communicating with a parallel port JTAG interface. What should I try?

 Answer:

 1.    The BIOS settings for the Parallel port should be one of the following: ECP, EPP or PS/2 Bi-directional.

 2.    In Windows XP: make sure to turn off the parallel port plug and play scanning "feature". This feature of Windows XP will interrupt parallel port communications between the PC and LPT-to-JTAG interface. This will yield what looks like sporatic communications. Turning of the autoscan "feature" may be turned off for the parallel port in the WINXP registry…….

 3.    The parallel cable connecting the PC parallel port and the LPT-to-JTAG interface MUST be IEEE1284 compliant. If the cable is not marked with the IEEE1284 text, then it is not compliant.

 4.    In Windows XP/2000, the parallel port dialog checkbox entitled "Enable Legacy Plug and Play" should be checked. This setting is located in the Control Panel à System à Hardware à Device Manager à Ports à Printer Port (LPTx) dialog. You must reboot your PC after this setting to take effect.

 5.    Make sure to turn off any applications which may be trying to access the printer port (such as a Print Manager) before running software to debug with LPT-to-JTAG interface.

 6.    Also beware that some laptops, in particular some of the IBM Thinkpads, do not implement a standard parallel port even though they claim they do. If you encounter this problem on a laptop and have access to a desktop machine, it is best to try the experiment on the desktop in order to rule out other issues.

JTAG header connector

Question:

We need to interface to X2, an ARM-JTAG connector pads on the i.MX31 board. Do you supply a connector/cable for this interface?

Answer:

We have the header connectors to be populated at X2 on the SBC module. We also have an adapter cable that converts the non-standard 2.0mm pitch at X2 to a more standard 2.54mm male connector. However, my recommendation is to access the JTAG header connector on the Carrier Board at X6.

Pengutronix BSP supporting IDE

Question:

Will the Pengutronix BSP support IDE?

Answer:

The PXA270 can either support CAN or IDE. In the default settings, CAN is enabled and IDE is disabled. There are two lines of code to be changed in the Kernel.

 

Graphics driver

Question:

Where can I find more information about graphics unit on the PXA270? Also, is there source code driver support for the graphics display in Linux or other OS?

Answer:

Please refer to CHP 7 of the Hardware Manual in regards to the LCD controller. Our Windows Embedded CE BSP supports the graphics display.

 

Brownout and reset

Question:

On a new module, the boot time increase in proportion as power failure number. There was some signal quality issue on the reset signal when powering off/on too fast. The result was that CPU restarted while the flash device was not reset, which generate some read access failures to the flash from the boot loader. The boot loader not being able to access the flash considers it as corrupt and starts a reformat procedure. How do we fix this?

Answer:

During brownout conditions the /RESET_CORE is not set to a known state, thus causing eboot to think something is wrong so it begins to reformat the flash. It is recommended to connect an external supervisor outside of the phyCORE module to monitor the 3.3V (Vcc) supply and connected to the /RESIN pin, this will reset the PXA270 (via /RESET_CORE) properly. The module does not provide such a Vcc supervisor because it is designed to provide flexibility for the low current/power sleep modes that the PXA270 provides.

Please see section 4 of the phyCORE-PXA270 Hardware Manual. "If a core reset based on a VCC supply voltage drop is desired then the signal /RESIN must be activated by an external reset controller."

We recommend that you add an external supervisor to your target board. We use the MAX6364: http://datasheets.maxim-ic.com/en/ds/MAX6361-MAX6364P.pdf

You should test this fix in your system by connecting /RESET_CORE to /RESET. The easiest way to tie these signals together is to tie pin 1 of supervisor (U6) to pin 1 of supervisor (U9).

 

phyCORE-PXA270: SYS_EN pin on Acceleration PCB

Problem:

I am concerned that the SYS_EN pin isn’t used on the PXA270 Acceleration baseboard (Rev 001). Assuming the SYS_ENAB net (X1201B-pin 2B) is routed directly to the SYS_EN processor pin, shouldn’t this turn on the 3.3V supply to all the peripherals on the baseboard? I believe this is needed not just for deep sleep/wakeup, but also to ensure the 3.3V peripherals are initialized sufficiently before VCORE during power on. This is per Section 6.2.1: Power on Timing Specification in the PXA270 Electrical, Mechanical, and Thermal specification.   Please comment if this has been considered.

Solution:

It might be useful in other system architectures, especially in 'PDA-style applications', where the power supply circuits are more close combined with the CPU than this is possible within a SBC-design.

 

On our application board we have a dedicated power supply, which is logically separated from the CPU's power control unit on the SBC. Only two signals (PWR_KEY and PWR_OFF) are used to control the DC/DC-converters. This is a very simple approach, which enables to use the power sources in two ways (with and without sleep options). In our system architecture, the peripherals are immediately powered on in the moment the power supply is switched on (by pressing the 'Power Key'). Thus the peripherals are powered before the system reset becomes inactive.

SYS_EN is useful or even necessary, if not only the deep sleep mode but also the other sleep modes are intended to be used and also the peripherals are intended to be shut down during sleep state. Setting up a system architecture, which is able to handle this, is more complex and difficult to handle (especially concerning software drivers).

The idea of the PCM-969's power architecture is to demonstrate an easy way using the deep-sleep mode to avoid the boot-delay after power on in conjunction with a SBC module. The board design is not intended to support all possible sleep options of the PXA270 in an optimal way and is not capable to use any othe wakeup-source from deep-sleep than a power-on-event.

phyCORE-PXA270: Serial Peripheral Interface

Question:

How do I use the Serial peripheral interface? What are the basic instructions? Where can I find them?

Answer:

Serial peripheral interface information can be obtained by referencing the manufacturer users' manual which can be found at:

Downolad: Developer's Manual

phyCORE-PXA: Jtag Prob (JA-001-PXA)

Question:

 

Can I use the Jtag Prob (JA-001-PXA) for debugging? 

Answer:

 

PHYTEC recommends several Jtag emulators that work with the phyCORE-PXA270:

1) The macraigor Raven or USB jtag is a good low cost option: http://www.macraigor.com/raven.htm

2) BDI2000 is the other option but more expensive: http://www.abatron.ch

3) Our winCE tool partner uses the EPI Majic-LX probe for debugging, it is expensive but can be used on various hardware. This probe can be accessed using an ethernet cable, or a serial cable. It is provided with an os-less application that can perform write and read from various flash devices, usefull when you want to dump the content of the strataflash. This EPI probe can also be used under platform builder 5.0 for debugging drivers or windows CE Kernel, by using hardware break points. http://www.epitools.com/products/probes.php

 

phyCORE-PXA270: Linux reboot problem

Question:

I’ve noticed that sometimes when I do a soft reboot that the system doesn’t always fully reset. This will happen in both the uboot boot-loader SW and under Linux. Have you seen this issue before? Is there a register-based ‘switch’ I could control thru SW that will reset the HW? I’m doing either a ‘reset’ from u-boot or a ‘reboot’ from the linux shell. Either case will cause the system to ‘exit’, but not ever come back to allow uboot to run the kernel (or itself) again.

Answer:

 

Such reset problems can occur if the application is writing to Flash right before the soft reset takes place. It can be fixed by first reading from Flash after such writes and then initiating the reboot.

The “dd” command can be used for this, example:

root@phyCORE-PXA270:dd if=/dev/mtdblock2 of=/dev/null count=10
root@phyCORE-PXA270:reboot

 

Interfacing with Hitachi TFT

Question:

Could the PXA270 interface easily with the Hitachi 3.5” displays in portrait mode without hardware modifications?

Answer:

Be careful with displays that are based on the Hitachi TX09D70xxxxx and are labeled as “landscape version”. These types are in fact the same as the portrait displays, where they are equipped with the same electronics, but have their polarization filters rotated by 90degrees. This means that additional software is needed to rotate the image in the graphics performance would not be very fast. I would strongly recommend a display with “true” landscape mode.

 

Wireless Ethernet and LCD touch screen support

Question:

Is there a version of the PXA270 with wireless Ethernet and LCD/touch screen support?

Answer:

The current version of our PXA270 SBC module does not support WLAN. We only have wired LAN available. However, we offer a kit version with LCD and touch screen.

 

IEEE camera

Question:

Can the PXA270 connect to an IEEE 1394 camera? Is there a PCMCIA slot?

Answer:

There is an issue of the driver support. PHYTEC has no specific IEEE 1394 to PC card drivers available. You need to check with the provider of the card. I’m not sure what OS you would use on the PXA270 board.

 

USB-OTG and USB 2.0

Question:

Is there a USB-OTG on the board, or USB 2.0 compatible?

Answer:

The USB on the PXA 270 controller is 1.1. There are currently no drivers for OTG; only host or device are available. Please refer to Section 12 of the Intel PXA270 Developers Manual.

 

Camera speed and Frame Grabber

Question:

We need to obtain images on our PXA270 at about 100 frames per second in color 640*480 pixels. The frame rate of that Embedded Video Kit is too slow. About the image grabber pciGRABBER-4plus and pc/104 GRABBER-4plus, can they work with PXA270?

Answer:

The PXA270 does not have a PCI or PC/104 connection hence you wouldn’t be able to connect such frame grabber cards to the PHYTEC module. Some options to implement these on the module would be:

    • The Quick Capture Interface

It handles up to 60fps at 640*480 color. This would be doable with MICRON sensor for example. But for that, we would first have to develop a camera board, followed by writing a driver for it. In our Linux kit, because we have a 4-fold data amount to VGA, with the image processing add-on, we use a 1.3MPix sensor which can only handle 1.5fps at maximum.

    • IEEE1394 Interface

You are not able to get the full 480MBit speed.

    • Analog Frame grabber with PXA

This is typically rated for 30fps maximum speed.

 

phyCORE-PXA270: PCMCIA and ATA

Question:

Do you support the sockets for the PCMCIA ?
Can I connect a HDD 2.5” in ATA to your card without special controller?

Answer:

The PXA270 controller's first PCMCIA interface is used on the Development Board to realize an IDE socket for 2.5" hard drives. PLD U7 provides all the control logic to operate the IDE interface and the 2.0 mm header connector is located at X20 on the Development Board. Mounting holes for attaching the hard drive are located on the Development Board. The hard disk will be attached to the board using spacers above of the phyCORE-PXA270 module (refer to Figure 14
for details).

phyCORE-PXA270: MAC Addresses

Question:

 

Does phyCORE-PXA270 comes with MAC addresses already assigned?

 

Answer:

 

Yes we provide the MAC addresses.

 

phyCORE-PXA270: MMC/SD Card Modes

The following cards can be used with the MMC Connector on the PCM-027 operating in the following modes:

* MMC in 1-bit MMS (Multimedia Messaging)/SPI Mode

* SD in 1-bit SD/SPI Mode

* SD in 4-bit SD Mode

 

phyCORE-PXA270: "Bad Image CRC" Error After Restart

Question:

 

I have a question concerning a possible compatibility issue on our PHYTEC PXA270 development systems. Are the 1235.1 CPU cards incompatible with the 1220.3 development boards?  With this configuration I can load and copy an image into flash, however, a "Bad image CRC" error occurs after a power up restart, and in addition the red ‘activity’ LED, on the 1235.1, remains on all of the time. If I replace the 1235.1 with a 1235.2, the activity LED remains off until an application or process is started – and I have no boot-up errors.

Answer:

Check what version of U-Boot resides in the Flash by simply viewing the output on a serial Terminal. The Uboot version number will be 1.1.3 but the build date will be Jul 20 2005 or Jan 28 2006. If the build date is Jan 28 2006 then the wrong U-boot is on that board. That version of Uboot is for 1235.2 PCB only, because the 1235.2 has different version of Flash than 1235.1. The 1235.1 has Intel Strata Flash version K3 which has been discontinued. The 1235.2 has Intel Strata Flash version J3. The correct version of U-Boot for K3 flash (module pcb 1235.1) is included as an attachment below.  Follow the instructions here for loading Uboot at: 

Download: AppNote

 

 

Wie hoch ist die Leistungsaufnahme des phyCORE-PXA270 Moduls in unterschiedlichen Sleep und PowerDown Modi?

Zur Zeit unterstützen die Standardimages von WinCE oder Linux keine Sleep und PowerDown Modi. Die Leistungsaufnahmen der Module für den normalen Betrieb liegt bei max. 2W bei 3,3V.