L-1009e.A1 phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.1) Hardware Manual

Table of Contents

L-1009e.A1 phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.1) Hardware Manual
Document TitleL-1009e.A1 phyCORE-i.MX 8M Plus/phyBOARD-Pollux (1549.2/1552.1) Hardware Manual
Article NumberL-1009e.A1
Release Date28.07.2021
SOM Prod. No.PCM-070
SOM PCB No.1549.2


SBC Prod. No.:PBA-C-17
CB PCB No.: 1552.1


Edition:08.07.2021

Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (™ or ®) and copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents and trademarks are similarly not expressly indicated in this manual.

The information in this document has been carefully checked and is considered to be entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result.

Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so.

@ Copyright 2021 PHYTEC Messtechnik GmbH, D-55129 Mainz.

Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH.


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Address:

PHYTEC Messtechnik GmbH
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GERMANY

PHYTEC America LLC
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USA

PHYTEC France
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FRANCE

PHYTEC Embedded Pvt. Ltd
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27th Main, 2nd Sector, Opp. PEP School
V2, HRS Layout
Bangalore 560102
INDIA

PHYTEC Information Technology (Shenzhen) Co. Ltd.
2106A, Block A, Tianxia Jinniu Square
Taoyuan Road, Nanshan District
518052 Shenzhen, Guangdong,
CHINA

Ordering Information:

+49 6131 9221-32
sales@phytec.de

+1 800 278-9913
sales@phytec.com

+33 2 43 29 22 33
info@phytec.fr

+91-80-4086 7046/48
sales@phytec.in
+86-755-3395-5875
sales@phytec.cn

Technical Support:

+49 6131 9221-31
support@phytec.de

+1 206 780-9047
support@phytec.com


support@phytec.fr

+91-80-4086 7047
support@phytec.in

support@phytec.cn

Fax:

+49 6131 9221-33

+1 206 780-9135

+33 2 43 29 22 34


+86-755-3395-5999

Web Site:

http://www.phytec.de
http://www.phytec.eu

http://www.phytec.com

http://www.phytec.fr

http://phytec.inhttp://www.phytec.cn

Information on this Manual

This hardware manual describes the PCL-070 System on Module, referred to as phyCORE®-i.MX 8M Plus, and the PBA-C-17, referred to as phyBOARD®-Pollux. This manual also specifies the phyCORE-i.MX 8M Plus and phyBOARD-Pollux' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M Plus microcontrollers can be found in the i.MX 8M Plus Microcontroller Data Sheet/Reference Manual.

Both of these products are in the alpha stage. Due to this, there will be several changes and additions to this manual. New versions will be released in the future with no notice. Please make sure that you are using the latest version of this manual when working with your product.

Design Considerations

The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and is known to work. The schematics have been re-formatted to fit better in this hardware manual.

Many hardware examples and suggestions are given in the following pages. Designing the phyCORE System on Module onto a Carrier Board is generally straightforward. However, before committing to a particular active component selection when designing a carrier board, it is wise to check out the software driver support for those components. A particular device may be supported in, say, for example, Linux but not in Windows Embedded Compact 7. Your overall project may go smoother if you pick components that are already supported in your target OS. The premade selections for our reference designs, for example our Single Board Computers, are typically focused on using components that are well supported under Linux.

Specific details may need to be considered when designing a customer-specific carrier board. For design information on carrier board components, please check the Design Considerations in each component section of phyCORE-i.MX 8M Plus on the phyBOARD-Pollux. Be aware that not all components need to be considered when designing your own carrier board.

Preface

As a member of PHYTEC's phyCORE® product family, the phyCORE‑i.MX 8M Plus is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers, various types of memory (RAM, NAND flash, eMMC), and many other features. This, in turn, offers increased types of functions and configurations. PHYTEC supports a variety of 8/16/32/64-bit controllers in two ways:

  1. As the basis for Rapid Development Kits which serve as a reference and evaluation platform
  2. As insert-ready, fully functional phyCORE® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "reinvent" microcontroller circuitry. Furthermore, much of the value of the phyCORE® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative, full-system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Ordering Information

The part numbering of the phyCORE PCM-070 has the following structure:


Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
https://www.phytec.de/produkte/system-on-modules/phycore-imx-8m-plus/
or
https://www.phytec.com/product/phycore-i-mx-8m-plus/

Note

Assembly Options include a choice of Controller, RAM (Size/Type), Size of NAND Flash, interfaces available, vanishing, temperature range, and other features. Please contact our sales team to get more information on the ordering options available.

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 8M Plus

PHYTEC System on Modules are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

Warning

PHYTEC products lacking protective enclosures are subject to damage by ESD and, therefore, must be unpacked, handled, or operated in environments in which sufficient precautionary measures have been taken with respect to ESD dangers. Only appropriately trained personnel such as qualified electricians, technicians, and engineers should handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than 3 m.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Tip

Implementation of PHYTEC products into target devices, as well as user modifications and extensions of PHYTEC products, is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives. Users should ensure conformity following any modifications to a product as well as the implementation of a product into target systems.

Product Change Management and Information Regarding Parts Populated on the SOM / SBC

With the purchase of a PHYTEC SOM / SBC, you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.

Our general philosophy here is: We will never discontinue a product as long as there is a demand for it.

To fulfill this, we have established a set of methods to fulfill our philosophy:

Avoidance strategies:

  • Avoid changes by evaluating the longevity of parts during the design-in phase.
  • Ensure the availability of equivalent second source parts.
  • Stay in close contact with part vendors to keep up with roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

  • Ensure long-term availability by stocking parts through last time buy management according to product forecasts.
  • Offer long-term frame contracts to customers.

Change management in cases of functional changes:

  • Avoid impacts on product functionality by choosing equivalent replacement parts.
  • Avoid impacts on product functionality by compensating changes through hardware redesign or backward-compatible software maintenance.
  • Provide early change notifications concerning functional, relevant changes to our products.

We refrain from providing detailed part-specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

  • QS Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a BSP, the device tree, and accessing peripherals.
  • Hardware Manual:  A detailed description of the System on Module and accompanying carrier board. 
  • Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; introducing, installing, and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
  • BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
  • Development Environment Guide:  This guide shows how to work with the Virtual Machine (VM) Host PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running demo projects for these programs on a phyCORE product as well. Information on how to build a Linux host PC yourself is also a part of this guide.
  • Pin Muxing Table:  phyCORE SOMs have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case-by-case basis. Most of the documentation can be found on the applicable download page of our products.

Tip

After finishing the Quickstart Guide, we recommend working through the Development Environment Guide. This will give you a comprehensive overview of the features and functions of both the SOM and carrier board.

These manuals and more can be found in the download section of phyCORE-i.MX 8M Plus Product page.

Conversions, Abbreviations, and Acronyms

Tip

Due to part maintenance for our products (which are subject to continuous changes), we refrain from providing detailed, part-specific information within this manual. Please read the section Product Change Management and Information Regarding Parts Populated on the SOM / SBC  within the Preface for more information.

Tip

The BSP delivered with the phyCORE-i.MX 8M Plus usually includes drivers and/or software for controlling all components such as interfaces, memory, etc. Programming close to hardware at the register level is not necessary in most cases. For this reason, this manual does not contain detailed descriptions of the controller's registers or information relevant to software development. Please refer to the i.MX 8M Plus Reference Manual, if any information not found in this manual is needed to connect customer-designed applications.

Conventions

The conventions used in this manual are as follows:

  • Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low or are driving low.
  • A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
  • The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the address byte. The correct value of the LSB, which depends on the desired command (read (1), or write (0)), must be added to get the complete address byte. For example, if the given address in this manual is 0x41 =>, the complete address byte = 0x83 to read from the device and 0x82 to write to the device
  • Tables that describe all settings show the default position in bold, blue text.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of signal.

Signal Type

Description

Abbreviation

Power In
Supply voltage inputPWR_I
Power Out
Supply voltage outputPWR_O
Ref-VoltageReference voltage outputREF_O
Input  Digital inputI

Output

Digital outputO
I/O
Bidirectional input/push-pull outputI/O
Input/OD-OutputInput / open-drain output requires an external pull upI/OD
OC-Bidir PUOpen collector input/output with pull upOC-BI-PU
OC-Output  Open collector output without pull up requires an external pull upOC
OD-Bidir PU  Open-drain input/output with pull upOD-BI-PU
OD-Output Open-drain output without pull up requires an external pull upOD
5V Input PD5 V tolerant input with pull-down5V-PD
USB IO Differential line pairs 90 Ohm USB level bidirectional input/outputUSB_I/O
ETHERNET Input Differential line pairs 100 Ohm Ethernet level inputETH_I
ETHERNET Output Differential line pairs 100 Ohm Ethernet level outputETH_O
ETHERNET IO Differential line pairs 100 Ohm Ethernet level bidirectional input/outputETH_I/O
PCIe Input Differential line pairs 100 Ohm PCIe level inputPCIe_I

PCIe Output 

Differential line pairs 100 Ohm PCIe level outputPCIe_O

PCIe IO

Differential line pairs 100 Ohm PCIe level outputPCIe_I/O
HDMI InputDifferential line pairs 100 Ohm HDMI level inputHDMI_I
HDMI OutputDifferential line pairs 100 Ohm HDMI level outputHDMI_O

MIPI CSI-2 Input 

Differential line pairs 100 Ohm MIPI CSI‑2 level inputCSI2_I
MIPI DSI-2 Output Differential line pairs 100 Ohm MIPI DSI-2 level inputDSI2_O
CAN FD IO Differential line pairs 120 Ohm  CAN FD level bidirectional input/outputCAN_I/O

Signal Types

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document.

AbbreviationDefinition
BGABall Grid Array

BSP

Board Support Package (software delivered with the Development Kit including an operating system (Windows or Linux) preinstalled on the module and development tools)

CB

Carrier board; used in reference to the phyCORE development kit carrier board

EMI

Electromagnetic Interference

GPI

General-purpose input

GPIO

General-purpose input and output

GPO

General-purpose output

IRAM

Internal RAM; the internal static RAM on the NXP® Semiconductor i.MX 8M Plus microcontroller

J

Solder jumper; these types of jumpers require solder equipment to remove and place

JP

Solderless jumper; these types of jumpers can be removed and placed by hand with no special tools

OEMOriginal Equipment Manufacturers

PCB

Printed circuit board

PCMProduct Change Management
PCNProduct Change Notification

PMIC

Power management IC

RTC

Real-time clock

SBCSingle Board Computer

SMT

Surface mount technology

SOM

System on Module; used in reference to the PCM-070 /phyCORE®-i.MX 8M Plus module

Sx

User button Sx (e.g. S1, S2, etc.) used in reference to the available user buttons, or DIP-Switches on the carrier board

Sx_y

Switch y of DIP-Switch Sx; used in reference to the DIP-Switch on the carrier board

VMVirtual Machine

Abbreviations and Acronyms Used in this Manual

phyCORE-i.MX 8M Plus Introduction

The phyCORE‑i.MX 8M Plus belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of the PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all EMI (Electro-Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 20 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high noise environments.

phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 8M Plus is a subminiature (40 mm x 37 mm) insert-ready System on Module populated with the NXP® Semiconductor i.MX 8M Plus microcontroller. Its universal design enables it to be inserted into a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch, or surface mount technology (SMT) connectors (all pitch 0.5 mm) aligning two sides of the board, allowing it to be plugged or soldered into any target application like a "big chip".

The descriptions in this manual are based on the NXP® Semiconductor i.MX 8M Plus. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 8M Plus.

phyCORE-i.MX 8M Plus Features

The phyCORE‑i.MX 8M Plus offers the following features:

  • Insert-ready, sub-miniature (40 mm x 37 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology
  • Mounted using Samtec Connectors or using Direct Solder Connector (DSC)
  • Populated with the NXP® Semiconductor i.MX 8M Plus microcontroller (BGA548 packaging)
  • Up to 4 ARM-A53 cores (clock frequency up to 1.8 GHz)
  • Machine Learning Neuronal Processing Unit (NPU) with 2.3 TOPS
  • One Cortex M7 core (800 MHz). All Cortex M7 dedicated interfaces are explicitly made available on the SOM connector.
  • Tensilica Hifi4 Audio DSP (800 MHz)
  • 3D GPU GC7000UL and 2D GPU GC520L
  • Neural Network Accelerator (up to 2.3TOPS)
  • Onboard Image Signal Processor (up to 12MP resolution/ up to 375MP/s)
  • Boot from different memory devices (eMMC Flash standard)
  • Single supply voltage of +3.3 V with onboard power management
  • Selectable IO voltage between 1.8 V and 3.3 V
  • All controller-required supplies are generated onboard using sophisticated onboard Power Management
  • Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins
  • up to 8 GB[1] LPDDR4 RAM

  • up to 64 GB[1] onboard eMMC in the commercial temperature range (up to 32 GB for I-Temp)
  • up to 64 MB[1]Quad SPI Nor Flash
  • 4kB[1]I2C EEPROM
  • Two USB 3.0/2.0 Dual-Role interfaces with PHY
  • Two 1Gbit Ethernet interfaces with TSN support (either one of them with Ethernet transceiver on the phyCORE-i.MX 8 M Plus enabling a direct connection to an existing Ethernet network; the second as RGMII Signals at logic-level at the signal pins instead)

  • Three I2C interfaces
  • Two SPI interfaces
  • PCIe interface
  • Four UART interfaces
  • Two CAN-FD interfaces
  • Four PWM outputs
  • MIPI DSI-2 interface
  • HDMI interface
  • Two MIPI CSI-2 camera interfaces
  • LVDS Tx interface 2 channels x4
  • One 4-bit SD-Card interface
  • One 8-bit SDIO interface
  • Two SAI audio interfaces
  • One SPDIF interface
  • Extreme Low Power RTC Module
  • Four temperature sensors to monitor the board's temperature profile
  • All processor interfaces available at the SOM Connector
  • Available for different temperature grades (see Product Temperature Grades)

1.

The maximum memory size listed as of the printing of this manual. Please contact PHYTEC for more information about additional or new module configurations available.

phyCORE-i.MX 8M Plus Block Diagram

Block-diagram-phyCORE-iMX8M-Plus.png

phyCORE-i.MX 8M Plus Block Diagram

phyCORE-i.MX 8M Plus Component Placement

phyCORE-i.MX 8M Plus Component Placement (Top View)

phyCORE-i.MX 8M Plus Component Placement (Bottom View)

phyCORE-i.MX 8M Plus Minimum Operating Requirements

Warning

We recommend connecting all available +3.3 V input pins to the power supply system on a custom carrier board housing the phyCORE-i.MX 8M Plus and, at minimum, the matching number of GND balls neighboring the +3.3 V balls. In addition, proper implementation of the phyCORE-i.MX 8M Plus module into a target application also requires connecting all GND pins.
Refer to Power for more information.

Before the phyCORE-i.MX 8M plus can be used, please make sure the host system meets the minimum operating requirements. These include:

  • Stable and clean input power supply of 3.3 V with low ESR bulk capacitors (e.g. 2x 100µ/6.3V MLCC) paired with some HF blocking capacitors (e.g. 100nF MLCC) connected to the input pins as near as possible (phyCORE-i.MX 8M Plus Power Consumption)
  • Appropriate configuration of the I/O voltage (3.3 V or 1.8 V) configured by signal X_VIO_Ctrl (External Logic IO Supply Voltage)
  • Supply voltage for externally connected peripherals should be controlled by signal X_nPWR_READY to avoid reverse currents (External Logic IO Supply Voltage)
  • If external peripherals need longer reset delay, hold reset signal X_POR_B_VIO as long low as needed (Reset)
  • Desired boot configuration - default configuration is "Boot from onboard eMMC" (System Boot Configuration)
  • To back up the onboard I2C-RTC, connect a buffer voltage source to input pin VBAT (Backup Power (VBAT / VIN_SNVS_1V8), RTC)

Pin Description

Warning

Module connections must not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller manuals/datasheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.   

All controller signals extend to surface mount technology (SMT) connectors (0.5 mm). These connectors line two sides of the module (referred to as phyCORE-Connectors). This enables phyCORE-i.MX 8 Plus to be plugged into any target application like a "big chip".

PHYTEC provides a complete pinout table for the phyCORE-i.MX 8M Plus Connector (X1). This table contains a complete signal path for the phyCORE‑i.MX 8M Plus and the carrier board phyBOARD-Pollux, including signal names, pin muxing paths, and descriptions specific to each pin. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found with the phyCORE-i.MX 8M Plus Pinout Table.

Warning

  • The NXP® Semiconductor i.MX 8M Plus is a multi-voltage operated microcontroller and, as such, special attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other onboard components. Please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual for details on the functions and features of controller signals and port pins.
  • As some of the signals which are brought out on the phyCORE-Connector are used to configure the boot mode for specific boot options, please make sure that these signals are not driven by any device on the baseboard during reset. The signals which may affect the boot configuration are shown in phyCORE-Connector Boot Configuration Pins.
  • It is necessary to avoid voltages at the IO pins of the phyCORE-i.MX 8M Plus which are sourced from the supply voltage of peripheral devices attached to the SOM during power-up or power-down. These voltages can cause a current flow into the controller, especially if peripheral devices attached to the interfaces of the i.MX 8M Plus are supposed to be powered while the phyCORE‑i.MX 8M Plus is in suspend mode or turned off. To avoid this, bus switches are either supplied by VDD_3V3 on the phyCORE side or have their output enabled to the SOM controlled by the X_nPWR_READY signal (see Supply Voltage for External Logic) must be used.

Jumpers

The phyCORE-i.MX 8M Plus has only one pre-configured solder jumper (J1). There are, however, a few jumpers on the phyCORE-Pollux. Information on these jumpers can be found inJumpers.

Warning

Due to the small footprint of the solder jumpers (J), PHYTEC does not recommend manual jumper modifications. This may also render the warranty invalid. Contact our sales team if you need jumper configurations different from the default configuration.

Typical Jumper Pad Numbering Scheme

Jumper Location (top view)

The jumpers (J = solder jumper) have the following functions.

JumperPositionDescriptionTypeSection
J11+2 (default)
RTC_CLKOUT is connected to X_RTC_CLKOUT/nTEMP_ALERT0201RTC
2+3nTEMP_ALERT is connected to X_RTC_CLKOUT/nTEMP_ALERT
Temperature Sensors

Jumper Settings

Power

The phyCORE‑i.MX 8M Plus operates off of a single power supply voltage. The following section discusses the primary power pins on the phyCORE i.MX 8M Plus Connector X1 in detail.

Primary System Power (VIN_3V3)

The phyCORE‑i.MX 8M Plus is powered by a primary voltage supply with a nominal value of +3.3 V. Onboard switching regulators generate the voltage supplies required by the i.MX 8M Plus MCU and onboard components from the primary 3.3 V supplied to the SOM.

For proper operation, the phyCORE‑i.MX 8M Plus must be supplied with a voltage source of 3.2...3.5 V with a maximum power consumption of a 4 A load at the VCC pins on the phyCORE.

                VIN_3V3:                        X1 → C1..C4, D1..D4

Connect all +3.3 V VCC input pins to your power supply and, at minimum, the matching number of GND pins.

                Corresponding GND:           X1 → C5..C7, C15, D5..D7, D13

Please refer to section Pin Description for information on additional GND Pins located at the phyCORE i.MX 8M Plus Connector X1.

For information on various power consumption scenarios that PHYTEC has run, go to phyCORE-i.MX 8M Plus Power Consumption.

Warning

As a general design rule, PHYTEC recommends connecting all GND pins to neighboring signals which are being used in the application circuitry. For maximum EMI performance, all GND pins should be connected to a solid ground plane. Additionally take care of a solid, low impedance connection of the power supply line to avoid voltage drop. It is recommended to place a couple of bulk capacitors near as possible to the phyCORE's system power input (VIN_3V3) to compensate for the trace inductance.

Power Management IC (PMIC) (U3)

The phyCORE-i.MX 8M Plus provides an onboard Power Management IC (PMIC) at position U3 to generate different voltages required by the microcontroller and the onboard components. The PMIC supports many functions like different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 8M Plus via the onboard I2C bus (I2C1). The I2C address of the PMIC is 0x25.

Power Domains

External voltages to supply the board:

  • VIN_3V3 3.3 V main supply voltage (3.2 .. 3.5 V / max. 4A)
  • optional: VIN_SNVS_1V8 low power supply voltage input (1.8 V ±5% / 10mA; if left open, it is provided on-board if VIN_3V3 is present)
  • VBAT backup supply voltage for the on-board I2C-Bus RTC U9 (RV-3028-C7)

External Logic IO Supply Voltage

The voltage level (VDD_IO) of the phyCORE’s logic interface circuitry is VDD_3V3 (3.3 V) or VDD_1V8 (1.8 V) which is determined by the configuration input signal X_VIO_Ctrl (X1-D8). Connect X_VIO_Ctrl to the module input supply voltage VIN_3V3 to configure VDD_IO=3.3 V interface voltage level or connect it to GND to select VDD_IO=1.8 V interface voltage level.

In order to follow the power-up and power-down sequencing mandatory for the i.MX 8M Plus, external devices connected to the phyCORE interface circuitry have to be supplied by an external power supply which is controlled by the output signal X_nPWR_READY (OD driver) which is brought out at pin X1-C14. X_nPWR_READY should control the external supply voltage which is used to supply the external interface circuitry connected to the phyCORE's interfaces. X_nPWR_READY switches to GND to start the external voltage supply or to switch over a power switch. If the onboard interface voltage (VDD_IO) switches off, X_nPWR_READY is released to high impedance. To raise the signal, an external pull-up resistor (eg. 4k7) is needed. It can be connected to voltage levels up to max. 12V depending on the external power supply control signal requirement. Use of X_nPWR_READY ensures that external components are only supplied when the supply voltages of the i.MX 8M Plus is stable and avoids undefined return currents while the system is powered down.

Warning

It is recommended to monitor the externally generated power supply voltages by a voltage supervisor. The supervisor should hold X_POR_B_VIO (X1-C13) low, as long as the externally generated voltages are not in proper shape. To drive X_POR_B_VIO to GND, use an open-drain driver (OD) or N-channel FET (e.g. DMN1260UFA). X_POR_B_VIO has an onboard pull-up resistor to VDD_IO.

Backup Power (VBAT / VIN_SNVS_1V8)

To back up the on-board I2C-Bus RTC U9 (RV-3028-C7), an external voltage source must be added at Pin X1-C9 (VBAT). The RTC has an extremely low backup current consumption of only 40nA (@3 V). It is also possible to supply the internal RTC and some critical registers of the i.MX 8M Plus' low power domain (NVCC_SNVS_1V8). NVCC_NSNVS_1V8 can be supplied over Pin X1-C8 if VIN_3V3 is not present.

Reset

The X_PMIC_RST_B signal (Pin X1-C11) on the phyCORE-Connector is designated as a "cold reset" input. Driving X_PMIC_RST_B to low (has weak pull-up to SNVS_1V8) will restart the system performing a complete power recycle. X_PMIC_RST_B has a 50ms debouncing circuit. This input can be used for a mechanical reset switch button. X_POR_B_VIO Signal (Pin X1-C13) can be used to prevent bootup of the i.MX 8M Plus. This can be used as a startup as described in the section Power Management IC

System Boot Configuration

Most features of the i.MX 8 Plus microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

  • Boot mode selection
  • Boot device selection
  • Boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 8M Plus after POR. The ROM code detects the boot mode by using the boot mode pins (BOOT_MODE[3:0]), while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO input pins (X_BOOT_MODE[3:0]).

Boot Mode Selection

The boot mode of the i.MX 8M Plus microcontroller is determined by the configuration of four boot mode inputs BOOT_MODE[3:0] during the reset cycle of the operational system. These inputs are brought out at the phyCORE processor pins X_BOOT_MODE[3:0] (X1-D22, X1-D23, X1-D24, X1-D25). phyCORE-i.MX 8M Plus Boot Modes shows the possible settings of pins X_BOOT_MODE[3:0] and the resulting boot configuration of the i.MX 8M Plus.

Boot ModeX_BOOT_MODE3X_BOOT_MODE2X_BOOT_MODE1X_BOOT_MODE0Boot Source
0

0

000Boot from internal fuses
10001USB Serial Downloader
20010

Boot from onboard eMMC U4

30011Boot from ext. SD-Card on SD2
60110Boot from onboard QSPI Flash U5
151111JTAG mode

 phyCORE-i.MX 8M Plus Boot Modes

The X_BOOT_MODE[3,2,0] lines have 100 kΩ pull-down resistors populated (and unpopulated pull-up resistors) while X_BOOT_MODE[1] has a 4,7 kΩ pull-up resistor on the module in parallel to the internal pull-down resistors of the i.MX8 M Plus. Leaving the four pins unconnected sets the controller to boot mode 1, boot from onboard eMMC U4 memory device. The boot configuration settings can be changed by changing the populated resistors configuration on the module or by connecting configuration resistors (e.g. 4,7 kΩ pull-up) to the X_BOOT_MODE configuration signals. The pull-up resistors must be supplied by the right VDD_IO voltage level of 1.8 V or 3.3 V depending on the VDD_IO configuration (see section "External Logic IO Supply Voltage").


 phyCORE-i.MX 8M Plus onboard Boot Configuration schematic

TThe BOOT_MODE is initialized by sampling the BOOT_MODE inputs on the rising edge of the POR_B. After these inputs are sampled, their subsequent state does not affect the contents of the BOOT_MODE internal register and the pins can be used for GPIO operation.

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

D22X_BOOT_MODE0VDD_IO1.8 V / 3.3 VI/O

Boot configuration pin 0 during reset

has onboard 100k pull-down resistor (SMD 0201)

D23X_BOOT_MODE1VDD_IO1.8 V / 3.3 VI/O

Boot configuration pin 1 during reset

has onboard 4,7 k pull-down resistor  (SMD 0201)

D24X_BOOT_MODE2VDD_IO1.8 V / 3.3 VI/O

Boot configuration pin 2 during reset

has onboard 100k pull-down resistor (SMD 0201)

D25X_BOOT_MODE3VDD_IO1.8 V / 3.3 VI/O

Boot configuration pin 3 during reset

has onboard 100k pull-down resistor (SMD 0201)

 phyCORE-i.MX 8M Plus Boot Configuration Pins

Warning

Modules up to revision PCM-070-0F3243I.A1, PCM-070-0F3243I.S1, PCM-070-0F5443I.A0 are configured for boot from internal fuses. This moduls have a populated 100 kΩ pull-down resistor R88 and the 4,7 kΩ pull-up resistor R45 is unpopulated

System Memory

The phyCORE‑i.MX 8M Plus provides three types of onboard memory:


Basic-VersionKit-VersionExclusive-VersionMaximum available
One bank LPDDR4 RAM
2 GB
8 GB
eMMC
8 GB
64 GB
QSPI NOR Flash
32 MB
256 MB

Additionally, an I²C-EEPROM with 4 kB is mounted to every SOM. Details for each memory type used on the phyCORE‑i.MX 8M Plus are below.

LPDDR4-RAM (U1)

The RAM memory interface of the phyCORE‑i.MX 8M Plus supports one 32-bit LPDDR4-RAM chip (U1). The LPDDR4 memory is accessible starting at address 0x4000 0000 and 1 0000 0000.

Typically, the LPDDR4-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 8M Plus controller. Refer to the NXP Semiconductor i.MX 8M Plus Reference Manual to access and configure these registers.

eMMC Flash Memory (U4)

The main flash memory of the i.MX 8M Plus is eMMC and is populated at U4. The eMMC device is programmable with 1.8 V. No dedicated programming voltage is required. The eMMC Flash memory is connected to the SD3 interface of the i.MX 8M Plus.

For more information about the eMMC Flash interface, please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual.

I2C EEPROM (U10)

The phyCORE‑i.MX 8M Plus is populated with a non-volatile 4 kB I2C EEPROM at U10. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I2C port 1 on the i.MX 8M Plus. The control registers for I2C port 1 are mapped between addresses 0x30A2 0000 and 0x30A3 0000. Please see the NXP Semiconductor i.MX 8M Plus Reference Manual for detailed information on the registers.

The three lower address bits are fixed to zero which means that the EEPROM can be accessed at I2C address 0x51. The EEPROM has a second address on 0x59, which is called Identification Page, and is reserved for internal PHYTEC uses only.

QSPI NOR Flash (U5)

The QSPI NOR Flash memory of the phyCORE-i.MX 8M Plus at U5 can be used to store configuration data or any other general-purpose data. It can also be used as a boot device and recovery boot device. The device is accessed through QSPIA SS0 on the i.MX 8 Plus. The control registers for QSPI are mapped between addresses 0x30BB 0000 and 0x30BB FFFF. Please see the NXP Semiconductor i.MX 8M Plus Reference Manual for detailed information on the registers.

As of the printing of this manual, these SPI Flash devices generally have a life expectancy of at least 100,000+ erase/program cycles and a data retention rate of 20 years. This makes the QSPI Flash a reliable and secure solution to store the first and second-level bootloaders.

Serial Interfaces

The phyCORE‑i.MX 8M Plus provides numerous dedicated serial interfaces, some of which are equipped with a transceiver to enable direct connection to external devices:

  1. One 4-bit SDIO interface (SD2) with controlled IO voltage
  2. One 8-bit SDIO interface (SD1)
  3. Four high-speed UARTs
  4. Two CAN-FD interfaces
  5. Two USB 3.0/2.0 Dual-Role interfaces with PHY
  6. Two 1Gbit Ethernet interfaces with TSN support (ENET1 with Ethernet transceiver on the phyCORE-i.MX 8 M Plus enabling a direct connection to an existing Ethernet network; ENET0 as RGMII Signals at logic-level at the signal pins instead)
  7. Three I2C interfaces
  8. Two Serial Peripheral Interfaces (SPI)
  9. Two SAI audio interface
  10. One SPDIF interface
  11. PCI Express x1 interfaces
  12. Two MIPI CSI-2 camera interfaces
  13. One MIPI DSI-2 display interface

Details for each of these serial interfaces and any applicable jumper configurations are below.

SDIO Interface

The SDIO interface can be used to connect external SD cards, eMMC, or any other device requiring SDIO interface (i.e WiFI, I/O expansion, etc.) The phyCORE bus features one SDIO interface. On the phyCORE‑i.MX 8M Plus, the interface signals extend from the first and second Ultra Secured Digital (SD1 and SD2) Host controller to the phyCORE-Connector. 

The table below shows the location of the different interface signals on the phyCORE-Connector. The MMC/SD/SDIO Host Controller is fully compatible with the SD Memory Card Specification 3.0. The interface supports SD cards with 3.3 V and 1.8 V I/O signals.

SDIO SD2 (4-bit)

SDIO SD2 is a 4-bit wide interface with controlled I/O-voltage to support high-speed modes that require 1.8 V I/O voltage. During runtime, the I/O voltage can be switched from 3.3 V (default) to 1.8 V by the processor via GPIO signal X_PMIC_SD_VSEL/GPIO1_IO04 which controls the PMIC integrated voltage regulator. X_VDDSW_SD2 will be used exclusively to supply an external SD or MicroSD memory card. X_VDDSW_SD2 is monitored by the PMIC load switch circuit for overcurrent and short circuits. For more details, please refer to the PMIC data sheet provided by NXP.

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

B36X_VDDSW_SD2VDD_3V33.3 VPWR_OControlled SD Card Supply Voltage
B37X_SD2_CD_BNVCC_SD21.8 V / 3.3 VISD2 Card Detect
B38X_SD2_WPNVCC_SD21.8 V / 3.3 VISD2 Write Protect
B39X_SD2_CMDNVCC_SD21.8 V / 3.3 VOSD2 Command
B40X_SD2_CLKNVCC_SD21.8 V / 3.3 VOSD2 Clock
B42X_SD2_DATA0NVCC_SD21.8 V / 3.3 VI/OSD2 Data 0
B43X_SD2_DATA1NVCC_SD21.8 V / 3.3 VI/OSD2 Data 1
B44X_SD2_DATA2NVCC_SD21.8 V / 3.3 VI/OSD2 Data 2
B45X_SD2_DATA3NVCC_SD21.8 V / 3.3 VI/OSD2 Data 3

SDIO Interface Pinout of SD2

SDIO SD1 (8-bit)

SDIO SD1 is an 8-bit wide interface. The I/O voltage is determined by VDD_IO which is statically configured for the system to 3.3 V or 1.8 V (refer to External Logic IO Supply Voltage).

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

B46X_SD1_RESET_BVDD_IO1.8 V / 3.3 VI/OSD1 Reset
B48X_SD1_CMDVDD_IO1.8 V / 3.3 VOSD1 Command
B49X_SD1_STROBEVDD_IO1.8 V / 3.3 VOSD1 Strobe
B50X_SD1_CLKVDD_IO1.8 V / 3.3 VOSD1 Clock
B51X_SD1_DATA0VDD_IO1.8 V / 3.3 VI/OSD1 Data 0
B52X_SD1_DATA1VDD_IO1.8 V / 3.3 VI/OSD1 Data 1
B53X_SD1_DATA2VDD_IO1.8 V / 3.3 VI/OSD1 Data 2
B55X_SD1_DATA3VDD_IO1.8 V / 3.3 VI/OSD1 Data 3
B56X_SD1_DATA4VDD_IO1.8 V / 3.3 VI/OSD1 Data 4
B57X_SD1_DATA5VDD_IO1.8 V / 3.3 VI/OSD1 Data 5
B58X_SD1_DATA6VDD_IO1.8 V / 3.3 VI/OSD1 Data 6
B59X_SD1_DATA7VDD_IO1.8 V / 3.3 VI/OSD1 Data 7

SDIO Interface Pinout of SD1

Universal Asynchronous Interfaces (UARTs)

The phyCORE‑i.MX 8M Plus provides four high-speed universal asynchronous interfaces. The following table shows the location of the signals on the phyCORE-Connector.

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A2

X_UART1_RXD

VDD_IO

1.8 V / 3.3 V

I

UART1 Receive Data

A3

X_UART1_TXD

VDD_IO

1.8 V / 3.3 V

O

UART1 Transmit Data







B2

X_UART2_RXD

VDD_IO

1.8 V / 3.3 V

I

UART2 Receive Data (A53 Debug)

B3

X_UART2_TXD

VDD_IO

1.8 V / 3.3 V

O

UART2 Transmit Data (A53 Debug)







A4

X_UART3_RXD

VDD_IO

1.8 V / 3.3 V

I

UART3 Transmit Data

A5

X_UART3_TXD

VDD_IO

1.8 V / 3.3 V

O

UART3 Receive Data







B4

X_UART4_RXD

VDD_IO

1.8 V / 3.3 V

I

UART4 Receive Data (M7 Debug)

B5

X_UART4_TXD

VDD_IO

1.8 V / 3.3 V

O

UART4 Transmit Data (M7 Debug)

UART Signal Locations

USB Interfaces

The phyCORE‑i.MX 8M Plus provides two USB 3.0/2.0 dual role interfaces, which support super-speed (5Bbit/s), high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) operation. The applicable interface signals can be found on the phyCORE‑Connector X1. If overcurrent and power enable signals are needed for the USB host interface, the functionality can be easily implemented with GPIOs.

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

C16

X_USB1_VBUS

VDD_3V3

3.3 V / 5V

I

USB 1 bus voltage detection (5 V compliant)

C17

X_USB1_ID

VDD_3V3

-

USB-I/O

(do not use, has no function in the CPU)

C18

X_USB1_D_N

VDD_3V3

-

USB_I/O

USB 1 Data-

C19

X_USB1_D_P

VDD_3V3

-

USB_I/O

USB 1 Data+

C21

X_USB1_TX_N

VDD_3V3

-

USB_I/O

USB 1 Transmit Data-

C22

X_USB1_TX_P

VDD_3V3

-

USB_I/O

USB 1 Transmit Data+

C23X_USB1_RX_NVDD_3V3

-

USB_I/O

USB 1 Receive Data-
C24X_USB1_RX_PVDD_3V3

-

USB_I/O

USB 1 Receive Data+

USB 1 Signal Locations

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

C26

X_USB2_VBUS

VDD_3V3

3.3 V / 5V

I

USB 2 bus voltage detection (5V compliant)

C27X_USB2_IDVDD_3V3-USB_I/O(do not use, has no function in the CPU)
C28

X_USB2_D_N

VDD_3V3-USB_I/O

USB 2 Data-

C29

X_USB2_D_P

VDD_3V3-USB_I/O

USB 2 Data+

C31

X_USB2_TX_N

VDD_3V3-USB_I/O

USB 2 Transmit Data-

C32

X_USB2_TX_P

VDD_3V3-USB_I/O

USB 2 Transmit Data+

C33

X_USB2_RX_NVDD_3V3-USB_I/OUSB 2 Receive Data-
C34X_USB2_RX_PVDD_3V3-USB_I/O

USB 2 Receive Data+

USB 2 Signal Locations

Ethernet Interfaces ENET0 and ENET1

The phyCORE‑i.MX 8M Plus provides two Ethernet Interfaces ENET0 and ENET1 with TSN support. Connection of the phyCORE‑i.MX 8M Plus to the world wide web or a local area network (LAN) is possible using the onboard GbE PHY at U6. It is connected to the RGMII interface of ENET1. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. Additionally, the RGMII interface of ENET0, which is available on the phyCORE‑Connector, can be used to connect an external PHY. (ENET0 RGMII Interface).

Note

Please note that only ENET1 has TSN support.

PHYTEC has chosen to make the ETH1 available as RGMII for customers to accommodate their individual needs when it comes to choosing the right PHY or switching components applicable to their network topology.

As an example, we have connected a TSN capable Ethernet Phy to ENET1 on the carrier board, which may be used for reference in your own design. See Ethernet (X8/X9) for details.

ENET1 Ethernet PHY (U6)

With an Ethernet PHY mounted at U6, the phyCORE‑i.MX 8M Plus has been designed for use in 10Base-T, 100Base-T, and 1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE‑Connector X1.

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

D47

X_ETH_A_N

--

ETH_I/O

Data A-

D48

X_ETH_A_P

--

ETH_I/O

Data A+

D49

X_ETH_B_N

--

ETH_I/O

Data B-

D50

X_ETH_B_P

--

ETH_I/O

Data B+

D52

X_ETH_C_N

--ETH_I/OData C-

D53

X_ETH_C_P

--

ETH_I/O

Data C+

D54

X_ETH_D_N

--

ETH_I/O

Data D-

D55

X_ETH_D_P

--ETH_I/OData D+
D57X_ETH_GPIO0VDD_1V81.8 VI/OGPIO0
D58X_ETH_GPIO1VDD_1V81.8 VI/OGPIO1
D59

X_ETH_LED0_LINK

--

OD

Link

D60

X_ETH_LED2_ACT

--

OD

Activity

Ethernet PHY Signal Locations

Ethernet Signal Locations of ENET1

The onboard GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct-connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface ENET1 of the i.MX 8M Plus. Please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (ETH_A±, ETH_B±, ETH_C±, ETH_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.

Warning

Please refer to the Ethernet PHY datasheet when designing the Ethernet transformer circuitry or request the schematic of the applicable carrier board (phyBOARD‑Pollux i.MX 8M Plus).

Reset of the Ethernet Controller

The reset input of the Ethernet PHY at U6 is connected to the system reset POR_B.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 8M Plus is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

ENET0 RGMII Interface

In order to use an external Ethernet PHY, the RGMII interface (ENET0) of the i.MX 8M Plus is brought out at phyCORE‑Connector X1. ENET0 is primarily used for TSN network operation. For that use case, an external TSN-ready ethernet switch device is used.

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level**

Signal Type

Description

A15

X_ENET_MDIO

VDD_1V81.8 VI/OManagement Data

A17

X_ENET_RGMII_TD0

VDD_1V81.8 V
OTransmit Data 0

A18

X_ENET_RGMII_TD1

VDD_1V81.8 VOTransmit Data 1

A19

X_ENET_RGMII_TD2

VDD_1V81.8 V

O

Transmit Data 2

A20

X_ENET_RGMII_TD3

VDD_1V81.8 VOTransimt Data 3

A22

X_ENET_RGMII_TX_CTL

VDD_1V81.8 VOTransmit Control
A23

X_ENET_RGMII_TXC

VDD_1V81.8 VOTransmit Clock

A24

X_ENET_RGMII_RX_CTL

VDD_1V81.8 V

I

Receive Control

A25

X_ENET_RGMII_RXC

VDD_1V81.8 V

I

Receive Clock

A27

X_ENET_RGMII_RXD0

VDD_1V81.8 V

I

Receive Data 0

A28

X_ENET_RGMII_RXD1

VDD_1V81.8 V

I

Receive Data 1

A29

X_ENET_RGMII_RXD2

VDD_1V81.8 V

I

Receive Data 2

A30

X_ENET_RGMII_RXD3

VDD_1V81.8 V

I

Receive Data 3

A32

X_ENET_MDC

VDD_1V81.8 VOManagement Clock

ENET0 RGMII Interface Signal Locations

SPI Interface

The Serial Peripheral Interface (SPI) is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI on the phyCORE‑Connector X1. The SPI provides one chip select signal for each interface. The Enhanced Configurable SPI (eCSPI) of the i.MX 8M Plus has three separate modules (eCSPI1, eCSPI2, and eCSPI3) which support clock rates of up to 60 MHz. The interface signals of the first and second modules (eCSPI1, eCSPI2) are made available on the phyCORE-Connector. These modules are master/slave configurable. The following table lists the SPI signals on the phyCORE-Connector.

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

B26

X_ECSPI1_SS0

VDD_IO

1.8 V / 3.3 V

O

eCSPI1 Chip Select

B27

X_ECSPI1_MOSI

VDD_IO

1.8 V / 3.3 V

I/O

eCSPI1 Master Out

B28

X_ECSPI1_MISO

VDD_IO

1.8 V / 3.3 V

I/O

eCSPI1 Master In

B29

X_ECSPI1_SCLK

VDD_IO

1.8 V / 3.3 V

O

eCSPI1 Clock







B31

X_ECSPI2_SS0

VDD_IO1.8 V / 3.3 VOeCSPI2 Chip Select

B32

X_ECSPI2_MOSI

VDD_IO

1.8 V / 3.3 V

I/O

eCSPI2 Master Out

B33

X_ECSPI2_MISO

VDD_IO

1.8 V / 3.3 V

I/O

eCSPI2 Master In

B34

X_ECSPI2_SCLK

VDD_IO1.8 V / 3.3 VOeCSPI2 Clock

SPI Interface Signal Locations

I2C Interface

The Inter-Integrated Circuit (I2C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 8M Plus contains four identical and independent Multimaster fast-mode I2C modules. The interface of 3 modules is available on the phyCORE-Connector X1. I2C1 is reserved for controlling on the SOM. 

Tip

To ensure the proper functioning of the I2C interface, external pull resistors matching the load at the interface must be connected. There are no pull-up resistors mounted on the module. For detailed information on the voltage levels for the pull-up resistors, please refer to the i.MX 8M Plus Datasheet.

The following table lists the I2C ports on the phyCORE-Connector:

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage Domain

Signal Level

Signal Type

Description

B13

X_I2C2_SCL

VDD_IO

1.8 V / 3.3 V

I/OD

I2C2 Clock

B14

X_I2C2_SDA

VDD_IO

1.8 V / 3.3 V

I/OD

I2C2 Data







B15

X_I2C3_SCL

VDD_IO

1.8 V / 3.3 V

I/OD

I2C3 Clock

B16

X_I2C3_SDA

VDD_IO

1.8 V / 3.3 V

I/OD

I2C3 Data







E11

X_I2C4_SCL

VDD_IO

1.8 V / 3.3 V

I/OD

I2C4 Clock

E12

X_I2C4_SDA

VDD_IO1.8 V / 3.3 VI/ODI2C4 Data

I2C Interface Signal Locations

Audio Interface

 The i.MX 8M Plus supports multiple audio interfaces as listed below:

InterfaceRX Data LineTX Data Line
SAI-122
SAI-211
SAI-311
SAI-540
SPDIF-111

phyCORE-i.MX 8M Plus Audio Interfaces

I2S Audio Interface (SAI)

The phyCORE-i.MX 8M Plus features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-Connector X1. 

The tables below show the signal locations for each SAI and SPDIF interface.

SAI1 Interface

Warning

** SAI1 and SAI5 have fixed 1.8 V I/O voltage levels.

SAI1 is originally an 8-bit wide interface, but some of the signals are used dedicated for the Ethernet RGMII interface of ENET1, which is connected to the on-board PHY U6

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level**

Signal Type

Description

A7X_SAI1_MCLKVDD_1V81.8VI/OSAI1 MCLK

A8

X_SAI1_TXD6

VDD_1V8

1.8V

I/O

SAI1 TXD6 is connected to X_PMIC_IRQ_B signal via R131 and acts for interrupt recognition for PMIC events.

A9

X_SAI1_TXD7

VDD_1V81.8VI/OSAI1 TXD7
A10X_SAI1_RXFSVDD_1V81.8VI/OSAI1 RXFS
A12X_SAI1_RXCVDD_1V81.8VI/OSAI1 RXC
A13X_SAI1_RXD0VDD_1V81.8V

I/O

SAI1 RXD0
A14X_SAI1_RXD1VDD_1V81.8VI/OSAI1 RXD1

SAI1 Interface Signal Locations

SAI2 Interface

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A33

X_SAI2_MCLK

VDD_IO

1.8V / 3.3 V

I/O

SAI2 MCLK

A34

X_SAI2_TXFS

VDD_IO1.8V / 3.3 V

I/O

SAI2 TXFS

A35

X_SAI2_TXC

VDD_IO

1.8V / 3.3 V

I/O

SAI2 TXC

A37

X_SAI2_TXD0

VDD_IO

1.8V / 3.3 V

I/O

SAI2 TXD0

A38

X_SAI2_RXFS

VDD_IO

1.8V / 3.3 V

I/O

SAI2 RXFS

C20

X_SAI2_RXC

VDD_IO

1.8V / 3.3 V

I/O

SAI2 RXC

C22

X_SAI2_RXD0

VDD_IO

1.8V / 3.3 V

I/O

SAI2 RXD0

SAI2 Interface Signal Locations

SAI3 Interface

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

B18

X_SAI3_MCLK

VDD_IO

1.8V / 3.3 V

I/O

SAI3 MCLK

B19

X_SAI3_TXFS

VDD_IO1.8V / 3.3 V

I/O

SAI3 TXFS

B20

X_SAI3_TXC

VDD_IO

1.8V / 3.3 V

I/O

SAI3 TXC

B21

X_SAI3_TXD

VDD_IO

1.8V / 3.3 V

I/O

SAI3 TXD

B22

X_SAI3_RXFS

VDD_IO

1.8V / 3.3 V

I/O

SAI3 RXFS

B23

X_SAI3_RXC

VDD_IO

1.8V / 3.3 V

I/O

SAI3 RXC

B24

X_SAI3_RXD

VDD_IO

1.8V / 3.3 V

I/O

SAI3 RXD

SAI3 Interface Signal Locations

SAI5 Interface

Warning

** SAI1 and SAI5 have fixed 1.8 V I/O voltage level.

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level**

Signal Type

Description

E18

X_SAI5_RXD3

VDD_1V8

1.8V

I/O

SAI5 RXD3

E19

X_SAI5_RXD2

VDD_1V81.8V

I/O

SAI5 RXD2

E20

X_SAI5_RXD1

VDD_1V8

1.8V

I/O

SAI5 RXD1

E21

X_SAI5_RXD0

VDD_1V8

1.8V

I/O

SAI5 RXD0

E22

X_SAI5_RXC

VDD_1V8

1.8V

I/O

SAI5 RXC

E23

X_SAI5_RXFS

VDD_1V8

1.8V

I/O

SAI5 RXFS

E24

X_SAI5_MCLK

VDD_1V8

1.8V

I/O

SAI5 MCLK

SAI5 Interface Signal Locations

SPDIF Interface

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

E14

X_SPDIF_RX

VDD_IO1.8V / 3.3 V

I

SPDIF RX

E15

X_SPDIF_TX

VDD_IO

1.8V / 3.3 V

O

SPDIF TX

E16

X_SPDIF_EXT_CLK

VDD_IO

1.8V / 3.3 V

I

SPDIF Ext. CLK

SPDIF Interface Signal Locations

PCI Express Interface

The one 1-lane PCI Express interfaces of the phyCORE‑i.MX 8M Plus provides PCIe Gen. 2.0 functionality which supports 5 Gbit/s operations. Furthermore, the interfaces are fully backward compatible with the 2.5 Gbit/s Gen. 1.1 specifications. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented with GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Pollux) for a circuit example.

The position of the PCIe signals on the phyCORE‑Connector X1 is shown below:

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

D27

X_PCIE_TXN_N

VDDA_1V8

LVDS

PCIe_O

PCIe1 TXN-

D28

X_PCIE_TXN_P

VDDA_1V8

LVDS

PCIe_O

PCIe1 TXN+

D29

X_PCIE_RXN_N

VDDA_1V8

LVDS

PCIe_I

PCIe1 RXN-

D30

X_PCIE_RXN_P

VDDA_1V8

LVDS

PCIe_I

PCIe1 RXN+

D32

X_PCIE_REF_PAD_CLK_N

VDDA_1V8

LVDS

PCIe_I/O

PCIe1 Ref CLK- Input

D33

X_PCIE_REF_PAD_CLK_P

VDDA_1V8

LVDS

PCIe_I/O

PCIe1 Ref CLK+ Input

PCIe Interface Signal Locations

General Purpose I/Os

All pins not used by any of the other interfaces specifically described in this manual and can be used as GPIO without harming other features of the phyCORE‑i.MX 8M Plus. These pins are shown below:

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

D14X_GPIO1_IO00VDD_IO1.8V / 3.3 VI/OGPIO1_IO00
D15X_GPIO1_IO01VDD_IO1.8V / 3.3 VI/OGPIO1_IO01
C12X_PMIC_WDOG_B/GPIO1_IO02VDD_IO1.8V / 3.3 VI/OGPIO1_IO02 is used to trigger the PMIC WDOG_B input from the i.MX 8M Plus to perform a "cold reset".
D16X_GPIO1_IO03VDD_IO1.8V / 3.3 VI/OGPIO1_IO03
D17X_PMIC_SD_VSEL/GPIO1_IO04VDD_IO1.8V / 3.3 VOGPIO1_IO04 is on-board used to switch the NVCC_SD2 I/O voltage via the PMIC U3 from 3.3 V to 1.8 V for the high-speed data rates. Low means NVCC_SD2 = 3.3 V and high 1.8 V.
D18X_GPIO1_IO05VDD_IO1.8V / 3.3 VI/OGPIO1_IO05 is output high during reset and changes to input with PU after reset.
D20X_GPIO1_IO06VDD_IO1.8V / 3.3 VI/OGPIO1_IO06
D21X_GPIO1_IO06VDD_IO1.8V / 3.3 VI/OGPIO1_IO07
E2X_nETHPHY_INT/GPIO1_IO15VDD_IO1.8V / 3.3 VI/OGPIO1_15 is connected to the nINT output of the Ethernet PHY U6 for supporting interrupt connection to the i.MX 8M Plus.
E3X_GPIO1_IO14VDD_IO1.8V / 3.3 VI/OGPIO1_14
E4X_GPIO1_IO13VDD_IO

1.8V / 3.3 V

I/O

GPIO1_13

E5X_GPIO1_IO12VDD_IO1.8V / 3.3 VI/OGPIO1_12
E6X_GPIO1_IO11VDD_IO

1.8V / 3.3 V

I/O

GPIO1_11

E8X_GPIO1_IO10VDD_IO

1.8V / 3.3 V

I/O

GPIO1_10

E9X_GPIO1_IO09VDD_IO

1.8V / 3.3 V

I/O

GPIO1_09

E10X_GPIO1_IO08VDD_IO1.8V / 3.3 VI/OGPIO1_08

GPIO Pin Locations

Besides these pins, most of the i.MX 8M Plus signals which are connected directly to the module connector can be configured to act as GPIOs, due to the multiplexing functionality of most controller pins. Normally, pins with signal type I/O are able to work as a GPIO.

GPIO Changing I/O Voltage

I/O voltage can be configured to 3.3 V or 1.8 V. Please refer to section External Logic IO Supply Voltage. Be aware that changing the I/O voltage alters all interfaces which are in reference to VDD_IO.

Debug Interface

The phyCORE‑i.MX 8M Plus is equipped with a JTAG interface to download program code into the external flash, internal controller RAM, or any debugging programs being executed. The location of the JTAG pins on the phyCORE-Connector X1 are below:

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

B7

X_JTAG_TCK

VDD_IO

1.8V / 3.3 V

I

JTAG clock signal. Has 10 kOhm pull-down.

B8

X_JTAG_TDI

VDD_IO

1.8V / 3.3 V

I

JTAG data in signal

B9

X_JTAG_TDO

VDD_IO

1.8V / 3.3 V

O

JTAG data out signal

B10

X_JTAG_TMS

VDD_IO

1.8V / 3.3 V

I

JTAG test mode select signal

B11

X_JTAG_MOD

VDD_IO

1.8V / 3.3 V

I

JTAG mode signal. To enable JTAG mode, this signal must be driven high. Signal has 10 kOhm pull-down.

Debug Interface Signal Locations

UART Debug

The default debug UART Interfaces (TTL) is UART2 for Cortex-A53 Cores and UART4 for Cortex-M7 Core. UART2 is accessible on connector X1 pins B2 (RXD) and B3 (TXD) and UART4 on pins B4 (RXD) and B5 (TXD).

For more information also refer to Universal Asynchronous Interfaces (UARTs).

Display Interfaces

High Definition Multimedia Interface (HDMI)

The High Definition Multimedia Interface (HDMI) of the phyCORE-i.MX 8M Plus is compliant with HDMI 2.0a for up to 1920x1080 at 60 Hz display resolutions. Please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual for more information.

The location of the HDMI signals on the phyCORE-Connector X1 are shown below:

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A42X_HDMI_DDC_SCLVDD_IO1.8V / 3.3 V

I/O

Display Data Channel SCL
A43X_HDMI_DDC_SDAVDD_IO1.8V / 3.3 VI/ODisplay Data Channel SDA
A44X_HDMI_HPDVDD_IO1.8V / 3.3 VI/OHot Plug Detect
A45X_HDMI_CECVDD_IO1.8V / 3.3 VI/OConsumer Electronics Control
A46X_HDMI_EARC_AUXVDDA_1V81.8 VIHDMI EARC AUX

A48

X_HDMI_EARC_N_HPD

VDDA_1V8

LVDS

HDMI_I

HDMI EARC- / HPD

A49

X_HDMI_EARC_P_UTIL

VDDA_1V8

LVDS

HDMI_I

HDMI EARC+ / UTIL

A50

X_HDMI_TX0_N

VDDA_1V8

LVDS

HDMI_O

HDMI TX0-

A51

X_HDMI_TX0_P

VDDA_1V8

LVDS

HDMI_O

HDMI TX0+

A53

X_HDMI_TXC_N

VDDA_1V8

LVDS

HDMI_O

HDMI TX Clock -

A54

X_HDMI_TXC_P

VDDA_1V8

LVDS

HDMI_O

HDMI TX Clock +

A56

X_HDMI_TX1_N

VDDA_1V8

LVDS

HDMI_O

HDMI TX1-

A57

X_HDMI_TX1_P

VDDA_1V8LVDSHDMI_OHDMI TX1+

A58

X_HDMI_TX2_N

VDDA_1V8LVDSHDMI_OHDMI TX2-

A59

X_HDMI_TX2_P

VDDA_1V8LVDSHDMI_OHDMI TX2+

 HDMI Interface Signal Locations

Low Voltage Differential Signal Display Interface (LVDS)

The phyCORE-i.MX 8M Plus offers one LVDS display interface which supports two output channels.

The locations of the LVDS signals are shown below:

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

LVDS channel 1

C36

X_LVDS1_D0_N

VDDA_1V8

LVDS

LVDS_O

LVDS1 DATA0-

C37

X_LVDS1_D0_P

VDDA_1V8

LVDS

LVDS_O

LVDS1 DATA0+

C38

X_LVDS1_D1_N

VDDA_1V8

LVDS

LVDS_O

LVDS1 DATA1-

C39

X_LVDS1_D1_P

VDDA_1V8

LVDS

LVDS_O

LVDS1 DATA1+

C41

X_LVDS1_CLK_N

VDDA_1V8

LVDS

LVDS_O

LVDS1 Clock-

C42

X_LVDS1_CLK_P

VDDA_1V8

LVDS

LVDS_O

LVDS1 Clock+

C43

X_LVDS1_D2_N

VDDA_1V8

LVDS

LVDS_O

LVDS1 DATA2-

C44

X_LVDS1_D2_P

VDDA_1V8LVDSLVDS_OLVDS1 DATA2+

C46

X_LVDS1_D3_N

VDDA_1V8LVDSLVDS_OLVDS1 DATA3-

C47

X_LVDS1_D3_P

VDDA_1V8LVDSLVDS_OLVDS1 DATA3+
LVDS channel 0

C48

X_LVDS0_D0_N

VDDA_1V8

LVDS

LVDS_O

LVDS0 DATA0-

C49

X_LVDS0_D0_P

VDDA_1V8

LVDS

LVDS_O

LVDS0 DATA0+

C51

X_LVDS0_D1_N

VDDA_1V8

LVDS

LVDS_O

LVDS0 DATA1-

C52

X_LVDS0_D1_P

VDDA_1V8

LVDS

LVDS_O

LVDS0 DATA1+

C53

X_LVDS0_CLK_N

VDDA_1V8

LVDS

LVDS_O

LVDS0 Clock-

C54

X_LVDS0_CLK_P

VDDA_1V8

LVDS

LVDS_O

LVDS0 Clock+

C56

X_LVDS0_D2_N

VDDA_1V8

LVDS

LVDS_O

LVDS0 DATA2-

C57

X_LVDS0_D2_P

VDDA_1V8LVDSLVDS_OLVDS0 DATA2+

C58

X_LVDS0_D3_N

VDDA_1V8LVDSLVDS_OLVDS0 DATA3-

C59

X_LVDS0_D3_P

VDDA_1V8LVDSLVDS_OLVDS0 DATA3+

Display Interface LVDS Signal Locations

MIPI-DSI Display Interface (DSI)

The phyCORE-i.MX 8M Plus offers one MIPI-DSI display interface. MIPI-DSI has 4 channels, supporting one display with a resolution of up to 1920 x 1080 at 60Hz.

The locations of the MIPI-DSI signals are shown below:

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

F6

X_MIPI_DSI_D0_N

VDDA_1V8

LVDS

DSI2_O

DSI DATA0-

F7

X_MIPI_DSI_D0_P

VDDA_1V8

LVDS

DSI2_O

DSI DATA0+

F8

X_MIPI_DSI_D1_N

VDDA_1V8

LVDS

DSI2_O

DSI DATA1-

F9

X_MIPI_DSI_D1_P

VDDA_1V8

LVDS

DSI2_O

DSI DATA1+

F11

X_MIPI_DSI_CLK_N

VDDA_1V8

LVDS

DSI2_O

DSI Clock-

F12

X_MIPI_DSI_CLK_P

VDDA_1V8

LVDS

DSI2_O

DSI Clock+

F13

X_MIPI_DSI_D2_N

VDDA_1V8

LVDS

DSI2_O

DSI DATA2-

F14

X_MIPI_DSI_D2_P

VDDA_1V8LVDSDSI2_ODSI DATA2+

F16

X_MIPI_DSI_D3_N

VDDA_1V8LVDSDSI2_ODSI DATA3-

F17

X_MIPI_DSI_D3_P

VDDA_1V8LVDSDSI2_ODSI DATA3+

Display Interface MIPI / DSI Signal Locations

Camera Connections

The phyCORE-i.MX 8M Plus offers 2 MIPI-CSI interfaces to connect digital cameras with a resolution of up to 12MP. The two MIPI/CSI‑2 camera interfaces of the i.MX 8M Plus extends to the phyCORE‑Connector X1 with 4 data lanes and one clock lane.

The locations of the MIPI-CSI signals are shown below:

SOM Connector Pin / phyBOARD-Pollux Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

D34

X_MIPI_CSI1_D0_N

VDDA_1V8

LVDS

CSI2_I

CSI1 DATA0-

D35

X_MIPI_CSI1_D0_P

VDDA_1V8

LVDS

CSI2_I

CSI1 DATA0+

D37

X_MIPI_CSI1_D1_N

VDDA_1V8

LVDS

CSI2_I

CSI1 DATA1-

D38

X_MIPI_CSI1_D1_P

VDDA_1V8

LVDS

CSI2_I

CSI1 DATA1+

D39

X_MIPI_CSI1_CLK_N

VDDA_1V8

LVDS

CSI2_I

CSI1 Clock-

D40

X_MIPI_CSI1_CLK_P

VDDA_1V8

LVDS

CSI2_I

CSI1 Clock+

D42

X_MIPI_CSI1_D2_N

VDDA_1V8

LVDS

CSI2_I

CSI1 DATA2-

D43

X_MIPI_CSI1_D2_P

VDDA_1V8LVDSCSI2_ICSI1 DATA2+

D44

X_MIPI_CSI1_D3_N

VDDA_1V8LVDSCSI2_ICSI1 DATA3-

D45

X_MIPI_CSI1_D3_P

VDDA_1V8LVDSCSI2_ICSI1 DATA3+






F18

X_MIPI_CSI1_D3_N

VDDA_1V8

LVDS

CSI2_I

CSI1 DATA3-

F19

X_MIPI_CSI1_D3_P

VDDA_1V8

LVDS

CSI2_I

CSI1 DATA3+

F21

X_MIPI_CSI1_D2_N

VDDA_1V8

LVDS

CSI2_ICSI1 DATA2-

F22

X_MIPI_CSI1_D2_P

VDDA_1V8

LVDS

CSI2_I

CSI1 DATA2+

F23

X_MIPI_CSI1_CLK_N

VDDA_1V8

LVDS

CSI2_I

CSI1 Clock-

F24

X_MIPI_CSI1_CLK_P

VDDA_1V8

LVDS

CSI2_I

CSI1 Clock+

F26

X_MIPI_CSI1_D1_N

VDDA_1V8

LVDS

CSI2_I

CSI1 DATA1-

F27

X_MIPI_CSI1_D1_P

VDDA_1V8LVDSCSI2_ICSI1DATA1+

F28

X_MIPI_CSI1_D0_N

VDDA_1V8LVDSCSI2_ICSI1 DATA0-

F29

X_MIPI_CSI1_D0_P

VDDA_1V8LVDSCSI2_ICSI1 DATA0+

Camera Interface MIPI / CSI-2 Signal Locations

RTC

The i.MX 8M Plus has an onboard, externally mounted RTC. The RV-3028 is the newest generation of RTC from Micro Crystal with an extremely low backup current of typically 40nA at 25 degrees. PHYTEC uses the most optimal implementation in each phyCORE design to give the most optimal usage for all customers.

The RTC is accessible over I2C1 on Address 0x52. In a normal operation state, the RTC power is supplied from the SOM voltage VDD_3V3. If the SOM is not powered and RTC backup is needed, the VBACKUP Pin of the RTC can be supplied over the VBAT pin X1-C9.

The RTC provides an interrupt output signal (X_RTC_INT) which is fed to the module connector X1-C10. This signal is an open drain (OD). The onboard pull-up resistor R12 is, by default, not mounted. To use the X_RTC_INT signal, add an external pull-up resistor (e.g. 10k) to an appropriate I/O voltage level (e.g. VBAT).

Furthermore, the RTC is able to supply a programmable clock output signal (push-pull) RTC_CLKOUT. Frequencies of 1/32/64/1024/8192 Hz and 32.768 Hz (default) are programmable. The RTC_CLKOUT signal is fed via soldering jumper J1 to module connector at X1-D12. For a detailed description of the programming capabilities of the RTC, refer to the Micro Crystal RV-3020 App-Manual.

Temperature Sensors

The phyCORE-i.MX 8M Plus supports two internally senorsed thermal zones in the i.MX 8M Plus CPU as well as 4 externally sensored thermal zones for monitoring board-level temperatures. The presence of the sensors depends on the delivery variant of the module.

The external temperature sensors are located at the following positions.

Temperature Sensor Locations

The TMP102 temperature sensor devices used are connected to I2C1 bus. TMP102 measures temperatures from -40 °C to +125 °C. For a more detailed description of TMP102, refer to the Texas Instruments TMP102 Datasheet.

SensorI2C slave address
U110x48
U120x49
U130x4A
U140x4B

I2C1 Temperature Sensor Slave Addresses

CPU Core Frequency Scaling

The phyCORE-i.MX 8M Plus on the phyBOARD‑Pollux is able to scale the clock frequency and voltage. This is used to save power and reduce heat dissipation when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as 'Dynamic Voltage and Frequency Scaling' (DVFS).

The phyCORE-i.MX 8M Plus BSP supports the DVFS feature. The Linux kernel provides a DVFS framework that allows each CPU core to have a min/max frequency as well as the applicable voltage and a governor that governs these values depending on the system load. Depending on the i.MX 8M Plus variant used, several different frequencies are supported. Further details on how to configure this governor can be found in the phyCORE-i.MX 8M Plus BSP Manual.

Technical Specifications

Warning

Due to changes in functionality and design that are currently being developed, there are several values that cannot be determined in time for the release of this manual. All values with "TBD (To Be Determined)" are currently being evaluated. These values will be added to future manual editions.

The module’s profile is max. 6 mm thick, with a maximum component height of 1.0 mm on the bottom (connector) side of the PCB and approximately 1.2 mm on the top (microcontroller) side. The board itself is approximately 1.6 mm thick. The phyCORE-i.MX 8M Plus Footprint can be seen below.

Additional specifications:

Dimensions:40 x37 mm
Weight:11 g
Storage Temperature:-40 to +85deg
Operating Temperature:i.MX8M Plus Product Temperature Grades
Humidity:TBD
Operating Voltage:3.2 V .. 3.5 V
Power Consumption:phyCORE-i.MX8M Plus Power Consumption

Technical Specifications

These specifications describe the standard configuration of the phyCORE‑i.MX 8M Plus as of the printing of this manual.

phyCORE-i.MX 8M Plus Power Consumption

The values listed in the table below are a guideline to determine the required dimensions of the power supply circuitry on a carrier board. They do not take application-specific load situations into account. These values have been generated by looking at the maximum power consumption measured using different load scenarios and adding a voltage source of 3.3 V.  These values are based on internal PHYTEC testing. Customers need to consider their application power requirements to ensure they do not generate a load greater than the values listed here

Required Supply Voltage3.3 V
Ramp-Up Time (10%-90%)
100µs to 10ms
Allowed Tolerance of Supply Voltage3.2 V .. 3.5 V
Max. current consumption4 A

phyCORE-i.MX 8M Plus Power Consumption

For power measurement, a SOM with 2 GB RAM, 16GB eMMC, ETH0, and an IMX8ML8DVNLZAA was used together with PD19.1.0.


Case 1Case 2Case  3Case 4Case 5Case 6Case 7
eMMC-BootXXXXXXX
Scenario 2 (tbd)
XXXXXXTBD
Scenario 3 (tbd)XXXXXTBDTBD
Scenario 4 (tbd)XXXXTBDTBDTBD
Scenario 5 (tbd)XXXTBDTBDTBDTBD
Scenario 6 (tbd)XXTBDTBDTBDTBDTBD
Power ConsumptionTBDTBDTBDTBDTBDTBD1.7 W

phyCORE-i.MX 8M Plus Power Consumption Test Scenarios

Additionally, there are some values that cannot be tested. Situations such as suspending to RAM, suspend freeze, and standby mode must be tested on a case by case basis to ensure the application's power consumption stays within the guideline stated above.

Tip

For further information and assistance regarding your application's power consumption, please contact PHYTEC sales.

Product Temperature Grades

Warning

The right temperature grade for the module greatly depends on the use case. It is necessary to determine if the use case suits the temperature range of the chosen module (see below). A heat spreader can be used if temperature compensation is required.

The feasible operating temperature of the SOM highly depends on the use case of your software application. Modern high-performance microcontrollers and other active parts as the ones described within this manual are usually rated by qualifications based on tolerable junction or case temperatures. Therefore, making a general statement about minimum or maximum ambient temperature ratings for the described SOM is not possible.

However, the above-mentioned parts are available in different temperature qualification levels by the producers. We offer our SOM's in different configurations, making use of those temperature qualifications. To indicate which level of temperature qualification is used for active and passive parts of a SOM configuration, we have categorized our SOMs into three temperature grades.

The table below describes these grades in detail. This table describes a set of components that, in combination, add up to a useful set of product options with different temperature grades. This enables us to make use of cost optimizations depending on the required temperature range.

In order to determine the right temperature grade and whether the minimum or maximum qualification levels are met within an application, the following conditions must be defined by considering the use case:

  • Determined the processing load for the given software use case
  • Maximum temperature ranges of components (table below)
  • Power consumption resulting from a baseload and the calculating power required (in consideration of peak loads as well as time periods for system cooldown)
  • Surrounding temperatures and existing airflow in case the system is mounted into a housing
  • Heat resistance of the heat dissipation paths within the system along with the considered usage of a heat spreader or a heat sink to optimize heat dissipation

Product Temperature
Grade

Controller  Range
(Junction Temperature)

RAM
(Case Temperature)
Other
(Ambient)

I

Industrial: -40 °C to +105 °C

Industrial: -40 °C to +95 °C

Industrial: -40 °C to +85 °C

C

Commercial: 0 °C to +95 °C

Consumer: 0 °C to +95 °C

Consumer: 0 °C to +70 °C

Product Temperature Grades

Connectors on the phyCORE-i.MX 8M Plus

ManufacturerSamtec
phyCORE-Connector (X1 2x120+60 pins)

240 pins main connectors X1-A/B and X1-C/D

Two main connectors with 2x60 pins each.

Samtec part number (lead-free)BSH-060-01-L-D-A-TR / REF-177857-02
PHYTEC part number (lead-free)VB211
60 pins extension connectors X1-E/FOne extension connector with 2x 30 pins.
Samtec part number (lead-free)BSH-030-01-L-D-A / REF-177855-01
PHYTEC part number (lead-free)VB118

Information on the receptacle sockets that correspond to the connectors populating the underside of the phyCORE-i.MX 8 is provided below. The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board. In order to get the exact spacing, the maximum component height (1 mm) on the bottom side of the phyCORE must be subtracted.

Mating Connector

ManufacturerSamtec
To connect phyCORE-Connector (X1) with 5mm distance board-to-board

240 pins main connectors X1-A/B and X1-C/D

Two main connectors with 2x60 pins each.

Samtec part number (lead-free)BTH-060-01-L-D-A-K-TR / REF-177862-03
PHYTEC part number (lead-free)VM240
60 pins extension connectors X1-E/FOne extension connector with 2x 30 pins.
Samtec part number (lead-free)BTH-030-01-L-D-A-K-TR
PHYTEC part number (lead-free)VM368

Please refer to the corresponding data sheets and mechanical specifications provided by Samtec (www.samtec.com).

Hints for Integrating and Handling the phyCORE‑i.MX 8M Plus

Integrating the phyCORE-i.MX 8M Plus

Besides this hardware manual, more information is available to facilitate the integration of the phyCORE‑i.MX 8M Plus into customer applications.

  1. The design of the phyBOARD‑Pollux can be used as a reference for any customer application.
  2. Many answers to common questions can be found at: https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-plus-download/ or https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-plus-download/
  3. The link “Carrier Board” within the category Dimensional Drawing leads to the layout data phyCORE-i.MX 8M Plus Footprint. It is available in different file formats. The use of this data allows the user to integrate the phyCORE-i.MX 8M Plus SOM as a single component into their design.
  4. Different support packages are available for support in all stages of embedded development. Please visit http://www.phytec.de/de/support/support-pakete.html or https://www.phytec.eu/support/support-packages/ or contact our sales team for more details.

Handling the phyCORE-i.MX 8M Plus

phyCORE Module Modifications

The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station, or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Warning

If any modifications to the module are performed, regardless of their nature, the manufacturer guarantee may be null and void.

Integrating the phyCORE into a Target Application

Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. At a minimum, all GND pin neighboring signals which are being used in the application circuitry should be connected to GND.

Tip

Specific details may need to be considered when designing a customer-specific carrier board. For design information on carrier board components, please check the Design Considerations in each component section of phyCORE-i.MX 8M Plus on the phyBOARD-Pollux. Be aware that not all components need to be considered when designing your own carrier board.

phyCORE-i.MX 8M Plus on the phyBOARD-Pollux

Hardware Overview

The phyBOARD‑Pollux for phyCORE-i.MX 8M Plus is a low-cost, feature-rich software development platform supporting the NXP Semiconductors i.MX 8M Plus microcontroller. Due to numerous standard interfaces, the phyBOARD‑Pollux i.MX 8M Plus can serve as the bedrock for any application. At the core of the phyBOARD‑Pollux is the PCM-070/phyCORE-i.MX 8M Plus System On Module (SOM) containing the processor, LPDDR4 RAM, eMMC Flash, power regulation, supervision, transceivers, and other core functions required to support the i.MX 8M Plus processor. Surrounding the SOM is the PB-03123/phyBOARD‑Pollux carrier board, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals.

The PCM-070 System On Module connects to the phyBOARD‑Pollux carrier board using 3 Samtec BTH connectors. This solution offers a highly flexible Single Board Computer for the i.MX 8M Plus processor, while maintaining most of the advantages of the SOM concept.

phyBOARD-Pollux Concept

PHYTEC phyCORE carrier boards are fully equipped with all mechanical and electrical components necessary for a fast, secure start-up. Subsequent communication to and programming of applicable PHYTEC System on Modules (SOM) is made easy. phyCORE carrier boards are designed for evaluation, testing, and prototyping PHYTEC System on Modules in laboratory environments prior to their use in customer designed applications.

This modular development platform concept includes the following components:

  • The phyCORE-i.MX 8M Plus Module populated with the i.MX 8M Plus microcontroller and all applicable SOM circuitry such as LPDDR4 SDRAM, eMMC-Flash, Ethernet-PHY, and PMIC, etc.
  • The phyBOARD-Pollux Carrier Board offers all essential components and connectors for a start-up including: a power supply for 24 V input voltage, interface connectors such as HDMI, USB, and Ethernet, which enable the use of the SOM’s interfaces with a standard cable.

The carrier board can also serve as a reference design for developing custom target hardware in which the phyCORE SOM can be deployed. Carrier board schematics are available under a Non-Disclosure Agreement (NDA). Reuse of carrier board circuitry enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

SBCplus Concept

The SBCplus concept was developed to meet the many, small differences in customer requirements with little development effort. This greatly reduces the time-to-market. The core of the SBCplus concept is the SBC design library (a kind of construction set) that consists of a large number of function blocks (so-called "building blocks") that are continuously being refined and updated.

Recombining these function blocks allows PHYTEC to develop a customer-specific SBC within a short time. We are able to deliver production-ready custom Single Board Computers within a few weeks at very low costs. The already developed SBCs, such as the phyBOARD-Pollux, each represent a combination of different customer wishes. This means all necessary interfaces are already available on the standard versions, allowing PHYTEC SBCs to be integrated into a large number of applications without modification.

For any necessary detail adjustment, extension connectors are available which enable a wide variety of functions to be added.

Tip

For further information, please contact PHYTEC sales.

phyBOARD-Pollux Features

The phyBOARD‑Pollux supports the following features:

  • Developed in accordance with PHYTEC's SBCplus concept (SBCplus Concept)
  • Populated with PHYTEC’s phyCORE-i.MX 8M Plus SOM
  • Dimensions of 160 mm × 73 mm
  • Boot from eMMC, SD Card, or over USB with the Serial Downloader
  • Max. 1.3 GHz core clock frequency and up to four cores (at I-Temp Kit Version)
  • 24 V power supply
  • 2GB RAM (at Kit Version)
  • 8GB eMMC (at Kit Version)
  • 32MB NOR (at Kit Version)
  • 4kB EEPROM
  • Two RJ45 jack for 10/100/1000 Mbps Ethernet
  • USB-PD (USB Power Delivery)
  • One USB 3.0 host interface connected to a USB 3.0 4-port HUB. The 3.0 interface is brought out to an upright USB Standard-A connector. The other 3 port are connected to the Mini PCI express connector, the Audio/Video connector, and the expansion connector[2]

  • One USB 3.0 host interface connected to phyCORE-i.MX 8M Plus Module
  • One Secure Digital / MultiMedia Memory Card interface brought out to a Micro-SD connector
  • One HDMI interface brought out to a standard Type-A connector
  • One MIPI-DSI brought out via an A/V Connector
  • Two MIPI-CSI-2 camera interfaces brought out as phyCAM-M interface
  • One PCI interface brought out to a Mini PCI Express connector
  • RS-232 and RS-485 multiprotocol transceiver supporting RS-232 including handshake, RS-485 Half-Duplex, and RS-485 Full-Duplex signals with data rates of up to 20 Mbps (RS-485) / 1 Mbps (RS-232) (2×5 pin header 2.54 mm)
  • Reset button
  • ON/OFF button
  • One multicolor LED
  • SAI Audio brought out via an A/V connector
  • Digital I/O via an Expansion Connector
  • JTAG via an Evaluation Adapter connected to the Expansion Connector
  • Expansion connector for different interfaces
    • I2C
    • SPI
    • UART
    • QSPI
    • USB
  • RTC
    • Goldcap Backup supply for RTC
  • Onboard measurement of SOM Power Consumption
  • Onboard TPM Security Chip
  • All processor interfaces available onboard (may be limited by predefined muxing)

Warning

2.

There is no protective circuit for the USB interfaces brought out at the Mini PCI Express connector, expansion connector. and A/V connectors.

Block Diagram

phyBOARD-Pollux Block Diagram

Temperature Range

The vast majority of components on the phyBOARD Pollux have an operating temperature range of -40 °C to 85 °C. The following components are the exception:

BOM No.Component DescriptionTemperature RangeAdvice
C398GoldCap for RTC Backup-20 °C to 85 °CAs alternative C399 with -40°C to 85 °C can be mounted
X5Dual USB Connector-20 °C to 85 °CThere is a drop-in replacement available with -40 °C to 85 °C
X20HDMI Connector-25 °C to 85 °CThere is no replacement available
X24LVDS1 Data Connector-35 °C to 85 °CThere is no replacement available
X26LVDS1 Backlight Connector-25 °C to 85 °CThere is no replacement available
X7Micro SD-Card Slot-25 °C to 85 °CThe SD-Card slot can be used in the range of -40 °C to 85 °C without mechanical changes
U24Trusted Platform Module (TPM)-20 °C to 85 °CThere is a drop-in replacement available with -40 °C to 85 °C

For this reason, the operation temperature range for the kit variant is: -20 °C to 85 °C.

The storage temperature range is: -40 °C to 85 °C.

phyBOARD-Pollux Components

Note

For easy reference, Pin 1 for each component has been highlighted.

phyBOARD-Pollux Component Placement Diagram

phyBOARD-Pollux Components (Top)

phyBOARD-Pollux Components (Bottom)

phyBOARD-Pollux Components (Bottom)

phyBOARD-Pollux Component Overview

The phyBOARD-Pollux features many different interfaces and is equipped with the components listed in table Connectors and Pin Header. For a more detailed description of each component, refer to the appropriate section listed in the table below. phyBOARD-Pollux Components (Top) and phyBOARD-Pollux Components (Bottom) highlight the location of each component for easy identification.

Connectors and Pin Header

The table below lists all available connectors on the phyBOARD‑Pollux.

Reference Designator

Description

Section

X1USB DebugUSB Debug
X2RS-232 / RS-485RS-232 and RS-485
X3CAN-FD1
CAN-FD

X4CAN-FD2
X5USB1 / USB2 (via Hub)USB Interfaces
X6ExpansionExpansion Connector
X7Micro SD CardSecure Digital Memory Card / MultiMedia Card
X8Ethernet1
Ethernet

X9Ethernet0
X10Mini-PCIePCIe
X11CSI1
Camera Connectivity

X12CSI2
X15LVDS0Audio/Video
X20HDMIHDMI
X21MIPI-DSIMIPI-DSI
X22USB-PD In
Power Supply

X23Power-In
X24LVDS1LVDS
X25SAI5 A/V-ConnectorAudio/Video
X26Backlight for LVDS1LVDS
X36phyCORE ConnectorphyCORE Connector
X39FanFan

phyBOARD-Pollux Connectors and Pin Header

Warning

Ensure that all module connections do not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller User's Manual/Data Sheets. As damage from improper connections varies according to use and application, it is the user‘s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

LEDs

The phyBOARD-Pollux is populated with 6 LEDs. One to indicate the status of the USB VBUS voltage of USB Debug Interface, four to indicate main board voltages. The sixth (D24) is user-programable. phyBOARD-Pollux Components (Top) and phyBOARD-Pollux Components (Bottom)) show the location of the LEDs. Their functions are listed in the table below:

LED

Color

Description

Section

D9GreenIndicator for VCC_5V_MAIN

Power Supply



D10GreenIndicator for VCC_3V3_SOM
D11GreenIndicator for VCC_3V3_SW
D12GreenIndicator for VCC_5V_SW
D13GreenIndicator for VBUS of USB Debug InterfaceUSB Debug

D24

 RGB

User-programmable RGB LED

Multicolor (RGB) LED

phyBOARD-Pollux LED Descriptions

Switches

The phyBOARD-Pollux is populated with three switches. The table below shows their functions:

SwitchDescriptionSection
S1RESETSystem Reset Button
S2ON/OFFSystem ON/OFF Button
S3Boot SwitchBoot Switch

phyBOARD-Pollux Switches

Jumpers

The phyBOARD-Pollux comes pre-configured with several removable jumpers (JP) and solder jumpers (J). These jumpers enable the flexible configuration of a limited number of features for development purposes.

Warning

Due to the small footprint of the solder jumpers (J), PHYTEC does not recommend manual jumper modifications. This may also render the warranty invalid. Only the removable jumper (JP) is described in this section. Contact our sales team if you need jumper configurations different from the default configuration.

The function of the removable jumper on the phyBOARD‑Pollux is shown below. More detailed information can be found in the appropriate section. The locations of the removable jumpers can be found in phyBOARD-Pollux Components (Top).

JumperPositionDefaultDescriptionSection
JP1opennoNo 120 Ohms termination for CAN1


CAN-FD

1+2yesCAN1 terminated with 120 Ohms
JP2opennoNo 120 Ohms termination for CAN2

1+2yesCAN2 terminated with 120 Ohms
JP3opennodo not use



RS-232 and RS-485




1+2noEnable RS-485 Mode for X2

2+3yesEnable RS-232 Mode for X2
JP4opennodo not use

1+2yesHalf-Duplex RS-485 Mode for X2 (JP3 1+2)

2+3noFull-Duplex RS-485 Mode for X2 (JP3 1+2)

phyBOARD-Pollux Jumper Settings

phyBOARD-Pollux SBC Component Detail

This section provides a more detailed look at the phyBOARD‑Pollux components. Each subsection details a particular connector/interface and associated jumpers for configuring that interface.

Tip

Where possible, we also provide useful information regarding design considerations for components. This can be used if you plan to design your own carrier board.

phyCORE Connector (X36)

phyCORE Connection (X36)

phyCORE Connector (X36)

Power Supply (X22/X23)

Warning

Do not change modules or jumper settings while the phyBOARD‑Pollux is supplied with power!

Power Supply Connector (X22, X23)

Power Supply Connectors (X22/X23)

The phyBOARD-Pollux can be powered either by a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector (X23) or by a USB Power Delivery Supply (X22).

Warning

Do not power phyBOARD-Pollux via X22 and X23 at the same time!

The phyBOARD‑Pollux is available with one power supply connector, a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector (X23) suitable for a single 12 V/24 V supply voltage. The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE mounted on the phyBOARD-Pollux, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board.

The permissible input voltage is 12 V to 24 V DC if your SBC is equipped with a 2-pole Phoenix Contact MINI COMBICON base strip. A 24 V adapter with a minimum supply of 1.0 A is recommended to supply the board via the 2-pole base strip. The pin assignment for power supply connector X23:

Interface Pin #Signal

Description

1VCC_IN_PWR_CON12 V to 24 V power supply
2GNDGround

X23 Pin Assignment

USB Power Delivery Connector (X22)

The phyBOARD‑Pollux can be powered by a USB Power Delivery Supply. The phyBOARD-Pollux provides the needed voltage and current with the connected supply and enables the onboard voltages. A 30 W USB-PD supply is recommended to power the phyBOARD-Pollux.

Note

Please note that the connector X22 is only usable as a power supply. It doesn't offer any USB communication interface functionality.

RTC Backup Supply

The phyBOARD-Pollux has a supercapacitor equipped to backup the VRTC rail of the phyCORE-i.MX 8M Plus. There is a multi-footprint to provide the most suitable Supercapacitor for customer applications. Default a 220 mF type is mounted that can be replaced by a 470 mF type. Using the 220 mF type the calculated minimum backup time is 176 h at 25 °C ambient temperature or 313 h at 25 °C ambient temperature using the 470 mF type. The maximum permissible backup time can be much longer depending on the charging time, the actual dark current, and in particular, the ambient temperature.

UARTs

The phyCORE-i.MX 8M Plus supports up to 4 UART units. On the phyBOARD-Pollux, TTL level signals of UART1 (the standard console) and UART4 are routed to Silicon Labs CP2105 UART to USB converter expansion. This USB is brought out at Micro-USB connector X1. UART2 is connected to a multi-protocol transceiver for RS-232 and RS-485, available at pin header connector X2 at RS-232 level, or at RS-485 level. UART3 is at X6 (Expansion Connector) at TTL level.

UART Design Consideration

When designing a custom carrier board, remember the TTL level is 3.3 V.

RS-232 and RS-485 (X2)

RS-232 and RS-485 (X2)

RS-232 and RS-485 Connector (X2)

Pin header connector X2 provides the UART2 signals of the i.MX 8M Plus at either the RS-232 or RS-485 level. The RS-232 interface is intended to be used as data terminal equipment (DTE) and allows for a 5-wire connection including the signals RTS and CTS for hardware flow control. RS-232 is enabled by setting JP3 to 2+3. The RS-485 can be used as a Half-Duplex (3-wire) or Full-Duplex (5-wire). Set JP4 to 1+2 for Half-Duplex Mode or 2+3 for Full-Duplex Mode. The table below shows the signal mapping of the RS-232 and RS-485 level signals at connector X2. The pinout is choosen to fit to the official standard RS-232 pinout on a DE9 plug (D-Sub 9 pin). Were TXD is pin 3, RXD is pin 2, RTS is pin 7, CTS is pin 8 and GND is pin 5. The suitable cables can be found in the table below.

PHYTEC Art-No.Description
WF072

Insulation-displacement connector to DE9 female

WF228Insulation-displacement connector to DE9 male
WK161DB9 RS-232 extension cable 1:1 3 m
WK041DB9 null modem cable 1.8 m


Interface Pin #

Signal name

Signal Type

Signal Level

Description

1N.C.--not connected
2N.C.--not connected
3

RS-232_RXD

RS-485_RX+

RS232_I

RS485_I

-

-

Input depends on JP3 and JP4 settings. See above.

4

RS-232_RTS

RS-485_TX+

RS232_O

RS485_O

-Output depends on JP3 and JP4 settings. See above.
5

RS-232_TXD

RS-485_TX-

RS-486_D-

RS232_O

RS485_O

RS485_I/O

-Input/Output depends on JP3 and JP4 settings. See above.
6

RS-232_CTS

RS-485_RX-

RS-485_D+

RS232_I

RS485_I

RS485_I/O

-Input/Output depends on JP3 and JP4 settings. See above.
7N.C.--not connected
8N.C.--not connected
9GND--Ground
10N.C.--not connected

RS-232/RS-485 (X2) Pin Assignment

CAN FD (X3/X4)

CAN FD (X3/X4)

The phyCORE i.MX 8M Plus FLEXCAN1 and FLEXCAN2 interfaces are brought out at X3 and X4, each as CAN FD. The maximum permissible CAN FD data rate is 8 Mbit/s. A 5 V power output is available to power a CAN device if needed. For development purposes, a 120 Ohms termination can be added by closing JP1 (CAN1) or JP2 (CAN2). For standard use, it is possible to mount a more suitable split termination in a customer-specific BOM.

The pinout is chosen to fit the inofficial standard CAN pinout on a DE9 plug (D-Sub 9 pin), where CAN_L is pin 2, CAN_H is pin 7, GND is pin 3 and VCC_5V is pin 9. The suitable cables can be found in the table below.

PHYTEC Art-No.Description
WF072

Insulation-displacement connector to DE9 female

WF228Insulation-displacement connector to DE9 male

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1N.C.--not connected
2N.C.--not connected
3CAN1_LCAN_I/O-Low-level CAN bus input/output line
4CAN1_HCAN_I/O-High-level CAN bus input/output line
5GND--Ground
6N.C.--not connected
7N.C.--not connected
8VCC_5V_CAN1PWR_O5 V5 V Supply
9N.C.--not connected
10N.C.--not connected

CAN FD1 (X3) Pin Assignment

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1N.C.--not connected
2N.C.--not connected
3CAN2_LCAN_I/O-Low-level CAN bus input/output line
4CAN2_HCAN_I/O-High-level CAN bus input/output line
5GND--Ground
6N.C.--not connected
7N.C.--not connected
8VCC_5V_CAN2PWR_O5 V5 V Supply
9N.C.--not connected
10N.C.--not connected

CAN FD1 (X4) Pin Assignment

Ethernet (X8/X9)

 

Ethernet Connectors (X8/X9)

The phyBOARD‑Pollux is equipped with 2 RJ45 connectors supporting a 10/100/1000Base-T network connection. The LEDs for LINK (green) and SPEED (yellow) indications are integrated into the connector. The Ethernet transceiver supports Auto MDI-X, eliminating the need for a direct connect LAN or cross-over path cable. They detect the TX and RX pins of the connected device and automatically configure the PHY TX and RX pins accordingly.

Ethernet Design Consideration (X8)

The data lanes should be routed with a differential impedance of 100 Ohm. The center taps of each pair's transformer have to be connected to GND through a 100nF capacitor. The LED pins are open-drain outputs of the SOM without a resistor, so they should be connected to the cathodes of the LEDs through a resistor.

USB 3.2 Gen1 Interfaces (X5)

USB Interfaces (X5)

USB 3.2 Gen1 Connectors (X5)

The phyBOARD-Pollux provides two USB 3.2 Gen1 (5 Gbps) interfaces. USB1 is accessible at the upper socket as a host. Using an A-plug to A-plug cable, it is possible to provide USB in dual role mode at this socket. USB dual role mode can be used for downloading program code into the external flash, internal controller RAM, or for debugging programs currently executing. The lower socket is connected via a USB 3.2 Gen 1 hub to USB2 of the phyCORE i.MX 8M Plus.

USB 3.2 Gen1 Design Considerations

Series capacitors are already present on the phyCORE-i.MX 8M Plus. It is not necessary to provide additional series capacitors in the TX lines. Take care to double-check the signal direction of the high-speed lines where TX is output and RX is input on phyCORE-i.MX 8M Plus. The TX and RX lines should be routed with an impedance of 50 Ohms to a ground plane and 100 Ohms differential impedance. Route USB D lines with 45 Ohms to Ground and 90 Ohms differential impedance.

USB Debug (X1)

USB Debug Connector (X1)

The main debug interface is UART1. UART4 is the debug interface for the M7 core. Both UART interfaces are connected to a UART-to-USB Converter (Silicon Labs CP2105). The USB interface is brought out at a Micro-USB-AB socket (X1). Use the following terminal settings to connect to phyBOARD-Pollux serial interfaces:

  • Speed: 115200 baud
  • Data bits: 8
  • Stop bits: 1
  • Parity: None
  • Flow control: None

The table below shows the pinout of the USB Debug connector:

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1VCC_USB_DEBUGPWR_I5 VVBUS Voltage input of Debug USB Port
2USB_DEBUG_D_NUSB_I/O-USB 2.0 Negative Lane
3USB_DEBUG_D_PUSB_I/O-USB 2.0 Positive Lane
4ID--not connected
5GND--Ground
6SHIELD1--Ground
7SHIELD2--Ground
8SHIELD3--Ground
9SHIELD4--Ground
10SHIELD5--Ground
11SHIELD6--Ground

 X1 Pin Assignment

Secure Digital Memory Card / MultiMedia Card (X7)


SD / MM Card Connector (X7)

The phyBOARD‑Pollux provides a standard microSDHC card slot at X7 for use with SD/MMC interface cards. It allows for a fast, easy connection to peripheral devices like microSD and MMC cards. Power to the SD interface is supplied by inserting the appropriate card into the SD/MMC connector. It also features card detection, a lock mechanism, and a smooth extraction function by pushing the card in and out.

SD / MM Card Design Considerations

Series resistors might be required to adapt the drive strength of the card. SD interface should be routed with an impedance of 50 Ohms to a ground plane. The trace length between CLK, CMD, and DATA lanes should be matched and keep as short as possible. Avoid Vias and take care of the signal current return path.

PCIe (X10)


PCIe Connector (X10)

The 1-lane PCI express interface provides PCIe Gen. 2.0 functionality, which supports 5 GT/s operations. The interface is fully backward compatible with the 2.5 GT/s Gen. 1.1 specification. Various control signals are implemented with GPIOs. The PCIe interface is brought out at the Mini PCIe connector X10 shown above.

The table below shows in-depth information such as pin assignment and signals used to implement special features of the Mini PCIe interface.

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1

X_GPIO1_IO10/PCIe_nWAKE

O

3.3 V

nWAKE

2

VCC_3V3_SW

PWR_O

3.3 V

3.3 V Supply

3

X_SD1_DATA0/GPIO2_IO02/PCIe_COEX1

O

3.3 V

COEX1

4

GND

-

-

Ground

5

X_SD1_DATA1/GPIO2_IO03/PCIe_COEX2

O

3.3 V

COEX2

6

VCC_1V5_MPCI

PWR_O

1.5 V

1.5 V Supply

7

X_GPIO1_IO11/PCIe_nCLKREQ

I

3.3 V

Inverted Clock Request

8

NC

-

-

accessible at TP10

9

GND

-

-

Ground

10

NC

-

-

accessible at TP11

11

X_PCIE_REF_PAD_CLK_N


PCIe_O

-

100 MHz Reference Clock Negative Lane

12

NC

-

-

accessible at TP12

13

X_PCIE_REF_PAD_CLK_P

PCIe_O

-

100 MHz Reference Clock Positive Lane

14

NC

-

-

accessible at TP13

15

GND

-

-

Ground

16

NC

-

-

accessible at TP14

17

NC

-

-

accessible at TP18

18

GND

-

-

Ground

19

NC

-

-

accessible at TP19

20

X_GPIO1_IO14/PCIe_nW_DISABLE

O

3.3 V

nW_DISABLE

21

GND

-

-

Ground

22

X_GPIO1_IO08/PCIe_nPERST

O

3.3 V

nPERST

23

X_PCIE_RXN_N

PCIe_I

-

SOM Receive Negative Lane

24

VCC_3V3_SW

PWR_O

3.3 V

3.3 V Supply

25

X_PCIE_RXN_P

PCIe_I

-

SOM Receive Positive Lane

26

GND

-

-

Ground

27

GND

-

-

Ground

28

VCC_1V5_MPCI

PWR_O

1.5 V

1.5 V Supply

29

GND

-

-

Ground

30

X_I2C2_SCL

OD-BI-PU

3.3 V

I²C Clock

31

X_PCIE_TXN_N

PCIe_O

-

SOM Transmit Negative Lane

32

X_I2C2_SDA

OD-BI-PU

3.3 V

I²C Data

33

X_PCIE_TXN_P

PCIe_O

-

SOM Transmit Positive Lane

34

GND

-

-

Ground

35

GND

-

-

Ground

36

USB_HUB_DN4_D-

USB_I/O

-

USB 2.0 Negative Lane

37

GND

-

-

Ground

38

USB_HUB_DN4_D+

USB_I/O

-

USB 2.0 Positive Lane

39

VCC_3V3_SW

PWR_O

3.3 V

3.3 V Supply

40

GND

-

-

Ground

41

VCC_3V3_SW

PWR_O

3.3 V

3.3 V Supply

42

nLED_WWAN

I

-

accessible at TP15

43

GND

-

-

Ground

44

nLED_WLAN

I

-

accessible at TP16

45

NC

-

-

-

46

nLED_WPAN

I

-

accessible at TP17

47

NC

-

-

-

48

VCC_1V5_MPCI

PWR_O

1.5 V

1.5 V Supply

49

NC

-

-

-

50

GND

-

-

Ground

51

NC

-

-

-

52

VCC_3V3_SW

PWR_O

3.3 V

3.3 V Supply

S1

GND

-

-

Ground

S2

GND

-

-

Ground

X10 Pin Assignment

PCIe Design Considerations

100nF AC-Coupling capacitors are placed at the output of the phyCORE-i.MX 8M Plus in series to the TX- and CLK-Lanes. No further TX coupling capacitors are needed. The differential impedance should be 85 Ohm for all lanes.

Camera Connectivity

phyCAM-M MIPI CSI Camera Connectors


phyCAM-M MIPI CSI-2 Camera Connectors (X11 and X12)

The phyCORE-i.MX 8M Plus on the phyBOARD-Pollux offers 2 independent interfaces to connect digital camera boards with MIPI CSI-2 interface. The 4-lane MIPI CSI-2 interfaces are brought out as phyCAM-M camera interfaces at connectors X10 and X11. The pin assignments of connectors X11 and X12 are shown below. 

The phyCAM-M camera connectors fit the phyCAM-M product family with different color and monochrome sensors. Suitable camera modules are e.g. VM-016-COL-M (1 MPix) or VM-017-BW-M (5 Mpix) which can be delivered with a complete objective. Contact the PHYTEC Sales Team for advice on how to tailor a camera module to your application.

The suitable cable can be found in the table below.

PHYTEC Art-No.Description
WF271

phyCAM-M cable 150 mm

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1

GND

-

-

Ground

2

X_MIPI_CSI1_D0_P

MIPI CSI-2-

MIPI-CSI-2 Data 0 Positive Lane

3

X_MIPI_CSI1_D0_N

MIPI CSI-2-

MIPI-CSI-2 Data 0 Negative Lane

4

GND

-

-

Ground

5

X_MIPI_CSI1_D1_P

MIPI CSI-2-

MIPI-CSI-2 Data 1 Positive Lane

6

X_MIPI_CSI1_D1_N

MIPI CSI-2-

MIPI-CSI-2 Data 1 Negative Lane

7

GND

-

-

Ground

8

X_MIPI_CSI1_CLK_P

MIPI CSI-2-

MIPI-CSI-2 Clock Positive Lane

9

X_MIPI_CSI1_CLK_N

MIPI CSI-2-

MIPI-CSI-2 Clock Negative Lane

10

GND

-

-

Ground

11

X_MIPI_CSI1_D2_P

MIPI CSI-2-

MIPI-CSI-2 Data 2 Positive Lane

12

X_MIPI_CSI1_D2_N

MIPI CSI-2-

MIPI-CSI-2 Data 2 Negative Lane

13

GND

-

-

Ground

14

X_MIPI_CSI1_D3_P

MIPI CSI-2-

MIPI-CSI-2 Data 3 Positive Lane

15

X_MIPI_CSI1_D3_N

MIPI CSI-2-

MIPI-CSI-2 Data 3 Negative Lane

16

GND

-

-

Ground

17

X_GPIO1_IO05/CSI1_CTRL4

OD-BI-PU3.3 V

CSI2_CTRL4

18

X_GPIO1_IO03/CSI1_CTRL3

OD-BI-PU3.3 V

CSI2_CTRL3

19

X_GPIO1_IO01/CSI1_CTRL2

OD-BI-PU3.3 V

CSI2_CTRL2

20

X_GPIO1_IO00/CSI1_CTRL1

OD-BI-PU3.3 V

CSI2_CTRL1

21

GND

-

-

Ground

22

X_I2C3_SCL

OD-BI-PU3.3 V

I²C Clock

23

X_I2C3_SDA

OD-BI-PU3.3 V

DI²C ata

24

CSI1_ADDR

O3.3 V

Choose the I2C address of the Camera

25

CSI1_nRESET

O3.3 V

Hard reset for camera

26

CSI1_VCC_SELECT

OD-I-PU3.3 V

Interface voltage selection

open = 3.3 V

GND = 5 V

27

GND

-

-

Ground

28

VCC_CSI1_OUT

PWR_O3.3 V / 5 V

Supply of Camera

29

VCC_CSI1_OUT

PWR_O3.3 V / 5 V

Supply of Camera

30

VCC_CSI1_OUT

PWR_O3.3 V / 5 V

Supply of Camera

CSI-1 (X11) Pin Assignment

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1

GND

-

-

Ground

2

X_MIPI_CSI2_D0_P

MIPI CSI-2-

MIPI-CSI-2 Data 0 Positive Lane

3

X_MIPI_CSI2_D0_N

MIPI CSI-2-

MIPI-CSI-2 Data 0 Negative Lane

4

GND

-

-

Ground

5

X_MIPI_CSI2_D1_P

MIPI CSI-2-

MIPI-CSI-2 Data 1 Positive Lane

6

X_MIPI_CSI2_D1_N

MIPI CSI-2-

MIPI-CSI-2 Data 1 Negative Lane

7

GND

-

-

Ground

8

X_MIPI_CSI2_CLK_P

MIPI CSI-2-

MIPI-CSI-2 Clock Positive Lane

9

X_MIPI_CSI2_CLK_N

MIPI CSI-2-

MIPI-CSI-2 Clock Negative Lane

10

GND

-

-

Ground

11

X_MIPI_CSI2_D2_P

MIPI CSI-2-

MIPI-CSI-2 Data 2 Positive Lane

12

X_MIPI_CSI2_D2_N

MIPI CSI-2-

MIPI-CSI-2 Data 2 Negative Lane

13

GND

-

-

Ground

14

X_MIPI_CSI2_D3_P

MIPI CSI-2-

MIPI-CSI-2 Data 3 Positive Lane

15

X_MIPI_CSI2_D3_N

MIPI CSI-2-

MIPI-CSI-2 Data 3 Negative Lane

16

GND

-

-

Ground

17

X_SAI1_RXD1/GPIO4_IO03/CSI2_CTRL3-4

OD-BI-PU3.3 V

CSI2_CTRL4

GPIO4_IO03 shared with CSI2_CTRL3 via J18. Default not connected

18

X_SAI1_RXD1/GPIO4_IO03/CSI2_CTRL3-4

OD-BI-PU3.3 V

CSI2_CTRL3

GPIO4_IO03 shared with CSI2_CTRL4 via J18. Default routes to CSI2_CTRL3

19

X_GPIO1_IO07/CSI2_CTRL2

OD-BI-PU3.3 V

CSI2_CTRL2

20

X_GPIO1_IO06/CSI2_CTRL1

OD-BI-PU3.3 V

CSI2_CTRL1

21

GND

-

-

Ground

22

X_I2C2_SCL

OD-BI-PU3.3 V

I²C Clock

23

X_I2C2_SDA

OD-BI-PU3.3 V

I²C Data

24

CSI2_ADDR

O3.3 V

Choose the I2C address of the Camera

25

CSI2_nRESET

O3.3 V

Hard reset for camera

26

CSI2_VCC_SELECT

OD-I-PU3.3 V

Interface voltage selection

open = 3.3 V

GND = 5 V

27

GND

-

-

Ground

28

VCC_CSI2_OUT

PWR_O3.3 V / 5 V

Supply of Camera

29

VCC_CSI2_OUT

PWR_O3.3 V / 5 V

Supply of Camera

30

VCC_CSI2_OUT

PWR_O3.3 V / 5 V

Supply of Camera

CSI-2 (X12) Pin Assignment

Camera Design Considerations

Regarding camera connections when designing a customer carrier board:

  1. The differential impedance should be 100 Ohm for all lanes to a Ground-Plane. Lanes should be matched.
  2. phyCAM-M interfaces offer 3.3V or 5V supply voltages (selected by interface pin 26). Both voltages should be provided by the board to guarantee full compatibility to the phyCAM-M interface.
  3. Each phyCAM interface needs a different I2C address if connected to the same I²C Bus. Place a Pull-up resistor at pin 24 to select the secondary address.

General information and design guidelines for PHYTEC camera interfaces can be found here:

Specific information for each PHYTEC camera module can be found on that module's download page: https://www.phytec.de/produkte/embedded-imaging/#c11529

HDMI (X20)

HDMI Connector (X32)

HDMI Connector (X20)

The phyBOARD‑Pollux provides a High-Definition Multimedia Interface (HDMI) which is compliant with HDMI 2.0a. It supports a maximum resolution of 1920x1080p60, 1280x720p60, 720x480p60, 640x480p60. Please refer to the i.MX 8M Plus Applications Processor Reference Manual for more information.

The HDMI interface is brought out at a standard HDMI type A connector (X20) on the phyBOARD‑Pollux and is comprised of the following signal groups:

  • Three pairs of data signals
  • One pair of clock signals
  • The Display Data Channel (DDC)
  • The Consumer Electronics Control (CEC)
  • The Hot Plug Detect (HPD) signal
  • Audio Return Channel (ARC)

All signals are routed from the phyCORE‑Connector to the HDMI receptacle through ESD Protection Diodes.

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1

X_HDMI_TX2_PHDMI_O-HDMI Data 2 Positive Lane

2

GND

-

-

Ground

3

X_HDMI_TX2_NHDMI_O-HDMI Data 2 Negative Lane

4

X_HDMI_TX1_PHDMI_O-HDMI Data 1 Positive Lane

5

GND

-

-

Ground

6

X_HDMI_TX1_NHDMI_O-HDMI Data 1 Negative Lane

7

X_HDMI_TX0_PHDMI_O-HDMI Data 0 Positive Lane

8

GND

-

-

Ground

9

X_HDMI_TX0_NHDMI_O-HDMI Data 0 Negative Lane

10

X_HDMI_TXC_PHDMI_O-HDMI Clock Positive Lane

11

GND

-

-

Ground

12

X_HDMI_TXC_NHDMI_O-HDMI Clock Negative Lane

13

X_HDMI_CECOD-BI-PUVDD_CECConsumer Electronics Control

14

X_EARC_P_UTIL--Audio Return Channel Positive Lane / Utility Pin

15

X_HDMI_DDC_SCLOD-BI-PU5 VI²C Clock

16

X_HDMI_DDC_SDAOD-BI-PU5 VI²C Data

17

GND

-

-

Ground

18

VCC_5V_HDMI_OUTPWR_O5 V5 V Supply for HDMI Device

19

X_EARC_N_HPD-5V
Audio Return Channel Negative Lane / Hot Plug detect

20

SHIELD_1

-

-

Shield connected to Ground over 100 nF and 150 pF parallel to 1 MOhm

21

SHIELD_2

-

-

22

SHIELD_3

-

-

23

SHIELD_4

-

-

X32 Pin Assignment

HDMI Design Considerations

The differential impedance should be 100 Ohm for all lanes to a Ground-Plane. Lanes should be matched. The DDC lanes need pull-up resistors between 1.5k and 2k to 5V through a diode. The CEC lane needs a 27k pull-up resistor connected to 3.3V through a diode. This prevents leaking current in a power-off state.

Audio/Video (SAI2/LVDS0)

Audio/Video Connectors (X15/X25)

The phyCORE-i.MX 8M Plus offers one LVDS display interface which supports two output channels. The Audio/Video (A/V) connectors X15 and X15 provide an easy way to add typical A/V functions and features to the phyBOARD‑Pollux. Standard interfaces such as 4-lane LVDS, I2S, I2C, and USB, as well as different supply voltages, are available at the two A/V female dual entry connectors.  A special feature of these connectors is their connectivity from the top or bottom.

The A/V connector is intended to be used with phyBOARD Expansion Boards and to add specific audio/video connectivity with custom expansion boards. A/V connector X25 makes all signals for display connectivity available, while X15 provides signals for audio and touch screen connectivity as well as an I2C bus and additional control signals. The tables below show the pin assignment of connectors X15 and X25. 

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

GND

-

-

Ground

2

X_LVDS0_D2_P

LVDS_O

-

LVDS Data 2 Positive Lane

3

X_LVDS0_CLK_P

LVDS_O

-

LVDS Clock Positive Lane

4

X_LVDS0_D2_N

LVDS_O

-

LVDS Data 2 Negative Lane

5

X_LVDS0_CLK_N

LVDS_O

-

LVDS Clock Negative Lane

6

GND

-

-

Ground

7

GND

-

-

Ground

8

X_LVDS0_D3_P

LVDS_O

-

LVDS Data 3 Positive Lane

9

X_LVDS0_D1_P

LVDS_O

-

LVDS Data 1 Positive Lane

10

X_LVDS0_D3_N

LVDS_O

-

LVDS Data 3 Negative Lane

11

X_LVDS0_D1_N

LVDS_O

-

LVDS Data 1 Negative Lane

12

GND

-

-

Ground

13

GND

-

-

Ground

14

X_LVDS0_D0_P

LVDS_O

-

MIPI DSI Data 0 Positive Lane

15

VCC_IN_AV

PWR_O

12 V to 24 V

Input Supply Voltage of phyBOARD Pollux

16

X_LVDS0_D0_N

LVDS_O

-

MIPI DSI Data 0 Negative Lane

X25 Pin Assignment

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

USB_HUB_DN3_D+_AV_CON

USB_I/O

-

USB 2.0 Data positive

2

USB_HUB_DN3_D-_AV_CON

USB_I/O

-

USB 2.0 Data negative

3

X_nRESET

OD-BI-PU

3.3 V

Global Board Reset

4

GND

-

-

Ground

5

X_SAI1_RXD0/GPIO4_IO02

I/O

3.3 V

SAI RXD/GPIO

6

X_SAI3_TXFS/GPIO4_IO24

I/O

3.3 V

SAI TXFS/GPIO

7

X_SAI3_TXC/GPIO5_IO00

I/O

3.3 V

SAI TXC/GPIO

8

X_SAI3_TXD/GPIO5_IO01

I/O

3.3 V

SAI TXD/Backlight EN

9

X_SAI3_MCLK/PWM4_OUT

I/O

3.3 V

SAI MCLK/Backlight PWM

10

X_SAI3_RXFS/GPIO4_IO28

I/O

3.3 V

SAI RXFS/GPIO

11

GND

-

-

Ground

12

X_SAI5_RXFS/GPIO3_IO19

I/O

3.3 V

SAI RXC/GPIO

13

X_SAI2_TXD0

I/O

3.3 V


14

GND

-

-

Ground

15

X_SAI2_TXFS

I/O

3.3 V

SAI TXFS

16

X_SAI2_TXC

I/O

3.3 V

SAI TXC

17

X_SAI2_RXC

I/O

3.3 V

SAI TXC

18

X_SAI2_RXFS

I/O

3.3 V

SAI RXFS

19

X_SAI2_MCLK

I/O

3.3 V

SAI MCLK

20

X_SAI2_RXD0

I/O

3.3 V

SAI RXD0

21

GND

-

-

Ground

22

X_I2C4_SDA

OD-BI-PU

3.3 V

I²C Data

23

X_UART3_RXD

I/O

3.3 V

UART RXD/GPIO

Depending on J27. Default not connected.

24

X_I2C4_SCL

OD-BI-PU

3.3 V

I²C Clock

25

X_UART3_TXD

I/O

3.3 V

UART TXD/GPIO

Depending on J26. Default not connected.

26

GND

-

-

Ground

27

VCC_5V

PWR_O

5 V

5 V Supply

28

VCC_3V3

PWR_O

3.3 V

3.3 V Supply

29

VCC_5V

PWR_O

5 V

5 V Supply

30

VCC_3V3

PWR_O

3.3 V

3.3 V Supply

X15 Pin Assignment

Audio/Video Design Considerations

The differential impedance of LVDS0 lanes should be 100 Ohm and 50 Ohm to a Ground-Plane for all lanes. Lanes should be matched. The audio signals should have a single-ended impedance of 50 Ohmto a Ground-Plane.

LVDS1 (X24/X26)

LVDS1 Connectors (X24/X26)

The phyCORE-i.MX 8M Plus offers one LVDS display interface which supports two output channels. The video connectors X24 and X26 provide an easy way to connect a display to the phyBOARD‑Pollux. The pinout of both connectors fits to the Glyn LVDS Display Family with different display sizes and display resolutions. In addition to the Glyn LVDS signals, there are USB and I²C for touch brought out at X24 too.

The connectors are intended to be used with PHYTEC KLCD-AC163. The tables below show the pin assignment of connectors X24 and X26. 

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

N.C.--not connected

2

N.C.--not connected

3

VCC_3V3_LVDS1PWR_O3.3 V3.3 V supply

4

GND--Ground

5

X_LVDS1_CLK_N

LVDS_O

-

LVDS Clock Negative Lane

6

X_LVDS1_CLK_P

LVDS_O

-

LVDS Clock Positive Lane

7

VCC_3V3_LVDS1PWR_O3.3 V3.3 V supply

8

GND--Ground

9

X_LVDS1_D0_N

LVDS_O

-

LVDS Data 0 Negative Lane

10

X_LVDS1_D0_P

LVDS_O

-

LVDS Data 0 Positive Lane

11

X_LVDS1_D1_N

LVDS_O

-

LVDS Data 1 Negative Lane

12

X_LVDS1_D1_P

LVDS_O

-

LVDS Data 1 Positive Lane

13

X_LVDS1_D2_N

LVDS_O

-

LVDS Data 2 Negative Lane

14

X_LVDS1_D2_P

LVDS_O

-

LVDS Data 2 Positive Lane

15

X_LVDS1_D3_N

LVDS_O

-

LVDS Data 3 Negative Lane

16

X_LVDS1_D3_P

LVDS_O

-

LVDS Data 3 Positive Lane

17VCC_5V_LVDS1PWR_O5 V5 V supply
18N.C.--

Default: not connected

Can be tied to GND if J28 is mounted.

19USB_HUB_DN3_D-_LVDS1USB_I/O-

Default: not connected

USB 2.0 Data negative shared X15 depending jumper setting J17.

20USB_HUB_DN3_D+_LVDS1USB_I/O-

Default: not connected

USB 2.0 Data positive shared X15 depending jumper setting J16.

21N.C.--not connected
22N.C.--

Default: not connected

Can be tied to GND if J29 is mounted.

23N.C.--not connected
24N.C.--not connected
25N.C.--not connected
26N.C.--not connected
27X_I2C4_SCL--

Default: not connected

Can be connected to X_I2C4_SCL or tied to GND or VCC_3V3_LVDS1 if J38 is mounted.

28GND--

Default tied to GND. Can be tied to VCC_3V3_LVDS1 if J4 is set to 2+3.

29X_I2C4_SDA--

Default: not connected

Can be connected to X_I2C4_SDA or tied to GND or VCC_3V3_LVDS1 if J39 is mounted.

30N.C.--not connected
31GND--Terminal Pin
32GND--Terminal Pin

X26 Pin Assignment

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

VCC_12V_LVDS1

PWR_O

12 V

12 V supply for display backlight. Default a 12 V voltage regulator to provide current for the backlight. If VCC_IN is 12 V, VCC_IN can be connected directly to VCC_12V_LVDS1 and lower BOM cost by removing the 12 V voltage regulator.

2

X_SPDIF_TX/PWM3_OUT

I/O

3.3 V

PWM output

3

GND

-

-

Ground

4

GND

-

-

Ground

5

X_SD2_WP/GPIO2_IO20/LVDS1_BL_EN

I/O

3.3 V

Backlight enable

X24 Pin Assignment

LVDS Design Considerations

The differential impedance of LVDS0 lanes should be 100 Ohm and 50 Ohm to a Ground-Plane for all lanes. Lanes should be matched.

MIPI-DSI (X21)

MIPI-DSI (X21)

MIPI-DSI (X21)

The phyCORE-i.MX 8M Plus offers one MIPI-DSI display interface. MIPI-DSI has 4 channels, supporting one display with a resolution of up to 1920 x 1080 at 60Hz.

The tables below show the pin assignment of connector X21 (Hirose DF12(4.0)-36DP-0.5V(86)).

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

GND--Ground

2

GND--Ground

3

X_MIPI_DSI1_D0_PDSI_O-MIPI DSI Data 0 Positive Lane

4

VCC_IN_MIPI_DSIPWR_O12 V to 24 Vinternally connected to VCC_IN

5

X_MIPI_DSI1_D0_NDSI_O-MIPI DSI Data 0 Negative Lane

6

VCC_IN_MIPI_DSIPWR_O12 V to 24 Vinternally connected to VCC_IN

7

GND--Ground

8

GND--Ground

9

X_MIPI_DSI1_D1_PDSI_O-MIPI DSI Data 1 Positive Lane

10

VCC_IN_MIPI_DSIPWR_O12 V to 24 Vinternally connected to VCC_IN

11

X_MIPI_DSI1_D1_NDSI_O-MIPI DSI Data 1 Negative Lane

12

VCC_IN_MIPI_DSIPWR_O12 V to 24 Vinternally connected to VCC_IN

13

GND--Ground

14

GND--Ground

15

X_MIPI_DSI1_CLK_PDSI_O-MIPI DSI Clock Positive Lane

16

VCC_5V_MIPI_DSIPWR_O5 V5 V supply
17X_MIPI_DSI1_CLK_NDSI_O-MIPI DSI Clock Negative Lane
18VCC_5V_MIPI_DSIPWR_O5 V5 V supply
19GND--Ground
20GND--Ground
21X_MIPI_DSI1_D2_PDSI_O-MIPI DSI Data 2 Positive Lane
22VCC_3V3_MIPI_DSIPWR_O3.3 V3.3 V supply
23X_MIPI_DSI1_D2_NDSI_O-MIPI DSI Data 2 Negative Lane
24VCC_3V3_MIPI_DSIPWR_O3.3 V3.3 V supply
25GND--Ground
26GND--Ground
27X_MIPI_DSI1_D3_PDSI_O-MIPI DSI Data 3 Positive Lane
28X_I2C4_SCL

OD-BI-PU

3.3 V

I²C Clock

29X_MIPI_DSI1_D3_NDSI_O-MIPI DSI Data 3 Negative Lane
30X_I2C4_SDA

OD-BI-PU

3.3 V

I²C Data

31GND--Ground
32GND--Ground
33MIPI_DSI1_GPIO0I/O3.3 VConnected to TP53
34X_SPDIF_RX/PWM2_OUT/MIPI-DSII/O3.3 VPWM output
35MIPI_DSI1_GPIO1I/O3.3 VConnected to TP54
36X_nRESET

OD-BI-PU

3.3 V

Global Board Reset

37GND--Terminal Pin
38GND--Terminal Pin

X21 Pin Assignment

MIPI-DSI Design Considerations

The differential impedance of MIPI-DSI1 lanes should be 100 Ohm and 50 Ohm to a Ground-Plane for all lanes. Lanes should be matched.

Expansion Connector (X6)

Expansion Connector (X6)

Expansion Connector (X6)

The expansion connector X6 provides an easy way to add other functions and features to the phyBOARD‑Pollux. Standard interfaces such as SPI, USB, JTAG, UART, SDIO, and I2C are available at the expansion connector. The expansion connector is intended to be used with a phyBOARD Evaluation Adapter. The expansion connector can also add specific functions with custom expansion boards. Information on the Evaluation Adapter for the expansion connector can be found in the Application Guide for phyBOARD Expansion Boards (L‑793e).

The pinout of the expansion connector is shown in the table below:

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

VCC_3V3_SW

PWR_O

3.3 V

3.3 V supply

2

VCC_5V_SW

PWR_O

5 V

5 V supply

3

VCC_1V8_EXP_CON

PWR_O

1.8 V

1.8 V supply

4

GND

-

-

Ground

5

X_UART3_TXD

I/O

3.3 V

Default connected to X_UART3_TXD via J47

6

X_SD1_STROBE/UART3_CTS_B

I/O

3.3 V

MOSI

7

X_SD1_RESET_B/UART3_RTS_B

I/O

3.3 V

MISO

8

X_UART3_RXD

I/O

3.3 V

Default connected to X_UART3_RXD via J46

9

GND

-

-

Ground

10

X_CLKOUT1

O

3.3 V

Monitor output clock

11

X_I2C2_SDA

OD-BI-PU

3.3 V

I²C Data

12

X_CLKOUT2

O

3.3 V

Monitor output clock

13

X_I2C2_SCL

OD-BI-PU

3.3 V

I²C Clock

14

GND

-

-

Ground

15

X_JTAG_TMS

I

3.3 V

JTAG TMS

16

JTAG_TRST

I

3.3 V

JTAG TRST

Default conneced to Global Board Reset X_nRESET via J35

17

X_JTAG_TDI

I

3.3 V

JTAG TDI

18

X_JTAG_TDO

O

3.3 V

JTAG TDO

19

GND

-

-

Ground

20

X_JTAG_TCK

I

3.3 V

JTAG TCK

21

USB_HUB_DN2_D+

USB_I/O

-

USB 2.0 Data positive

22

USB_HUB_DN2_D-

USB_I/O

-

USB 2.0 Data Negative

23

X_nRESET

OD-BI-PU

3.3 V

Global Board Reset

24

GND

-

-

Ground

25

X_SD1_CMD/GPIO2_IO01

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

26

X_SD1_DATA0/GPIO2_IO02/EXP_CON

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

27

X_SD1_CLK/GPIO2_IO00

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

28

X_SD1_DATA1/GPIO2_IO03/EXP_CON

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

29

GND

-

-

Ground

30

X_SD1_DATA2/GPIO2_IO04

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

31

X_UART3_RXD


I/O

3.3 V

Default connected to X_UART3_RXD via J34

32

X_SD1_DATA3/GPIO2_IO05

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

33

X_UART3_TXD

I/O

3.3 V

Default connected to X_UART3_TXD via J33

34

GND

-

-

Ground

35

X_SD1_DATA4/GPIO2_IO06

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

36

X_SD1_DATA5/GPIO2_IO07

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

37

USB_HUB_nPWRCTL2

O

3.3 V

PWRCTL2/BATEN2 output of Ti TUSB8042A USB hub belonging to USB_HUB_DN2 and USB_HUB_nOVERCUR2

38

X_SD1_DATA6/GPIO2_IO08

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

39

USB_HUB_nOVERCUR2

OD-I-PU

3.3 V

nOVERCUR2 input of Ti TUSB8042A USB hub belonging to USB_HUB_DN2 and USB_HUB_nPWRCTL2

40

X_EARC_AUX

-

-

-

41

GND

-

-

Ground

42

X_SPDIF_EXT_CLK/PWM1_OUT/GPIO5_IO05

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

43

X_ECSPI2_SCLK

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

44

X_SD1_DATA7/GPIO2_IO09

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

45

X_ECSPI2_MOSI

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

46

GND

-

-

Ground

47

X_ECSPI2_MISO

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

48

X_ONOFF

I

1.8 V

ONOFF input of phyCORE i.MX 8M Plus

49

X_ECSPI2_SS0

I/O

3.3 V

Refer to the i.MX 8M Plus Datasheet for all muxing options

50

X_PMIC_ON_REQ

I

1.8 V

PMIC_ONREQ input of phyCORE i.MX 8M Plus PMIC can be used to power up phyCORE i.MX8 M Plus from power-off state

51

GND

-

-

Ground

52

X_GPIO1_IO02/PMIC_WDOG

I

3.3 V

PMIC_WDOG input of phyCORE i.MX 8M Plus PMIC can be used to power off phyCORE i.MX8 M Plus from any power state

53

X_ETH1_GPIO0

I/O

1.8 V

GPIO_0 pin of phyCORE i.MX 8M Plus Ethernet-PHY Ti DP83867

54

X_nTEMP_ALERT

I/OD

3.3 V

ALERT output of phyCORE i.MX 8M Plus temperature sensors, if ALERT is enabled

55

X_ETH1_GPIO1

I/O

1.8 V

GPIO_1 pin of phyCORE i.MX 8M Plus Ethernet-PHY Ti DP83867

56

GND

-

-

Ground

57

VCC_IN

PWR_O

12 V to 24 V

Input Supply Voltage of phyBOARD

58

ETH0_LED_1

O

1.8 V

LED_1 pin of phyBOARD-Pollux Ethernet-PHY Ti DP83867

59

GND

-

-

Ground

60

VCC_5V_MAIN

PWR_O

5 V

5 V Supply (always on)

X6 Expansion Pinout

Fan (X39)

If heatsinking is required for the phyCORE-i.MX 8M Plus, a PWM-controlled fan can be connected to the phyBOARD-Pollux. The fan's supply voltage is 5 V and the PWM signal is brought out as open-drain. The frequency generator signal which can be used to monitor fan rotation is connected to test pad TP55 and comes with a pull-up resistor to 3.3 V.

A Hirose DF13-4P-1.25V(75) socket is used as a connector with the following pinout:

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

VCC_5V_SW

PWR_O

5 V

5 V Supply

2GND--Ground
3FAN_FGOD-BI-PU3.3 VFrequency Generator 'speedo'-signal of a PWM Fan. Connected to TP55
4X_SPDIF_RX/PWM2_OUT/FAN_CONI/OD-Inverted PWM Output, Default open. If the fan requires an external pull-up resistor, R226 can be mounted to tie to VCC_5V_SW

X39 Fan Pinout

Onboard Functionalities

Trusted Platform Module (TPM) (U24)

The phyBOARD-Pollux is equipped with a Trusted Platform Module (TPM) (Infineon TPM SLB 9670). The TPM is a chip developed, produced, tested, and certified according to the TCG specification that enhances the board with additional security functions. These security functions include the generation and secure storage (in the hardware) of keys for the authentication and identification of communication participants (SSH, server, cloud, etc.) and data, which can also be encrypted.

The TPM is connected to the phyCORE-i.MX 8M Plus through the X_ECSPI1 interface. GPIO1 and GPIO2 can be configured by J43 and J44. Default GPIO1 is not connected and GPIO2 is tied to Ground.

Note

PHYTEC has a specialized Embedded Security Team that supports customers who would like to plan and implement their individual security concepts. Contact PHYTEC for more information.

Multicolor (RGB) LED (D24)

The phyBOARD-Pollux provides one multicolor (RGB) LED (D24) (see phyBOARD-Pollux Components (Top)). The LEDs are connected to a LED driver (NXP PCA9533/01) controlled by I2C2 bus.

EEPROM (U16)

The phyBOARD-Pollux provides a 2 kbit EEPROM (ST M24C02-RMC6TG) for general use. It is controlled by I2C2 bus. The EEPROMs write protection pin is connected to TP41. Write protection can be enabled by mounting R39 pull-up resistor. In this case, the EEPROM can be written if TP41 is tied to Ground only. The EEPROM I²C address can be fully customized by jumpers J30, 31, and 32. The default address is 0x51.

Global Board Reset (X_nRESET)

The X_nRESET signal (X_POR_B at phyCORE-i.MX 8M Plus) is used to hold all devices with an external reset pin in the reset state. X_nRESET will be released after all board voltages are powered up and allow the phyCORE-i.MX 8M Plus to boot. X_nRESET is brought out at several connectors like the Expansion Connector (X6). The X_nRESET signal can be used in two ways:

  1. While Power-cycle it can be held low for additional delay of the phyCORE-i.MX 8M Plus boot
  2. After X_nRESET is released and phyCORE-i.MX 8M Plus is booting, the 'Power cycle on Reset'-circuit is active. If X_nRESET is pulled low again for 60 ms to 360 ms, X_PMIC_RST_B is pulled low too for about 65 ms which leads to a power cycle of the phyCORE-i.MX 8M Plus PMIC similar to pushing die reset button S1.

This enables the user to better control phyBOARD-Pollux in a complex use-case with external hardware and makes sure all components are in sync with the processor and that a triggered reset will not create unpredictable states within the system.

X_nRESET Design Considerations

Note that there is a 10 kOhms pull-up resistor phyCORE-i.MX 8M Plus VDD_IO voltage. It is recommended to use this signal as an open drain.

Onboard Power Supplies

The phyBOARD-Pollux provides supply voltages on several connectors to power external devices. Be sure not to exceed the maximum permissible current that can draw from each power domain.

Voltage DomainMax. recommended additional current
VCC_12V_LVDS1500 mA
VCC_5V_MAIN, VCC_5V_SW, VCC_5V_MIPI_DSI, VCC_5V_AV, VCC_5V_LVDS1, VCC_5V_CAN1, VCC_5V_CAN2600 mA

VCC_3V3_SW, VCC_3V3_MIPI_DSI, VCC_3V3_LVDS1,  VCC_3V3_AV

800 mA
VCC_1V8_EXP_CON200 mA

In addition to that currents, phyBOARD-Pollux deliver current for USB_VBUS of X5 (2x 900 mA), phyCAM-M Interfaces (2x 1500 mA 3.3 V or 5 V depending von VCC_SELECT pin), HDMI connector (150 mA).

Warning

Drawing current may result in heating of the voltage regulators components and may require additional heat sinking.

Switches

phyBOARD-Pollux Switch Locations

phyBOARD-Pollux Switch Locations

System Reset Button (S1)

The phyBOARD‑Pollux is equipped with a system reset button at S1. Pressing this button will tie the X_PMIC_RST_B pin (X36 Pin C11) of the phyCORE-i.MX 8M Plus low, causing the module to reset with a complete power cycle.

System ON/OFF Button (S2)

The phyBOARD-Pollux is equipped with an ON/OFF button at S2 which is connected to X_ONOFF  of phyCORE-iMX 8M Plus. For more information, refer to the i.XM 8M Plus Reference Manual.

Boot Switch (S3)

The phyBOARD‑Pollux features a boot switch with four individually switchable ports to select the phyCORE-i.MX 8M Plus default bootsource. Descriptions on the various boot modes can be found in Boot Mode Selection. The figures below show a visual representation of each S3 switch setting:

eMMCInternal FusesSD Card

SPI NORUSB Serial DownloadTest Mode

BootConfiguration Options (S3)

Boot Mode Design Considerations

Bootpin voltages have to be valid when X_POR_B (X_nRESET at phyBOARD-Pollux) is released.

Additional System Level Hardware Information

I2C Connectivity

The I2C1 interface of the i.MX 8M Plus is only available on the phyCORE module and is not connected to the phyBOARD‑Pollux. The table below provides a list of the connectors and pins with I2C connectivity and onboard devices. The I²C addresses are hexadecimal in 7-bit representation which is the default Linux representation.

I2C2 Interface 

Location or Address

phyCAM-M CSI2 Connector (X12)

SDA pin 23, SCL pin 22

Mini PCIe Connector (X10)

SDA pin 30, SCL pin 32

Expansion Connector (X6)

SDA pin 11, SCL pin 13

STUSB4500 (U22)

0x28

TUSB8042A (U3)

0x44
PCA9533D/01 (U21)0x62
M24C02-RMC6TG (U16)0x51

I2C2 Connectivity

I2C3 Interface 

Location or Address

phyCAM-M CSI2 Connector (X11)

SDA pin 23, SCL pin 22

I2C3 Connectivity

I2C4 Interface 

Location or Address

A/V Connector (X15)

SDA pin 22, SCL pin 24

Display Connector (X24)

SDA pin 29, SCL pin 27
MIPI DSI Connector (X21)SDA pin 30, SCL pin 28

I2C4 Connectivity

To avoid any conflicts when connecting external I2C devices to the phyBOARD‑Pollux, the addresses of the onboard I2C devices must be considered. The table below lists the addresses already in use the default address is printed bold. The I²C addresses are hexadecimal in 7-bit representation which is the default Linux representation.

BusConnectorProd. No.Addresses
I2C2phyCAM-M CSI2 Connector (X12)VM-016-xxx-M0x10, 0x18
VM-x17-xxx-M0x36, 0x37
VM-017-xxx-L0x36, 0x37, 0x18
VZ-0180x3D, 0x38

Reserved I2C Addresses

Revision History

Date

Version #

Changes in this manual



26.01.2021



L-1009e.A0

Preliminary Manual
Describes the phyCORE‑i.MX 8M Plus
SOM Version: 1549.0
Describes the phyBOARD-Pollux
PCB Version: 1552.0


28.07.2021


L-1009e.A1

Manual update
SOM Version: 1549.2
PCB Version: 1552.1