Introduction

This guide is intended to assist in the design of an FPSC Gamma Feature Set module when creating the schematic and layout of the carrier board. Recommendations are given to strategically prepare your design for other compatible FPSC modules. This design-in guide can be used as a companion document to help understand our carrier board, which is intended to serve as a reference design for customer carrier board designs. There are several factors that need to be considered before designing a carrier board:

• Carrier board schematic
• SoM/Carrier board hardware manual
• FPSC Feature Set 24A.0 Specifications (LAN-118e.A1)
• Soldering Guide - FPSC-Based Products Fused Tin Grid Array (FTGA) Information (LAN-128e.A1)

All of these guides/manuals can be found on the following product pages:

• phyCORE-i.MX 8M Plus FPSC
• phyCORE-I.MX 95 FPSC
• phyCORE-AM62Lx FPSC
• phyCORE-AM62Px FPSC (COMING SOON)

FPSC Footprints

There are three different footprint recommendations from which you can choose the right one for your design:

• Size L: The largest footprint available. It offers the greatest flexibility as it can accommodate all available module sizes. This format is particularly 'future proof' as it allows for easy upgrades to more powerful modules.
• Size M: This footprint is specifically designed for high-power modules. It can also accommodate size S modules, but not size L.
• Size S: The smallest footprint, suitable for medium and low-power modules.

The larger the footprint selected, the more options are available for mounting different performance classes. At the same time, it is a common requirement to keep the design as compact as possible. This means that you have to choose between available board space and an option for upgrading to higher performance in the future. When designing new FPSC modules, PHYTEC always strives to have the smallest possible footprint. 

The above graph and table show the compatibility of each footprint size to the FPSC modules. Using this, you can see the range of SoMs that are currently available for each size.

3 Feature Types

FPSC Gamma Feature modules have a concentric pinout with different zones: Core functionalities are located in the center while optional or future processor features can be routed to pins around the outside.

Must-have
All modules in a feature set are supported and provide the necessary interfaces to develop many products.

Preferred Signals
The Preferred Signals pins are routed to pins currently supported by many processors and should be considered for future System on Modules of the FPSC feature set.

Proprietary Signals
The third type allows the use of processor features that are not subject to standardization and is therefore unique to a processor. This allows the use of special and new processor features.

Design Checklist

This section provides an overview of the aspects to be considered in a design.

• Power supply and buffer capacitors on the connector
• External Pull-Ups (e.g. I2C and CMOS Inputs)
• Use nPWRREADY_OUT for Power-Sequencing
• RTC Backup
• Bootpins
• Alternative boot source
• Standard debug console

Power Supply Recommendation

Supply Voltage of the FPSC Gamma Feature Module

The recommended supply voltage is 5V +/- 5%. Many modules can also be supplied with 3.3 V. Please contact our sales department for more information. The supply voltage and supply current should be ramped up continuously. Peaks and/or dips should be avoided in order not to jeopardize the function of the module. 47 µF capacitance should be placed close to the solder connection.

FPSC Gamma Feature

Module Power Consumption

The worst-case power consumption of the module should be assumed to be 15 W. In practice, this power is not drawn because this value is obtained by adding several worst-case currents. A maximum power consumption of 8 W is more realistic, because the CPUs, the internal units such as NPU, GPU, and IPU, and the external units such as RAM, eMMC, and Ethernet PHY do not work simultaneously and continuously at 100% capacity. Since embedded systems are generally designed with volume costs in mind, minimizing power consumption is an important measure to achieve this goal. Low-cost voltage regulators on your custom baseboard and a low-cost external power supply can save a lot of money as well as volume and weight.

A good way to determine the power profile required for your application is to use the current transformer integrated into the development board. The measured instantaneous current can be evaluated and optimized as a voltage via test points.

Power Sequencing

All PHYTEC modules have an internal power management system (PMIC) that controls the individual processor voltages and control signals. Complex processors can go into unpredictable states if their power sequencing is incorrect. It is therefore imperative that the specified power sequencing is not affected.

Power-up

All PHYTEC modules start power-up sequencing automatically after the supply voltage is applied.

To simplify the design-in, the power-up in PHYTEC modules is optimized for three control lines:

• nPWRREADY_OUT (Pin U22)
• nRESET_OUT (Pin R22)
• nRESET_IN (Pin Y21)

nPWRREADY_OUT is an open-drain output on the module and requires an external pull-up resistor (<12V). nPWRREADY_OUT is pulled to GND by the SOM when all processor voltages are properly brought up. Once nPWRREADY_OUT is pulled to GND, voltages can be applied to the processor pins (e.g., push-pull outputs and pull-up/pull-down resistors). Use nPWRREADY_OUT to control the power to the peripherals connected to the module on your custom baseboard.

nRESET_OUT is an open-drain output on the module with an internal pull-up resistor (1.8 V). nRESET is held to GND during power sequencing. After nPWRREADY_OUT is also pulled to GND, nRESET_OUT may held to GND for several microseconds. All baseboard peripheral voltages must have ramped up during this time. If it takes more time for these voltages to ramp up, nRESET_IN can be held at GND on the baseboard for as long as necessary. Once nRESET_OUT is switched to high impedance, the processor will begin the boot process. You should connect nRESET_OUT to the reset inputs of your baseboard peripherals. nRESET_OUT is not intended to perform a CPU reset! Use nRESET_IN (Pin Y21) instead (see below).

nRESET_IN is an open-drain input on the module with an internal pull-up resistor (1.8 V). nRESET_IN is intended to perform a CPU reset. On falling edge and depending in the module, the module will cycle some or all module power-rails to reset the module properly. In this case, nPWRREADY_OUT may switch to a High-Z state as described above. nRESET_IN can be used to delay the boot process by holding it on GND during power-up. After Power-up and on rising edge the the processor will begin the boot process.

When designing power sequencing your baseboard, consider the case of a brief loss of external power. You may be using peripherals that operate with a power-on reset. To ensure that these peripherals are always in a defined state, an additional discharge of the voltages switched via nPWRREADY_OUT is often a useful addition.

Example Circuit for Power Sequencing:

Two internal voltage regulators are needed. The 5V and 3V3 voltages come from the external power supply (VCC_IN). For power-ups, defined voltages and timings are important. The circuit below generates VCC_3V3 only when VCC_5V_MAIN is already powered up. This means the switches are always safe to turn off before the voltage reaches the threshold for Q13. 

The SOM_PWRREADY signal is free of glitches that could accidentally turn on switches U3-5. Connect the SOM to VCC_5V_MAIN. All baseboard circuits are connected to VCC_5V_SW, VCC_3V3_SW, and VCC_1V8_SW. VCC_1V8_SW uses the VCC_1V8_OUT voltage from the SOM to power the circuits. If there are few loads on the baseboard, you can skip the voltage regulator for VCC_3V3 and use the voltage VCC_3V3_OUT from the SOM.

Transistors Q11, 12, and 14 are a simple discharge circuit for the switched voltages. They also reset the circuit parts of the baseboard that need it.

Power-cycle / Reset

nRESET_IN (pin Y21) is an open-drain input with an internal pull-up resistor (1.8 V). Use nRESET_IN to trigger a reset or power-cycle the module. You can connect nRESET_IN to a push-button or GPO.

On the falling edge of nRESET_IN, the module starts the reset sequence. nPRWREADY_OUT (U22) may be set to HIGH-Z during that.

On the rising edge of nREST_IN the the processor will begin the boot process and nRESET_OUT will be set to a High-Z state.

Voltage Outputs

PHYTEC modules of feature set 24A provide 3.3 V (pins AA24, AB25) and 1.8 V (pins AA20, AB21) for use on your baseboard. Please note that both voltages must be switched on your baseboard via nPWRREADY_OUT (pin U22) to avoid malfunctions of the processor (see above). The minimum current that can be drawn is 200 mA. The maximum current that can be drawn depends on the available line reserve of the PMIC on the module.

IO Voltage

This feature set has a fixed IO voltage of 1.8V. This makes it easy to design a universal baseboard so different modules can be used interchangeably. You can also choose the IO voltage at the module level, between 1.8 V and 3.3 V. Depending on the processor, you can change all IOs or only some. If you need a different IO voltage, please contact our sales team.

Additional FPSC-specific Circuitry

Boot Source Selection

FPSC Gamma Feature provides 4 signals for boot source selection. The signals BOOT_MODE0 (Pin AA4), BOOT_MODE1 (Pin AA5), BOOT_MODE2 (Pin AA6), and BOOT_MODE3 (Pin AA7) are usually connected directly to the processor. The processor evaluates the boot mode with the rising nRESET edge. On PHYTEC modules, the internal eMMC is always set as the default boot source if the signals for boot source selection on the baseboard are not connected (open). If you require a different boot source for your application, you can adjust the internal preset boot source to your requirements by using <=1 kOhm resistor against 1.8 V or GND. For more detailed information on boot source selection, please refer to the respective module hardware manual.

RTC Backup

The RTC used on the module has a so-called 'trickle charger'. Connect VCC RTC (pin AC7) directly to a gold cap to charge it via the RTC.

Interface Specific Circuits

UART

There are 3 UART interfaces with different prioritization:

• Primary Debug Interface for debug outputs of the main CPU
• Special Debug Interface for debug outputs of the support CPU (if available)
• A normal UART interface with no special function for the baseboard

All UARTs work as DTE (TxD and RTS are outputs, RxD and CTS are inputs). Under certain circumstances, the signal direction can be reversed within the CPU. You can find more information on this in the processor datasheet.

Example circuit for USB debug interface with USB-C socket:

U15 is wired as bus-powered. The level shifters U1 and U2 avoid dark currents in the SOM. Galvanic isolation of ground and shield at the USB-C connector can be useful. However, it must be ensured that this galvanic isolation is not inadvertently short-circuited elsewhere.

An example circuit for a UART-RS-232 converter:

An example circuit for a UART-RS-485 half-duplex converter:

CAN(-FD) Interface

If a processor supports CAN-FD, it can be used on the baseboard with an appropriate transceiver. Due to its backward compatibility, CAN-FD can also be used in a CAN system.

An example circuit of a CAN-FD interface:

The type of bus termination must be implemented depending on the application. Split termination is usually recommended. Attention must be paid to the maximum power loss in the termination. The circuit can be supplemented with a CAN common mode choke if required.

I²C Interface

The modules provide up to 5 I²C interfaces. I2C1 is used to connect various ICs to the processor on the module. If possible, I2C1 should not be used on the baseboard. If I2C1 is used on the baseboard, no pull-up resistors should be provided for it. The I²C interfaces 2-5 each require pull-up resistors against 1.8 V. Please note the maximum permitted output low current of 3 mA according to the I²C specification.

An example circuit of an I²C level shifter:

SD-Card Interface

The module provides the power supply for the SD card. The interface allows different "bus speed modes" that the SD card can negotiate with the host processor. No additional circuitry is required on the baseboard (except capacitors for VCC) as the module implements the logic for this. The CD and WP signals have an internal pull-up.

An example circuit for a micro SD card interface:

The series termination resistors R108-113 and capacitors C257, 44, 390, and 419 should be placed as close as possible to the SD card slot, with capacitor C258 closer to the SOM.

SDIO

The 4-bit SDIO interface can be used, for example, to connect an additional SD card or a WLAN module. The IO voltage can be set at the hardware level of the module. The IO voltage is set to 1.8 V by default. For your application, you should use VREF Out (pin DD4) if your application requires the presence of the IO reference voltage. Unlike the SD card interface, the CD (pin DD3) and WP (pin DF3) signals do not have any additional internal pull-up resistors against VREF Out (pin DD4). If required, these must be provided on your baseboard.

USB

Ensure that differential routing, correct impedance matching, and length matching are adhered to. For detailed guidelines and specifications, please refer to the "Design Constraints" section.

USB 2

Use VBUS (pin CB7/CA7) to supply the USB unit of the processor with 5 V. The signals PWR_EN (pin CA6/CA9) and OC (pin CA5/CA8) can be connected to a USB power switch and may require pull-up or pull-down resistors.

USB 3

The coupling capacitors of the TX data line pairs are located on the module. Please note that all signals specific to USB3 are not part of the must-have signals and therefore this feature set is not available with all modules. Furthermore, the line pairs USB1 TX1 (pin CF3/CF4), USB1 RX1 (pin CD3/CD4), USB2 TX1 (pin CF9/CF10) and USB2 RX2 (pin CD9/CD10) are defined as proprietary in this feature set. If you want to use a USB-C socket for your application, a multiplexer for these SS signals is recommended to ensure interchangeability between different modules of this feature set. This is not relevant for all other USB3 sockets because all other USB3 plugs have a coding and can only be plugged in in one direction.

If only one USB3 bus is available for a module, this is always USB1.

Example circuit with type A socket:

An example circuit with USB-C socket as dual-role:

U30 can be omitted under certain circumstances if the multiplexing of the USB3 signals can be handled within the processor, as with the PCL-079 (NXP i.MX 95).

Gb Ethernet

A Gb Ethernet PHY is available on all modules in this feature set. You can connect the Gb Ethernet signals to a network connection on your baseboard using a suitable transformer. The Gb Ethernet interface is backward compatible with 10/100 Ethernet and can be used in 10/100 networks without adapting your baseboard. The Gb-Ethernet-PHY independently negotiates the data rate and signal polarity with the remote station. The LED Link and LED Activity signals (pins CB1 and CB3) can be connected to LEDs with a series resistor (max. 30 mA). Ensure that differential routing, correct impedance matching, and length matching are adhered to. For detailed guidelines and specifications, please refer to the "Design Constraints" section.

An example circuit of a Gb Ethernet interface:

RGMII

The RGMII interface can be connected directly to a Gb Ethernet PHY. If the processor supports TSN, then it is available on this interface. The EVENT In (pin BB9) and EVENT Out (pin BC9) signals are available for time measurement in a TSN network. It is possible to connect a 10/100 Ethernet PHY. Please note that the I/O voltage is still 1.8 V. A 2.2 kOhms pull-up resistor must be connected externally to the MDIO signal. nINT (pin BA10) should be connected to the interrupt output of the Ethernet PHY. The TX lines have a series termination on the module. This can be individually adapted to your circuit if required.

An example circuit for a Gbit Ethernet PHY on an RGMII interface:

The series termination resistors R103, 104, and RN17 should be placed close to U25. Test pads in the TX signals can be a useful addition for evaluating signal integrity and timings. The wiring of the crystal XT2 is dependent on U25 and should not be generalized. The generation of the voltages VCC_2V5_ETH0, VCC_1V0_ETH,0, and VCC_1V8_ETH0 as well as the strap resistors are not part of this example and depend on the Ethernet PHY.

Quad-SPI

When using Quad-SPI, please note that the DQS signal is not part of the must-have signals and is therefore not available with all processors. You can find more information on the availability of DQS in the respective module manual.

An example circuit of an SPI-NOR with QSPI:

HDMI

External pull-up resistors and a level shifter to 5 V must be provided for the HDMI I2C bus. There are specialized ICs on the market for this purpose that integrate protective circuitry, current limiting, and level shifters for the HDMI interface. An example circuit can be found in the circuit diagram of the development board. A 1 µF coupling capacitor is required on your baseboard for the EARC signals (pin AD17 and AE17). Due to the dual function with HDMI HPD and HDMI UTILITY, these cannot be placed on the module. Ensure that differential routing, correct impedance matching, and length matching are adhered to. For detailed guidelines and specifications, please refer to the "Design Constraints" section.

An example circuit of an HDMI interface:

The resistor networks RN11-14 serve as placeholders for common mode chokes and can be omitted if required. The coupling capacitor C407 can be adapted if necessary. The diodes D39-41 prevent incorrect power supply to the base board via the connected screen.

ADC

Make sure that the maximum permissible analog voltage of 1.8 V is not exceeded on the baseboard. There is no additional circuitry on the module so the frequency behavior of the ADC is not affected. Further information on the ADC can be found in the respective processor datasheet.

An example circuit of ADC inputs with 5V input voltage:

The diodes dissipate overvoltages and undervoltages. The voltage dividers and smoothing capacitors can be adapted to the application or replaced by impedance converters.

PCIe

The coupling capacitors of the clock and TX data line pairs are located on the module. Please note that the IO voltage on the PCIe connectors is specified by the PCI consortium as 3.3 V nominal voltage. This means that at least for the nPERST signal (pin AE11 and BE3) and nCLKREQ signal (pin AD12 and BE1) on your baseboard a level adjustment of between 1.8 V and 3.3 V must be provided. If your application requires I2C on the PCIe connector, a level adjustment must also be provided there. There are Mini PCIe cards that are compatible with 1.8 V IO voltage and therefore exceed the PCI specification. Ensure that differential routing, correct impedance matching, and length matching are adhered to. For detailed guidelines and specifications, please refer to the "Design Constraints" section.

An example circuit of a Mini PCIe interface:

Q5 and Q6 realize the necessary level adjustment to 3.3 V for nCLKREQ and nPERST. The level adjustment for I2C and voltage generation of VCC_1V5_MPCI are not part of this example.

SAI

Please note that MCLK signals (pin BD5) are not part of the must-have signals and are therefore not available with all processors. If you require a dedicated clock for audio for your application (e.g. in conjunction with an audio codec), you should provide an oscillator on your baseboard to ensure interchangeability between different modules of this feature set. You can find more information on the availability of MCLK in the respective module manual.

An example connection of an audio codec to an SAI interface:

OZ2 can be equipped or not equipped depending on the availability of the MCLK signal. The voltage generation and the additional power amplifier (PWR_AMP_IN) are not part of the example.

CSI Camera Interface

For simple camera integration, the phyCAM-M is the recommended CSI-based interface. phyCAM-M camera modules are supplied with 3.3 V or 5 V depending on the VDD_SELECT line. phyCAM-M camera modules use 3.3 V logic voltage, so a level adjustment of nRESET, I2C, and, if necessary, CTRL. The resistor networks RN1-RN5 can be used as placeholders for common mode chokes or be omitted. Ensure that differential routing, correct impedance matching, and length matching are adhered to. For detailed guidelines and specifications, please refer to the "Design Constraints" section.

Recommended Baseboard PCB Stackup

The following layer structures can be used as a reference for the base board. With these layer structures, 45-50 Ohm single-ended and 85-100 Ohm differential impedance +/- 2 Ohm are possible. At the same time, this layer structure guarantees the fan-out of the module.

Design Constraints

RGMII

Ethernet

USB

LVDS Display

MIPI-CSI / MIPI-DSI

HDMI

PCIe

SDIO

QSPI

SPI

CAN

If a processor supports CAN-FD, it can be used on the baseboard with an appropriate transceiver. Due to its backward compatibility, CAN-FD can also be used in a CAN system.

UART

I2C

SAI

ADC

GPIO / PWM

JTAG

Revision History

Contact Information

If you have any questions, design considerations, or are interested in further information, please contact your nearest PHYTEC office.

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