L-863e.A0 phyCORE-i.MX 8M / phyBOARD-Polaris (1497.2 / 1501.2) Hardware Manual

Table of Contents

L-863e.A0 phyCORE-i.MX 8M / phyBOARD-Polaris (1497.2 / 1501.2) Hardware Manual
Document TitleL-863e.A0 phyCORE-i.MX 8M / phyBOARD-Polaris (1497.2 / 1501.2) Hardware Manual
Article NumberL-863e.A0
Release Date25.10.2019
SOM Prod. No.PCL-066
SOM PCB No.1497.2


SBC Prod. No.:PB-02419-xxxI.Ax
CB PCB No.: 1501.2


Edition:October 2019

Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (™ or ®) and copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents and trademarks are similarly not expressly indicated in this manual.

The information in this document has been carefully checked and is considered to be entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result.

Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so.

@ Copyright 2019 PHYTEC Messtechnik GmbH, D-55129 Mainz.

Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH.

 

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Address:

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INDIA

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4018 Jin Tian Road
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CHINA 518026

Ordering Information:

+49 6131 9221-32
sales@phytec.de

+1 800 278-9913
sales@phytec.com

+33 2 43 29 22 33
info@phytec.fr

+91-80-4086 7046/48
sales@phytec.in
+86-755-3395-5875
sales@phytec.cn

Technical Support:

+49 6131 9221-31
support@phytec.de

+1 206 780-9047
support@phytec.com


support@phytec.fr

+91-80-4086 7047
support@phytec.in

support@phytec.cn

Fax:

+49 6131 9221-33

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Web Site:

http://www.phytec.de
http://www.phytec.eu

http://www.phytec.com

http://www.phytec.fr

http://phytec.inhttp://www.phytec.cn

Conversions, Abbreviations, and Acronyms

This hardware manual describes the PCL-066 System on Module, referred to as phyCORE®-i.MX 8M, and the PB-02419-xxxI.Ax, referred to as phyBOARD®-Polaris . This manual also specifies the phyCORE-i.MX 8M and phyBOARD-Polaris' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M microcontrollers can be found in the i.MX 8M Microcontroller Data Sheet/Reference Manual.

Tip

Due to part maintenance for our products (which are subject to continuous changes), we refrain from providing detailed, part specific information within this manual. Please read the section Product Change Management and Information Regarding Parts Populated on the SOM / SBC  within the Preface for more information.

Tip

The BSP delivered with the phyCORE-i.MX 8M usually includes drivers and/or software for controlling all components such as interfaces, memory, etc. Programming close to hardware at register level is not necessary in most cases. For this reason, this manual does not contain detailed descriptions of the controller's registers or information relevant for software development. Please refer to the i.MX 8M Reference Manual, if any information not found in this manual is needed to connect customer designed applications.

Conventions

The conventions used in this manual are as follows:

  • Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low or are driving low.
  • A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
  • The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the address byte. The correct value of the LSB, which depends on the desired command (read (1), or write (0)), must be added to get the complete address byte. For example, if the given address in this manual is 0x41 =>, the complete address byte = 0x83 to read from the device and 0x82 to write to the device
  • Tables which describe all settings show the default position in bold,bluetext.

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document.

AbbreviationDefinition
BGABall Grid Array

BSP

Board Support Package (software delivered with the Development Kit including an operating system (Windows or Linux) preinstalled on the module and development tools)

CB

Carrier board; used in reference to the phyCORE development kit carrier board

EMI

Electromagnetic Interference

GPI

General purpose input

GPIO

General purpose input and output

GPO

General purpose output

IRAM

Internal RAM; the internal static RAM on the NXP® Semiconductor i.MX 8M microcontroller

J

Solder jumper; these types of jumpers require solder equipment to remove and place

JP

Solderless jumper; these types of jumpers can be removed and placed by hand with no special tools

OEMOriginal Equipment Manufacturers

PCB

Printed circuit board

PCMProduct Change Management
PCNProduct Change Notification

PMIC

Power management IC

RTC

Real-time clock

SBCSingle Board Computer

SMT

Surface mount technology

SOM

System on Module; used in reference to the PCL-066 /phyCORE®-i.MX 8M module

Sx

User button Sx (e.g. S1, S2, etc.) used in reference to the available user buttons, or DIP-Switches on the carrier board

Sx_y

Switch y of DIP-Switch Sx; used in reference to the DIP-Switch on the carrier board

VMVirtual Machine

Abbreviations and Acronyms used in this Manual

Preface

As a member of PHYTEC's phyCORE® product family, the phyCORE‑i.MX 8M is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers, various types of memory (RAM, NAND flash, eMMC), and many other features. This, in turn, offers increased types of functions and configurations. PHYTEC supports a variety of 8/16/32/64 bit controllers in two ways:

  1. As the basis for Rapid Development Kits which serve as a reference and evaluation platform
  2. As insert-ready, fully functional phyCORE® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "reinvent" microcontroller circuitry. Furthermore, much of the value of the phyCORE® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on the product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative, full-system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Ordering Information

The part numbering of the phyCORE has the following structure:

Ordering Information PCL-066

Product Specific Information and Technical Support

In order to receive product specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our website which provides product specific information, such as errata sheets, application notes, FAQs, etc.
http://www.phytec.de/support/knowledge-database/soms-system-on-modules/phycore/phycore-imx-8m/ 
or
https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-download/

Note

Assembly Options include choice of Controller, RAM (Size/Type), Size of NAND Flash, interfaces available, vanishing, temperature range, and other features. Please contact our sales team to get more information on the ordering options available.


Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 8M 

PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

Warning

PHYTEC products lacking protective enclosures are subject to damage by ESD and, therefore, must be unpacked, handled, or operated in environments in which sufficient precautionary measures have been taken in respect to ESD-dangers. Only appropriately trained personnel such as qualified electricians, technicians, and engineers should handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than 3 m.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Tip

Implementation of PHYTEC products into target devices, as well as user modifications and extensions of PHYTEC products, is subject to renewed establishment of conformity to and certification of Electro Magnetic Directives. Users should ensure conformity following any modifications to a product as well as implementation of a product into target systems.

Product Change Management and Information Regarding Parts Populated on the SOM / SBC

With the purchase of a PHYTEC SOM / SBC you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts which are used in our products. Possible impacts to the functionality of our products due to changes of functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware / software design.

Our general philosophy here is: We will never discontinue a product as long as there is demand for it.

To fulfill this, we have established a set of methods to fulfill our philosophy:

Avoidance strategies:

  • Avoid changes by evaluating longevity of parts during design-in phase.
  • Ensure availability of equivalent second source parts.
  • Stay in close contact with part vendors to keep up with roadmap strategies.

Change management in rare event of an obsolete and non-replaceable part:

  • Ensure long term availability by stocking parts through last time buy management according to product forecasts.
  • Offer long term frame contract to customers.

Change management in cases of functional changes:

  • Avoid impacts on product functionality by choosing equivalent replacement parts.
  • Avoid impacts on product functionality by compensating changes through hardware redesign or backward compatible software maintenance.
  • Provide early change notifications concerning functional, relevant changes of our products.

We refrain from providing detailed part specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

  • QS Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a BSP, the device tree, and accessing peripherals.
  • Hardware Manual:  A detailed description of the System on Module and accompanying carrier board. 
  • Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; introducing, installing, and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
  • BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
  • Development Environment Guide:  This guide shows how to work with the Virtual Machine (VM) Host PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running demo projects for these progams on a phyCORE product as well. Information on how to build a Linux host PC yourself is also a part of this guide.
  • Pin Muxing Table:  phyCORE SOMs have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an applicaiton. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case by case basis. Most of the documentation can be found in the applicable download page of our products.

phyCORE-i.MX 8M Introduction

The phyCORE‑i.MX 8M belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all EMI (Electro Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 20 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high noise environments.

phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 8M is a subminiature (40 mm x 55 mm) soldered System on Module populated with the NXP® Semiconductor i.MX 8M microcontroller. Its universal design enables it to be inserted into a wide range of embedded applications. All controller signals and ports extend from the controller to a 1,27mm Pitch BGA Ball. Each signal ball has an associated GND pin which ensures the GND reference for each signal. The ball packages are placed in lines. There is enough space between lines to ensure the possibility to easy routing out of the package. Signal balls for high speed signal like HDMI are placed on the outer lines, making it easy to route to the top layer of the carrier board. The SOM is designed to support carrier boards with as littile as 6 layers to reduce PCB costs. For proper EMC characteristics, it is necessary to place the processor caps directly under the SOM. This required a hole in the carrier board.

The descriptions in this manual are based on the NXP® Semiconductor i.MX 8M. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 8M.

phyCORE-i.MX 8M Features

The phyCORE‑i.MX 8M offers the following features:

  • Insert-ready, sub-miniature (55 mm x 40 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology
  • Mounted using BGA Technology
  • Populated with the NXP® Semiconductor i.MX 8M microcontroller (BGA624 packaging)
  • Up to 4 ARM-A53 cores (clock frequency up to 1.5 GHz)
  • Boot from different memory devices (eMMC Flash standard)
  • Single supply voltage of +3.3 V with onboard power management
  • All controller-required supplies are generated on board
  • Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins
  • 512MB (up to 4GB[1]) LPDDR4 RAM

  • 4GB (up to 128GB[1]) onboard eMMC
  • 4MB (up to 64MB[1])Quad SPI Nor Flash
  • 4kB[1] I2C EEPROM
  • Two High-Speed USB 3.0 interfaces
  • 10/100/1000 Mbit Ethernet interface (either with Ethernet transceiver on the phyCORE-i.MX 8M enabling a direct connection to an existing Ethernet network, or without onboard transceiver and using the RGMII signals at TTL-level at the signal pins instead.)[2]

  • 802.11 b/g/n WLAN/Bluetooth V4.2 (optional)
  • Four I2C interfaces
  • Two SPI interfaces (NAND/QSPI)
  • PCIe interface
  • Four UART interfaces
  • Four PWM outputs
  • MIPI DSI interface
  • HDMI interface
  • Two MIPI CSI camera interface
  • SDIO interface
  • SAI Audio interface
  • Internal RTC
  • Available for different temperature grades (see Product Temperature Grades)
    1.

    The maximum memory size listed as of the printing of this manual. Please contact PHYTEC for more information about additional or new module configurations available.

    2.
    Please refer to the order options described in the Preface or contact PHYTEC for more information about additional modules configurations.
     

phyCORE-i.MX 8M Block Diagram

 

phyCORE-i.MX 8M Block Diagram

phyCORE-i.MX 8M Component Placement

phyCORE-i.MX 8M Component Placement (Top View)

phyCORE-i.MX 8M Component Placement (Top View)

phyCORE-i.MX 8M Component Placement (Bottom View)

phyCORE-i.MX 8M Component Placement (Bottom View)

phyCORE-i.MX 8M Minimum Operating Requirements

Warning

We recommend connecting all available +3.3 V input pins to the power supply system on a custom carrier board housing the phyCORE-i.MX 8M and, at minimum, the matching number of GND balls neighboring the +3.3 V balls. In addition, proper implementation of the phyCORE-i.MX 8M module into a target application also requires connecting all GND balls.
Refer to Power for more information.

Pin Description

Warning

Module connections must not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller manuals/data sheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.   

All controller signals extend to BGA Signal Balls (1.27 mm) This allows the phyCORE‑i.MX 8M to be soldered into any target application like a "big chip".

PHYTEC provides an complete pinout table for the phyCORE-i.MX 8M Mini Connector (X31). This table contains a complete signal path for the phyCORE‑i.MX 8M and the carrier board phyBOARD-Polaris, including signal names, pin muxing paths, and descriptions specific to each pin. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found with the pinout table.

https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/phyCORE-i.MX8M_Pin_Muxing_Table.A0.xlsx

Warning

  • The NXP® Semiconductor i.MX 8M is a multi-voltage operated microcontroller and, as such, special attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other onboard components. Please refer to the NXP Semiconductor i.MX 8M Reference Manual for details on the functions and features of controller signals and port pins.
  • As some of the signals which are brought out on the phyCORE-Connector are used to configure the boot mode for specific boot options, please make sure that these signals are not driven by any device on the baseboard during reset. The signals which may affect the boot configuration are shown in table phyCORE-Connector Boot Configuration Pins.
  • It is necessary to avoid voltages at the IO pins of the phyCORE-i.MX 8M which are sourced from the supply voltage of peripheral devices attached to the SOM during power-up or power-down. These voltages can cause a current flow into the controller, especially if peripheral devices attached to the interfaces of the i.MX 8M are supposed to be powered while the phyCORE‑i.MX 8M is in suspend mode or turned off. To avoid this, bus switches either supplied by VDD_3V3 on the phyCORE side or having their output enabled to the SOM controlled by the X_PGOOD_OD signal (see Supply Voltage for External Logic) must be used.

Tips

  • Most of the controller pins have multiple multiplexed functions. As most of these pins are connected directly to the phyCORE-Connector, the alternative functions are available by using the i.MX 8M's pin muxing options. Signal names and descriptions in the accompanying table, however, are in regards to the specification of the phyCORE‑i.MX 8M and the functions defined. Please refer to the i.MX8M Reference Manual or the schematic to get to know about alternative functions. In order to utilize a specific pin's alternative function, the corresponding registers must be configured within the appropriate driver of the BSP.
  • The following tables describe the full set of signals available at the phyCORE‑Connector according to the phyCORE-i.MX 8M specification. However, the availability of some interfaces is order-specific (e.g. Camera_0). Thus, some signals might not be available on your module.
  • If the phyCORE-i.MX 8M is delivered with the carrier board phyBOARD‑Polaris, the pin muxing might be changed within the appropriate BSP in order to support all features of the carrier board. If so, information on the differences from the pinout given in the following tables can be found in the carrier board's documentation.

Jumpers

For configuration purposes, the phyCORE‑i.MX 8M has several solder jumpers, some of which have been installed prior to delivery. Typical Jumper Pad Numbering Scheme illustrates the numbering scheme for the various solder jumper pads. Jumper Locations (Top View) and Jumper Locations (Bottom View) indicate the location and the default configuration of the solder jumpers on the board.

The table Jumper Settings provides a functional summary of the solder jumpers which can be changed to adapt the phyCORE‑i.MX 8M to specific design needs. It shows their default positions, and possible alternative positions and functions. A detailed description of each solder jumper can be found in the applicable chapter listed in the table.

Tip

Jumpers not listed should not be changed as they are installed with regards to the configuration of the phyCORE‑i.MX 8M.

Typical Jumper Pad Numbering Scheme

Typical Jumper Pad Numbering Scheme

If manual jumper modification is required, please ensure that the board as well as surrounding components and sockets remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable.  If soldered jumpers need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Warning

If any modifications to the module are performed, regardless of their nature, the manufacturer guarantee is voided.

Jumper Locations (Top View)

Jumper Locations (Top View)

Jumper Locations (Bottom View)

Jumper Locations (Bottom View)

Pay special attention to the “TYPE” column to ensure you are using the correct type of jumper (0 Ohms, 10k Ohms, etc…). The jumpers are 0201 package with a 1/8 W or better power rating.

The jumpers (J = solder jumper) have the following functions.

JumperPositionDescriptionTypeSection
J5

1+2
Wifi Enable connected to GPIO1_IO10

0201










WIFI/Bluetooth
1+4GPIO1_IO10 available on BGA Ball (Default if WIFI/BT is not mounted)
2+3WLAN_EN available on BGA Ball
J61+2Bluetooth Enable connected to GPIO1_IO11

0201
1+4GPIO1_IO11 available on BGA Ball (Default if WIFI/BT is not mounted)
2+3BT_EN available on BGA Ball
J71+2WIFI_HCI_UART_WAKEHOST_L connected to GPIO1_IO08

0201
1+4GPIO1_IO08 available on BGA Ball (Default if WIFI/BT is not mounted)
2+3WIFI_HCI_UART_WAKEHOST_L available on BGA Ball
J81+2WIFI_WLAN_RF_KILL_L connected to GPIO1_IO09

0201
1+4GPIO1_IO09 available on BGA Ball (Default if WIFI/BT is not mounted)
2+3WIFI_WLAN_RF_KILL_L available on BGA Ball
J271+2RMGII IO Voltage set to 1.8V. 
0201


RGMII Interface


2+3RGMII IO Voltage set to 3.3V.
J341+2RTC_INT connected to GPIO1_IO05




0201


RTC
1+4GPIO1_IO05 available on BGA Ball (Default if WIFI/BT is not mounted)
2+3RTC_INT available on BGA Ball
J351+2GPIO1_IO06 available on BGA Ball


Ethernet

2+3RESET_ETHPHY connected to GPIO1_IO06
J361+2GPIO1_IO07 available on BGA Ball
2+3ETH0_INT connected to GPIO1_IO07
J371+2PMIC_nSDWN connected to GPIO1_IO14

0201

Power Management IC
1+4GPIO1_IO14 available on BGA Ball (Default if WIFI/BT is not mounted)
2+3PMIC_nSDWN available on BGA Ball





J282+3internal use only0201-

Jumper Settings

Power

The phyCORE‑i.MX 8M operates off of a single power supply voltage. The following section discuss the primary power pins on the phyCORE i.MX 8M Connector X1 in detail.

Primary System Power (VDD_IN_3V3)

The phyCORE‑i.MX 8M is powered by a primary voltage supply with a nominal value of +3.3 V. Onboard switching regulators generate the voltage supplies required by the i.MX 8M MCU and onboard components from the primary 3.3 V supplied to the SOM.

For proper operation, the phyCORE‑i.MX 8M must be supplied with a voltage source of 3.3 V ±5 % with 3 A load at the VCC pins on the phyCORE.

                VDD_IN_3V3:                        X1 → A65, A66, A67, A68

Connect all +3.3 V VCC input pins to your power supply and, at minimum, the matching number of GND pins.

                Corresponding GND:           X1 → B33,B34

Please refer to the section Pin Description for information on additional GND Pins located at the phyCORE i.MX 8M Connector X1.

Warning

As a general design rule, PHYTEC recommends connecting all GND pins neighboring signals which are being used in the application circuitry. For maximum EMI performance, all GND pins should be connected to a solid ground plane.

Power Management IC (PMIC) (U2)

The phyCORE-i.MX 8M provides an onboard Power Management IC (PMIC) at position U2 to generate different voltages required by the microcontroller and the onboard components. The PMIC supports many functions like different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 8M via the onboard I2C bus (I2C1). The I2C address of the PMIC is 0x08.

The PMIC Shutdown is controllable either by GPIO or by an external signal from the carrier board. If the signal is controlled by the carrier board, GPIO1_IO14 is available as a normal GPIO on the carrier board. The table below shows the differnt jumper options:

J37PMIC_nSDWNX_GPIO1_IO14
GPIO1_IO141+2 (Default)
1+4
X_PMIC_nSDWN2+3

PMIC Shutdown J37 Settings

Power Domains

External voltages:

  • VDD_IN_3V3 3.3 V main supply voltage
  • USB0_VBUS USB0 bus voltage, must be supplied with 5 V if USB0 is used (does not exceed 5.25V)
  • USB1_VBUS USB1 bus voltage, must be supplied with 5 V if USB1 is used (does not exceed 5.25V)
  • VRTC  Backup Supply for RTC (40nA)

External Logic Supply Voltage

The voltage level of the phyCORE’s logic circuitry is VDD_3V3 (3.3 V) or VDD_1V8 (1.8V) which is derived from the SOM main input voltage, VDD_IN_3V3. In order to follow the power-up and power–down sequencing mandatory for the i.MX 8M, external devices have to be supplied by the I/O supply voltage VDD_3V3 or VDD_1V8 which is brought out at pin A53/A54 (VDD_3V3) and A91/A92 (VDD_1V8) of the phyCORE-Connector. Use of VDD_3V3_LOGIC ensures that external components are only supplied when the supply voltages of the i.MX 8M are stable.

Warning

The current draw for VDD_3V3 and VDD_1V8 must not exceed 100 mA. Consequently, this voltage should only be used as a reference or supply voltage for level shifters, not for supplying purpose. If devices with a higher power consumption are connected to the phyCORE‑i.MX 8M, their supply voltage should be switched on and off by use of the X_PGOOD_OD signal. This way, the power-up and power–down sequencing will be considered even if the devices are not supplied directly by VDD_3V3 or VDD_1V8. Additionaly, a voltage supervisor should be added on the carrier board. This supervisor should be powered by VDD_3V3 or VDD_1V8 and hold X_POR_B (A61) low, as long as the external generated voltages are not in proper shape.

If used to control or supply bus switches on the phyCORE side, VDD_3V3 (VDD_1V8) also serves to strictly separate the supply voltages generated on the phyCORE‑i.MX 8M and the supply voltages used on the carrier board/custom application. That way, voltages at the IO pins of the phyCORE-i.MX 8M, which are sourced from the supply voltage of peripheral devices attached to the SOM, are avoided. These voltages can cause a current flow into the controller, especially if peripheral devices attached to the interfaces of the i.MX 8M are supposed to be powered while the phyCORE‑i.MX 8M is in suspend mode or turned off. The bus switches can either be supplied by VDD_3V3 (VDD_1V8) on the phyCORE side or the bus switches' output enabled to the SOM can be controlled by X_PGOOD_OD to prevent these voltages from occurring.

Use of level shifters supplied with VDD_3V3 (VDD_1V8) allows the signals to be converted according to the needs of the custom target hardware. Alternatively, signals can be connected to an open drain circuitry with a pull-up resistor attached to VDD_3V3 (VDD_1V8).

Backup Power (VRTC / NVCC_SNVS)

To backup the RTC (U27), an external voltage source can be added at Pin E36. The RTC has an extremely low backup current consumption of only 40nA (@3V). It is also possible to supply the RTC and some critical registers of the i.MX 8M's low power domain (NVCC_SNVS). NVCC_NSNVS can be supplied over Pin E19 if VDD_IN_3V3 is not present. 

Warning

NVCC_SNVS should not be supplied externally if VDD_IN_3V3 is present! 

Reset

The X_nRESET_IN signal (Pin A62) on the phyCORE-Connector is designated as the reset input. Holding this pin low triggers a hard reset of the module. The external reset signal has a 10ms debouncing circuit. X_POR_B Signal (Pin A61) can be used to prevent bootup of the i.MX8M. This can be used as startup as described in the section Power Management IC

System Boot Configuration

Most features of the i.MX 8 microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

  • Boot mode selection
  • Boot device selection
  • Boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 8M after POR. The ROM code detects the boot mode by using the boot mode pins (BOOT_MODE[1:0]), while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO input pins (BOOT_CFGx[7:0]).

Boot Mode Selection

The boot mode of the i.MX 8M microcontroller is determined by the configuration of two boot mode inputs BOOT_MODE[1:0] during the reset cycle of the operational system. These inputs are brought out at the phyCORE processor pins X_BOOT_MODE[1:0] (D1, C1). The table phyCORE-i.MX 8M Boot Modes shows the possible settings of pins X_BOOT_MODE0 (C1) and X_ BOOT_MODE1 (D1) and the resulting boot configuration of the i.MX 8M.

Boot ModeX_BOOT_MODE1X_BOOT_MODE0Boot Source
00

0

0Boot from fuses
0101Serial Downloader
1010

Internal Boot (GPIO Overwrite)

1111Reserved

 phyCORE-i.MX 8M Boot Modes

The BOOT_MODE[1:0] lines have 10 kΩ pull-up and pull-down resistors populated on the module. Leaving the two pins unconnected sets the controller to boot mode 2, internal boot. For serial boot (boot mode = 1), the ROM code polls the communication interface selected, initiates the download of the code into the internal RAM, and triggers its execution from there. Please refer to the i.MX 8M Reference Manual for more information.

In boot mode 0 and 2, the ROM code finds the bootstrap in permanent memories such as NAND-Flash or SD-Cards and executes it. The selection of the boot device and the configuration of the interface required are accomplished with the help of the eFUSEs and/or the corresponding GPIO input pins.

Boot Device Selection and Configuration

In normal operation (boot mode 0, or 2), the boot ROM uses the state of BOOT_MODE and eFUSEs to determine the boot device.

During development, it is advisable to set the boot type to “Internal boot” (BOOT_MODE[1:0]=104 so that choosing and configuring the boot device using GPIO pin inputs is available. The input pins are sampled at boot and, if the BT_FUSE_SEL fuse is not blown, override the values of the corresponding eFUSEs BOOT_CFGx[7:0]. The table phyCORE-Connector Boot Configuration Pins lists the eFUSEs BOOT_CFGx[7:0] and the corresponding input pins. On the phyCORE‑i.MX 8M, the GPIOs have 10 kΩ pull-up and pull-down resistors preinstalled to configure eFUSEs BOOT_CFGx[7:0] in accordance with the module features.

The specific boot configuration settings, which are set by the onboard configuration resistors, can be changed by modifying the resistors on the module or by connecting a configuration resistor (e.g. 10 kΩ) to the configuration signal. Please consider that any change of the default BCFG configuration can also influence other boot modes, which might result in faulty boot behavior.

Warning

Make sure that the signals shown in phyCORE-Connector Boot Configuration Pins are not driven by any device on the baseboard during reset. This is to avoid accidental change of the boot configuration.


Boot SourceAddressBOOT_CFG[15]BOOT_CFG[14]BOOT_CFG[13]BOOT_CFG[12]BOOT_CFG[11]BOOT_CFG[10]BOOT_CFG[9]BOOT_CFG[8]
Pin#



















0x470[15:8]






X31C50X31C51X31C52X31C53X31C54X31C55X31C56X31C57
SignalX_SAI1_TXD7

X_SAI1_TXD6

X_SAI1_TXD5X_SAI1_TXD4X_SAI1_TXD3X_SAI1_TXD2X_SAI1_TXD1X_SAI1_TXD0











Infinit-Loop
(Debug USE only)
0 - Disable
1 - Enable

001 - SD/eSD

Port Select:
00 - eSDHC1
01 - eSDHC2

Power Cycle Enable

0 - No power cycle
1 - Enabled via

SD Loopback Clock
Source Sel (for SDR50 and SDR104 only)
0 - through SD pad
1 - direct

010 - MMC/eMMC



011 - NAND

Pages In Block:
00 - 128
01 - 64
10 - 32
11 - 256

Nand_Row_address_bytes
00 -3
01- 2
10 - 4
11 - 5


100 - QSPI

QSPI Instance

0 - QuadSPI0
1 - Reserved

SDR SMP:

000 : Default
001 - 111


110 - SPI NOR

Port Select:
000 - eCSPI1
001 - eCSPI2

SPI Addressing:
0 - 3-bytes (24-bit)
1 - 2-bytes (16-bit)


Others - Reserved for future use






Boot Source

Address

BOOT_CFG[7]

BOOT_CFG[6]

BOOT_CFG[5]BOOT_CFG[4]BOOT_CFG[3]BOOT_CFG[2]

BOOT_CFG[1]

BOOT_CFG[0]

Pin#



X31C60

X31C61

X31C62X31C63X31C64X31C65X31C66X31C67

Signal



X_SAI1_RXD7

X_SAI1_RXD6

X_SAI1_RXD5X_SAI1_RXD4X_SAI1_RXD3X_SAI1_RXD2X_SAI1_RXD1X_SAI1_RXD0




SD/eSD























0x470[7:0]











Fast Boot:

0 - Regular
1 - Fast Boot





Reserved





Reserved




Bus Width:

0 - 1-bit
1 - 4-bit

Speed
000 - Normal/SDR12
001 - High/SDR25
010 - SDR50
011 - SDR104
101 - Reserved for DDR50
Others - Reserved




Reserved





MMC/eMMC

Bus Width:
000 - 1bit
001 - 4bit
010 - 8bit
101 - 4bit DDR (MMC 4.4)
110 - 8bit DDR (MMC 4.4)
Else - reserved


Speed

00 - Normal
01 - High
10 - Reserved for HS200
11 - Reserved



USDHC1 IO Voltage

0 - 3.3V
1 - 1.8V



USDHC2 IO Voltage Selection

0 - 3.3V
1 - 1.8V






NAND





BT_Togglemode



BOOT_SEARCH_COUNT:

00 - 2
01 - 2
10 - 4
11 - 8

Toogle Mode 33Mhz Preabmble Delay, Read Latency:

000 - 16 GPMICLK cycles.
001 - 1 GPMICLK cycles.
010 - 2 GPMICLK cycles.
011 - 3 GPMICLK cycles.
100 - 4 GPMICLK cycles.
101 - 5 GPMICLK cycles.
110 - 6 GPMICLK cycles.
111 - 7 GPMICLK cycles.





Reserved




QSPI

HSPHS: Half Speed Phase Selection

0: select sampling at non-inverted clock
1: select sampling at inverted clock

HSDLY: Half Speed Delay selection

0: one clock delay
1: two clock delay

FSPHS: Full Speed Phase Selection

0: select sampling at non-inverted clock
1: select sampling at inverted clock

FSDLY: Full Speed Delay selection

0: one clock delay
1: two clock delay




Reserved



Reserved



Reserved



Reserved




SPINOR

CS select (SPI only):

00 - CS#0 (default)
01 - CS#1
10 - CS#2
11 - CS#3



Reserved


Reserved


Reserved


Reserved


Reserved


Reserved


Reserved

phyCORE-Connector Boot Configuration Pins

System Memory

The phyCORE‑i.MX 8M provides three types of onboard memory:

  • One bank LPDDR4 RAM: 512 MB LPDDR4 RAM (up to 4 GB)
  • eMMC 4 GB (up to 128 GB)
  • QSPI NOR Flash (up to 64MB)
  • I²C-EEPROM: 4 kB

Details for each memory type used on the phyCORE‑i.MX 8M are below.

LPDDR4-RAM (U3)

The RAM memory interface of the phyCORE‑i.MX 8M supports one 32-bit LPDDR4-RAM chip (U3). The LPDDR4 memory is accessible starting at address 0x4000 0000 and 1 0000 0000.

Typically, the LPDDR4-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 8M controller. Refer to the i.MX 8M Reference Manual to access and configure these registers.

eMMC Flash Memory (U4)

The main flash memory of the i.MX 8M is eMMC and is populated at U4. The eMMC device is programmable with 1.8 V. No dedicated programming voltage is required. The eMMC Flash memory is connected to the SD1 interface of the i.MX 8M.

For more information about the eMMC Flash , please refer to the i.MX 8M Reference Manual.

I2C EEPROM (U6)

The phyCORE‑i.MX 8M is populated with a non-volatile 4 kB I2C EEPROM at U6. This memory can be used to store configuration data or other general purpose data. This device is accessed through I2C port 1 on the i.MX 8M. The control registers for I2C port 1 are mapped between addresses 0x30A2 0000 and 0x30A3 0000. Please see the i.MX 8M Reference Manual for detailed information on the registers.

The three lower address bits are fixed to zero which means that the EEPROM can be accessed at I2C address 0x52. The EEPROM has a second address on 0x5A, which is called Identification Page, and is reserved for internal PHYTEC uses only.

QSPI NOR Flash (U40)

The QSPI NOR Flash memory of the phyCORE-i.MX 8M at U40 can be used to store configuration data or any other general purpose data. It can also be used as a boot device and recovery boot device. The device is accessed through QSPIA SS0 on the i.MX 8. The control registers for QSPI are mapped between addresses 0x30BB 0000 and 0x30BC 0000. Please see the i.MX 8M Reference Manual for detailed information on the registers.

As of the printing of this manual, these SPI Flash devices generally have a life expectancy of at least 100,000+ erase/program cycles and a data retention rate of 20 years. This makes the QSPI Flash a reliable and secure solution to store the first and second level bootloaders.

Serial Interfaces

The phyCORE‑i.MX 8M provides numerous dedicated serial interfaces, some of which are equipped with a transceiver to enable direct connection to external devices:

  1. One SDIO interface (4 and 8-Bit)
  2. Four high-speed UARTs (TTL)
  3. Two USB super speed HOST interfaces
  4. One Gbit Ethernet interface
  5. Three I2C interfaces (derived from I2C port 1 of the i.MX 8M)
  6. Two Serial Peripheral Interfaces (SPI) (extended from the first and second SPI module (eCSPI1 and eCSPI2) of the i.MX 8M)
  7. SAI audio interface
  8. Two PCI Express interfaces (extended directly from the i.MX 8 PCIe PHY)
  9. Two MIPI CSI interfaces
  10. One MIPI DSI interface

Detail for each of these serial interfaces and any applicable jumper configurations are below.

SDIO Interface

The SDIO interface can be used to connect external SD cards, eMMC, or any other device requiring SDIO interface (i.e WiFI, I/O expansion, etc.) The phyCORE bus features one SDIO interface. On the phyCORE‑i.MX 8M, the interface signals extend from the second Ultra Secured Digital (SD2) Host controller to the phyCORE-Connector. 

The table below shows the location of the different interface signals on the phyCORE-Connector. The MMC/SD/SDIO Host Controller is fully compatible with the SD Memory Card Specification 3.0 The interface supports SD cards with 3.3V and 1.8V signals.

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A12

X_SD2_RESET_B

NVCC_SD2

3.3V/1.8V

I/O

SD2 Reset

A13

X_SD2_WP

NVCC_SD2

3.3V/1.8V

I/O

SD2 Write Protect

A14

X_SD2_CD_B

NVCC_SD2

3.3V/1.8V

I/O

SD2 Card Detect

A15

X_SD2_DATA1_EXT

-

3.3V/1.8V

I/O

SD2 DATA1

A16

X_SD2_DATA0_EXT

-

3.3V/1.8V

I/O

SD2 DATA0

A17

X_SD2_CLK_EXT

-

3.3V/1.8V

I/O

SD2 Clock

A18

X_SD2_CMD_EXT

-

3.3V/1.8V

I/O

SD2 Command

A19

X_SD2_DATA3_EXT

-

3.3V/1.8V

I/O

SD2 DATA3

A20

X_SD2_DATA2_EXT

-3.3V/1.8VI/OSD2 DATA2

SDIO Interface Pinout

Warning

The SD2 interface is also used for the WIFI module on the SOM. The interface is either connected to the WIFI module or the connector depending on which connection is needed at the moment. The default connection is WIFI if you are using a SOM populated with a WIFI chip. To change the direction to the phyCORE pins, pull the signal X_WIFI_SELECT on Pin A47 (X31) to ground.

Universal Asynchronous Interface

The phyCORE‑i.MX 8M provides four high speed universal asynchronous interfaces. The following table shows the location of the signals on the phyCORE-Connector.

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

C39

X_UART1_RXD

NVCC_UART

3.3V

I/O

UART1 Receive Data (Default Debug)

C40

X_UART1_TXD

NVCC_UART

3.3V

I/O

UART1 Transmit Data (Default Debug)







E3

X_UART2_RXD

NVCC_UART

3.3V

I/O

UART2 Receive Data

E4

X_UART2_TXD

NVCC_UART

3.3V

I/O

UART2 Transmit Data







C35

X_UART3_TXD

NVCC_UART

3.3V

I/O

UART3 Transmit Data

C36

X_UART3_RXD

NVCC_UART

3.3V

I/O

UART3 Receive Data







E1

X_UART4_RXD

NVCC_UART

3.3V

I/O

UART4 Receive Data

E2

X_UART4_TXD

NVCC_UART

3.3V

I/O

UART4 Transmit Data

UART Signal Locations

Warning

The signals extending from UART2 and UART4 of the i.MX 8M are only available if WIFI is not mounted.

USB Interfaces

The phyCORE‑i.MX 8M provides two super speed USB host interfaces. An external USB Standard-A (for USB host) connector is all that is needed to interface the phyCORE‑i.MX 8M USB host functionality. The applicable interface signals can be found on the phyCORE‑Connector X31. If overcurrent and power enable signals are needed for the USB host interface, the functionality can be easily implemented with GPIOs.

Both interfaces can also operate as high speed OTG interfaces. An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for USB OTG) connector is all that is needed to enable the phyCORE-i.MX 8M USB OTG functionality:

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A21

X_USB1_DP

USB_P0_VDD3

-

PHY

USB 1 Data+

A22

X_USB1_DN

USB_P0_VDD3

-

PHY

USB 1 Data-

A23

X_USB1_TX_P

USB_P0_VPH

-

PHY

USB 1 Transmit Data+

A24

X_USB1_TX_N

USB_P0_VPH

-

PHY

USB 1 Transmit Data-

A25

X_USB1_RX_P

USB_P0_VPH

-

PHY

USB 1 Receive Data+

A26

X_USB1_RX_P

USB_P0_VPH

-

PHY

USB 1 Receive Data-







C15

X_USB1_ID

USB_P0_VDD33

-

PHY

USB 1 OTG ID Pin

C16

X_USB1_VBUS

USB_P0_VDD33-PWR_INUSB 1 VBUS input

USB 1 Signal Locations

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A27

X_USB2_DP

USB_P1_VDD3

-

PHY

USB 2 Data+

A28

X_USB2_DN

USB_P1_VDD3

-

PHY

USB 2 Data-

A29

X_USB2_TX_P

USB_P1_VPH

-

PHY

USB 2 Transmit Data+

A30

X_USB2_TX_N

USB_P1_VPH

-

PHY

USB 2 Transmit Data-

A31

X_USB2_RX_P

USB_P1_VPH

-

PHY

USB 2 Receive Data+

A32

X_USB2_RX_P

USB_P1_VPH

-

PHY

USB 2 Receive Data-







C27

X_USB2_ID

USB_P1_VDD33-PHY

USB 2 OTG ID Pin

C28X_USB2_VBUSUSB_P1_VDD33-PWR_INUSB 2 VBUS input

USB 2 Signal Locations

Warning

X_USB1_VBUS and X_USB2_VBUS must be supplied with 5 V for proper USB functionality.

Ethernet Interface

Connection of the phyCORE‑i.MX 8M to the world wide web or a local area network (LAN) is possible using the onboard GbE PHY at U8. It is connected to the RGMII interface of the i.MX 8M. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. Alternatively, the RGMII (ENET) interface, which is available on the phyCORE‑Connector, can be used to connect an external PHY. In this case, the onboard GbE PHY (U8) must not be populated (RGMII Interface).

Ethernet PHY (U8)

With an Ethernet PHY mounted at U8, the phyCORE‑i.MX 8M has been designed for use in 10Base-T, 100Base-T, and 1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE‑Connector X31.

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A1

X_ETH0_LED2_ACT

--

OD

Activity

A2

X_ETH0_LED0_LINK

--

OD

Link

A3

X_ETH0_A+

--

PHY

Data A+

A4

X_ETH0_A-

--

PHY

Data A-

A5

X_ETH0_B+

--

PHY

Data B+

A6

X_ETH0_B-

--

PHY

Data B-

A7

X_ETH0_C+

--

PHY

Data C+

A8

X_ETH0_C-

--PHYData C-

A9

X_ETH0_D+

--PHYData D+

A10

X_ETH0_D-

--PHYData D-

Ethernet Signal Locations

The onboard GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface of the i.MX 8M. Please refer to the i.MX 8M Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (ETH0_A±, ETH0_B±, ETH0_C±, ETH0_D±) are integrated in the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies for the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.

Warning

Please refer to the Ethernet PHY datasheet when designing the Ethernet transformer circuitry or request the schematic of the applicable carrier board (phyBOARD‑Polaris i.MX 8M).

Software Reset of the Ethernet Controller

The Ethernet PHY at U8 can be reset by software. The reset input of the Ethernet PHY is permanently connected to RESET_ETHPHY (GPIO1_IO06) of the i.MX 8M.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 8M is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

RGMII Interface

In order to use an external Ethernet PHY instead of the onboard GbE PHY at U8, the RGMII interface (ENET) of the i.MX 8M needs to be brought out at phyCORE‑Connector X31.

Warning

The GbE PHY (U8) must not be populated on the module if the RMII interface is used.

Tip

It is possible to change the IO voltage level of the RGMII and MDIO signals. The default setting for jumper J27 sets the IO Voltage to 1.8V. Setting jumper J27 to 2+3 changes the RGMII IO Voltage to 3.3V. See Jumper Settings.

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

E21

X_ENET0_RGMII_RXD2

-

1.8V(*3.3V)

I

Receive Data 2

E22

X_ENET0_RGMII_RXD3

-

1.8V(*3.3V)

I

Receive Data 3

E23

X_ENET0_RGMII_RXD0

-

1.8V(*3.3V)

I

Receive Data 0

E24

X_ENET0_RGMII_RXD1

-

1.8V(*3.3V)

I

Receive Data 1

E25

X_ENET0_RGMII_RX_CTL

-

1.8V(*3.3V)

I

Receive Control

E26

X_ENET0_RGMII_RXC

-

1.8V(*3.3V)

I

Receive Clock

E27

X_ENET0_RGMII_TXD2

-

1.8V(*3.3V)

O

Transmit Data 2

E28

X_ENET0_RGMII_TXD3

-1.8V(*3.3V)OTransimt Data 3

E29

X_ENET0_RGMII_TXD0

-1.8V(*3.3V)OTransmit Data 0

E30

X_ENET0_RGMII_TXD1

-1.8V(*3.3V)OTransmit Data 1

E31

X_ENET0_RGMII_TX_CTL

-1.8V(*3.3V)OTransmit Control

E32

X_ENET0_RGMII_TXC

-1.8V(*3.3V)OTransmit Clock

E33

X_ENET0_MDC

NVCC_ENET1.8V(*3.3V)OManagment Clock

E34

X_ENET0_MDIO

NVCC_ENET1.8V(*3.3V)I/OManagment Data

GMII Interface Signal Locations

SPI Interface

The Serial Peripheral Interface (SPI) is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI on the phyCORE‑Connector X31. The SPI provide one chip select signals for each interface. The Enhanced Configurable SPI (eCSPI) of the i.MX 8M has three separate modules (eCSPI1, eCSPI2, eCSPI3) which support data rates of up to 52 Mbit/s. The interface signals of the first and second module (eCSPI1, eCSPI2) are made available on the phyCORE-Connector. These modules are master/slave configurable. The following table lists the SPI signals on the phyCORE-Connector.

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

C71

X_ECSPI1_MOSI

NVCC_ECSPI

3.3V

I/O

eCSPI1 Master Out

C72

X_ECSPI1_MISO

NVCC_ECSPI

3.3V

I/O

eCSPI1 Master In

C73

X_ECSPI1_SS0

NVCC_ECSPI

3.3V

O

eCSPI1 Chip Select

C74

X_ECSPI1_SCLK

NVCC_ECSPI

3.3V

O

eCSPI1 Clock







C75

X_ECSPI2_MOSI

NVCC_ECSPI

3.3V

I/O

eCSPI2 Master Out

C76

X_ECSPI2_MISO

NVCC_ECSPI

3.3V

I/O

eCSPI2 Master In

C77

X_ECSPI2_SS0

NVCC_ECSPI3.3VOeCSPI2 Chip Select

C78

X_ECSPI2_SCLK

NVCC_ECSPI3.3VOeCSPI2 Clock

SPI Interface Signal Locations

I2C Interface

The Inter-Integrated Circuit (I2C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 8M contains four identical and independent multimaster fast-mode I2C modules. The interface of 3 modules is available on the phyCORE-Connector. I2C1 is reserved for controlling on the SOM. 

Tip

To ensure the proper functioning of the I2C interface, external pull resistors matching the load at the interface must be connected. There are no pull-up resistors mounted on the module. For detailed information on the voltage levels for the pull up resistors, please refer to the i.MX 8M Mini datasheet.

The following table lists the I2C ports on the phyCORE-Connector:

Processor Pin

SOM Signal Name

SOM Voltage Domain

Signal Type

Signal Level

Description

G7

X_I2C2_SCL

-

O

3.3V

I2C2 Clock

G8

X_I2C3_SCL

-

O

3.3V

I2C3 Clock







E8

X_I2C3_SDA

-

I/O

3.3V

I2C3 Data







F7

X_I2C2_SDA

-

I/O

3.3V

I2C2 Data

F8

X_I2C4_SCL

-

O

3.3V

I2C4 Clock

F9

X_I2C4_SDA

-I/O3.3VI2C4 Data

I2C Interface Signal Locations

Audio Interface

 The i.MX8M supports multiple audio interfaces as listed below:

InterfaceRX Data LineTX Data Line
SAI-188
SAI-211
SAI-311
SAI-540
SPDIF-110

phyCORE-i.MX 8M Audio Interfaces

I2S Audio Interface (SAI)

The phyCORE-i.MX 8M features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-Connector X31. SAI1 provides 8-bit transmit and 8-bit receive functionality with receive, transmit, and master clock output. Frame synchronization is available for receive and transmit operations. The tables below show the signal locations for each SAI and SPDIF interfaces.

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal level

Signal Type

Description

C50

X_SAI1_TXD7/BOOT_CFG15

NVCC_SAI13.3VI/OSAI1 TXD7

C51

X_SAI1_TXD6/BOOT_CFG14

NVCC_SAI1

3.3V

I/O

SAI1 TXD6

C52

X_SAI1_TXD5/BOOT_CFG13

NVCC_SAI1

3.3V

I/O

SAI1 TXD5

C53

X_SAI1_TXD4/BOOT_CFG12

NVCC_SAI1

3.3V

I/O

SAI1 TXD4

C54

X_SAI1_TXD3/BOOT_CFG11

NVCC_SAI1

3.3V

I/O

SAI1 TXD3

C55

X_SAI1_TXD2/BOOT_CFG10

NVCC_SAI1

3.3V

I/O

SAI1 TXD2

C56

X_SAI1_TXD1/BOOT_CFG9

NVCC_SAI13.3V

I/O

SAI1 TXD1

C57

X_SAI1_TXD0/BOOT_CFG8

NVCC_SAI1

3.3V

I/O

SAI1 TXD0

C58X_SAI1_TXCNVCC_SAI13.3VI/OSAI1 TXC
C59X_SAI1_TXFSNVCC_SAI13.3VI/OSAI1 TXFS
C60X_SAI1_RXD7/BOOT_CFG7NVCC_SAI13.3VI/OSAI1 RXD7
C61X_SAI1_RXD6/BOOT_CFG6NVCC_SAI13.3VI/OSAI1 RXD6
C62X_SAI1_RXD5/BOOT_CFG5NVCC_SAI13.3VI/OSAI1 RXD5
C63X_SAI1_RXD4/BOOT_CFG4NVCC_SAI13.3VI/OSAI1 RXD4
C64X_SAI1_RXD3/BOOT_CFG3NVCC_SAI13.3VI/OSAI1 RXD3
C65X_SAI1_RXD2/BOOT_CFG2NVCC_SAI13.3VI/OSAI1 RXD2
C66X_SAI1_RXD1/BOOT_CFG1NVCC_SAI13.3VI/OSAI1 RXD1
C67X_SAI1_RXD0/BOOT_CFG0NVCC_SAI13.3V

I/O

SAI1 RXD0
C68X_SAI1_RXCNVCC_SAI13.3VI/OSAI1 RXC
C69X_SAI1_RXFSNVCC_SAI13.3VI/OSAI1 RXFS

SAI1 Interface Signal Locations

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

C20

X_SAI2_RXC

NVCC_SAI2

3.3V

I/O

SAI2 RXC

C21

X_SAI2_RXFS

NVCC_SAI2

3.3V

I/O

SAI2 RXFS

C22

X_SAI2_RXD0

NVCC_SAI2

3.3V

I/O

SAI2 RXD0

C23

X_SAI2_TXD0

NVCC_SAI2

3.3V

I/O

SAI2 TXD0

C24

X_SAI2_TXFS

NVCC_SAI23.3V

I/O

SAI2 TXFS

C25

X_SAI2_TXC

NVCC_SAI2

3.3V

I/O

SAI2 TXC

C26

X_SAI2_MCLK

NVCC_SAI2

3.3V

I/O

SAI2 MCLK

SAI2 Interface Signal Locations

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

C8

X_SAI3_RXC

NVCC_SAI3

3.3V

I/O

SAI3 RXC

C9

X_SAI3_RXFS

NVCC_SAI3

3.3V

I/O

SAI3 RXFS

C10

X_SAI3_RXD0

NVCC_SAI3

3.3V

I/O

SAI3 RXD0

C11

X_SAI3_TXD0

NVCC_SAI3

3.3V

I/O

SAI3 TXD0

C12

X_SAI3_TXFS

NVCC_SAI33.3V

I/O

SAI3 TXFS

C13

X_SAI3_TXC

NVCC_SAI3

3.3V

I/O

SAI3 TXC

C14

X_SAI3_MCLK

NVCC_SAI3

3.3V

I/O

SAI3 MCLK

SAI3 Interface Signal Locations

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

C1

X_SAI5_RXD0

NVCC_SAI5

3.3V

I/O

SAI5 RXD0

C2

X_SAI5_RXD1

NVCC_SAI53.3V

I/O

SAI5 RXD1

C3

X_SAI5_RXD2

NVCC_SAI5

3.3V

I/O

SAI5 RXD2

C4

X_SAI5_RXD3

NVCC_SAI5

3.3V

I/O

SAI5 RXD3

C5

X_SAI5_RXC

NVCC_SAI5

3.3V

I/O

SAI5 RXC

C6

X_SAI5_MCLK

NVCC_SAI5

3.3V

I/O

SAI5 MCLK

C7

X_SAI5_RXFS

NVCC_SAI5

3.3V

I/O

SAI5 RXFS

SAI5 Interface Signal Locations

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

C102

X_SPDIF_EXT_CLK

NVCC_SAI3

3.3V

I/O

SPDIF Ext. CLK

C103

X_SPDIF_TX

NVCC_SAI3

3.3V

I/O

SPDIF TX

C104

X_SPDIF_RX

NVCC_SAI33.3V

I/O

SPDIF RX

SPDIF Interface Signal Locations

PCI Express Interface

The two 1-lane PCI Express interfaces of the phyCORE‑i.MX 8M provide PCIe Gen. 2.0 functionality which supports 5 Gbit/s operation. Furthermore, the interfaces are fully backwards compatible with the 2.5 Gbit/s Gen. 1.1 specification. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented with GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Polaris) for a circuit example.

The position of the PCIe signals on the phyCORE‑Connector X31 are shown below:

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A107

X_PCIE1_TXN_N

PCIE0_VPH

-

PHY

PCIe1 TXN-

A108

X_PCIE1_TXN_P

PCIE0_VPH

-

PHY

PCIe1 TXN+

A109

X_PCIE1_RXN_N

PCIE0_VPH

-

PHY

PCIe1 RXN-

A110

X_PCIE1_RXN_P

PCIE0_VPH

-

PHY

PCIe1 RXN+

A111

X_PCIE1_REF_PAD_CLK_N

PCIE0_VPH

-

PHY

PCIe1 Ref CLK-

A112

X_PCIE1_REF_PAD_CLK_P

PCIE0_VPH

-

PHY

PCIe1 Ref CLK+

A113

X_PCIE2_TXN_N

PCIE1_VPH

-

PHY

PCIe2 TXN-

A114

X_PCIE2_TXN_P

PCIE1_VPH-PHYPCIe2 TXN+

A115

X_PCIE2_RXN_N

PCIE1_VPH-PHYPCIe2 RXN-

A116

X_PCIE2_RXN_P

PCIE1_VPH-PHYPCIe2 RXN+

A117

X_PCIE2_REF_PAD_CLK_N

PCIE1_VPH

-

PHYPCIe2 Ref CLK-

A118

X_PCIE2_REF_PAD_CLK_P

PCIE1_VPH-PHYPCIe2 Ref CLK+

PCIe Interface Signal Locations

General Purpose I/Os

All pins not used by any of the other interfaces specifically described in this manual and can be used as GPIO without harming other features of the phyCORE‑i.MX 8M. These pins are shown below:

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

C17X_GPIO1_12NVCC_GPI013.3VI/OGPIO1 12
C18X_GPIO1_13NVCC_GPI013.3VI/OGPIO1 13
C19X_GPIO1_IO05-

3.3V

I/O

GPIO1 05 (only available if RTC_IN is not used)

C29X_GPIO1_14NVCC_GPI013.3VI/OGPIO1_14 (only available if PMIC_nSDWN is not needed)
C41X_GPIO1_IO08NVCC_GPI01

3.3V

I/O

GPIO1_08 (only available if WIFI is not mounted or function is not needed)

C42X_GPIO1_IO09NVCC_GPI01

3.3V

I/O

GPIO1_09 (only available if WIFI is not mounted or function is not needed)

C43X_GPIO1_10NVCC_GPI01

3.3V

I/O

GPIO1_10 (only available if WIFI is not mounted or funciton is not needed)

C44X_GPIO1_11NVCC_GPI013.3VI/OGPIO1_11 (only available if WIFI is not mounted or function is not needed)
C45X_GPIO1_IO07NVCC_GPI01

3.3V

I/O

GPIO1_07 (only available if ETH0_INT is not used)

C46X_GPIO1_IO06NVCC_GPI01

3.3V

I/O

GPIO1_06 (only available if RESET_ETHPHY is not used)

C79X_GPIO1_IO01NVCC_GPI01

3.3V

I/O

GPIO1 01

GPIO Pin Locations

Beside these pins, most of the i.MX 8M signals which are connected directly to the module connector can be configured to act as GPIOs, due to the multiplexing functionality of most controller pins. Normally, pins with signal type I/O are able to work as a GPIO.

Debug Interface

The phyCORE‑i.MX 8M is equipped with a JTAG interface to download program code into the external flash, internal controller RAM, or any debugging programs being executed. The location of the JTAG pins on the phyCORE-Connector X31 are below:

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A79

X_JTAG_TCK

NVCC_JTAG

3.3V

I/O

JTAG TCK

A80

X_JTAG_TMS

NVCC_JTAG

3.3V

I/O

JTAG TMS

A81

X_JTAG_TDI

NVCC_JTAG

3.3V

I/O

JTAG TDI

A82

X_JTAG_TDO

NVCC_JTAG

3.3V

I/O

JTAG TDO

A83

X_JTAG_TRST_B

NVCC_JTAG

3.3V

I/O

JTAG TRST

A84

X_JTAG_MOD

NVCC_JTAG

3.3V

I/O

JTAG MOD

Debug Interface Signal Locations

UART Debug

The default debug UART Interface (TTL) is UART1. It is accessable on connector X31 pin C39(RXD) and pin C40(TXD).

Display Interfaces

High Definition Multimedia Interface (HDMI)

The High Definition Multimedia Interface (HDMI) of the phyCORE-i.MX 8M is compliant with HDMI 2.0a as well as DP 1.3 and eDP 1.4. It supports a maximum pixel clock up to 596 MHz for up to 2160p at 60 Hz UHDTV display resolutions and a graphic display resolution works up to 4096x2160 (QFHD). Please refer to the i.MX 8M Reference Manual for more information.

The location of the HDMI signals on the phyCORE-Connector are shown below:

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A33

X_HDMI_AUX_N

HDMI_AVDDIO

-

PHY

HDMI AUX-

A34

X_HDMI_AUX_P

HDMI_AVDDIO

-

PHY

HDMI AUX+

A35

X_HDMI_TX_M_LN_3

HDMI_AVDDIO

-

PHY

HDMI TX3-

A36

X_HDMI_TX_P_LN_3

HDMI_AVDDIO

-

PHY

HDMI TX3+

A37

X_HDMI_TX_M_LN_0

HDMI_AVDDIO

-

PHY

HDMI TX0-

A38

X_HDMI_TX_P_LN_0

HDMI_AVDDIO

-

PHY

HDMI TX0+

A39

X_HDMI_TX_M_LN_1

HDMI_AVDDIO

-

PHY

HDMI TX1-

A40

X_HDMI_TX_P_LN_1

HDMI_AVDDIO-PHYHDMI TX1+

A41

X_HDMI_TX_M_LN_2

HDMI_AVDDIO-PHYHDMI TX2-

A42

X_HDMI_TX_P_LN_2

HDMI_AVDDIO-PHYHDMI TX2+

 HDMI Interface Signal Locations

The default HDMI setup comes from the SOM. As the signals extend directly from the i.MX 8M’s dual-purpose PHY for HDMI and eDP, a standard HDMI connector (ususally a 5 V level shifter) for the DDC and the CEC signals is not needed. An optional ESD circuit protection device is all that is needed to interface the phyCORE-i.XM 8M’s HDMI functionality.

Camera Connections

The phyCORE-i.MX 8M offers 2 MIPI-CSI interfaces to connect digital cameras with a resolution of up to 4k at 30fps. The two MIPI/CSI‑2 camera interfaces of the i.MX 8M extend to the phyCORE‑Connector X31 with 4 data lanes and one clock lane. The locations of the MIPI-CSI signals are shown below:

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A69

X_MIPI_CSI2_D0_P

CSI_P2_VDDHA

-

PHY

CSI2 DATA0+

A70

X_MIPI_CSI2_D0_N

CSI_P2_VDDHA

-

PHY

CSI2 DATA0-

A71

X_MIPI_CSI2_D1_P

CSI_P2_VDDHA

-

PHY

CSI2 DATA1+

A72

X_MIPI_CSI2_D1_N

CSI_P2_VDDHA

-

PHY

CSI2 DATA1-

A73

X_MIPI_CSI2_CLK_P

CSI_P2_VDDHA

-

PHY

CSI2 Clock+

A73

X_MIPI_CSI2_CLK_N

CSI_P2_VDDHA

-

PHY

CSI2 Clock-

A75

X_MIPI_CSI2_D2_P

CSI_P2_VDDHA

-

PHY

CSI2 DATA2 +

A76

X_MIPI_CSI2_D2_N

CSI_P2_VDDHA-PHYCSI2 DATA2-

A77

X_MIPI_CSI2_D3_P

CSI_P2_VDDHA-PHYCSI2 DATA3+

A78

X_MIPI_CSI2_D3_N

CSI_P2_VDDHA-PHYCSI2 DATA3-






A97

X_MIPI_CSI1_D0_P

CSI_P1_VDDHA-PHYCSI1 DATA0+

A98

X_MIPI_CSI1_D0_N

CSI_P1_VDDHA-PHYCSI1 DATA0-

A99

X_MIPI_CSI1_D1_P

CSI_P1_VDDHA-PHYCSI1 DATA1+

A100

X_MIPI_CSI1_D1_N

CSI_P1_VDDHA-PHYCSI1 DATA1-

A101

X_MIPI_CSI1_CLK_P

CSI_P1_VDDHA-PHYCSI1 Clock+

A102

X_MIPI_CSI1_CLK_N

CSI_P1_VDDHA-PHYCSI1 Clock-

A103

X_MIPI_CSI1_D2_P

CSI_P1_VDDHA-PHYCSI1 DATA2+

A104

X_MIPI_CSI1_D2_N

CSI_P1_VDDHA-PHYCSI1DATA2-

A105

X_MIPI_CSI1_D3_P

CSI_P1_VDDHA-PHYCSI1 DATA3+

A106

X_MIPI_CSI1_D3_N

CSI_P1_VDDHA-PHYCSI1 DATA3-

Camera Interface MIPI / CSI-2 Signal Locations

The phyCORE-i.MX 8M offers one MIPI-DSI display interface. MIPI-DSI has 4 channels, supporting one display with a resolution of up to 1920 x 1080 at 60Hz. The locations of the MIPI-DSI signals are shown below:

SOM Connector Pin / phyBOARD-Polaris Carrier Board Connector Pin

SOM Signal Name

SOM Voltage DomainSignal Level

Signal Type

Description

A129

X_MIPI_DSI_D0_P

DSI_VDDHA

-

PHY

DSI DATA0+

A130

X_MIPI_DSI_D0_N

DSI_VDDHA

-

PHY

DSI DATA0-

A125

X_MIPI_DSI_D1_P

DSI_VDDHA

-

PHY

DSI DATA1+

A126

X_MIPI_DSI_D1_N

DSI_VDDHA

-

PHY

DSI DATA1-

A127

X_MIPI_DSI_CLK_P

DSI_VDDHA

-

PHY

DSI Clock+

A128

X_MIPI_DSI_CLK_N

DSI_VDDHA

-

PHY

DSI Clock-

A123

X_MIPI_DSI_D2_P

DSI_VDDHA

-

PHY

DSI DATA2 +

A124

X_MIPI_DSI_D2_N

DSI_VDDHA-PHYDSI DATA2-

A131

X_MIPI_DSI_D3_P

DSI_VDDHA-PHYDSI DATA3+

A132

X_MIPI_DSI_D3_N

DSI_VDDHA-PHYDSI DATA3-

Display Interface MIPI / DSI Signal Locations

WIFI/Bluetooth

WIFI

The i.MX8M is the first SOM in the PHYTEC phyCORE family with onboard Wifi/Bluetooth support. This feature is made possible with an Sterling-LWB module soldered onto the SOM. This module supports Wifi according to IEEE 802.11 b/g/n and Bluetooth v4.2 BR /DR/LE.

Wifi is controlled over the SD2 interface. It is also possible to use this interface on the carrier board. To achieve this, an SDIO switch has been added on the SOM.  This changes the signal depending on whether the signal is connected to WIFI or BGA Ball. There are two signals which are controlled by the SDIO switch.

  1.  X_GPIO1_IO03/WIFI_SELECT is connected to the Enable Pin of the SDIO Switch. This is an low active signal and, as the name indicates, is controlled by GPIO1_03 (from the processor). This signal is also connected to the BGA ball connector and can be controlled from the carrier board. This signal is connected to a pull-up. By default, the switch is disabled.
  2. X_WIFI_SELECT. This signal is only connected to the carrier board and determines if the SD2 interface is connected to WIFI or to the BGA balls. By default, SD2 is connected to WIFI. If you want to connect SD2 to the BGA balls, it is necessary to pull X_WIFI_SELECT to GND.
X_WIFI_SELECTConnection
HighSD2 → WIFI
LowSD2 → Connector X31

X_WIFI_SELECT Signal Options

Bluetooth

Bluetooth is controlled over UART2. The handshake signals that are needed, RTS and CTS, come out on the UART4 TX and RX pins (if you order a SOM without mounted a WIFI Module) These pins are connected via jumpers to the phyCORE-Connector X31.

There are a few other control signals on the WIFI Module. They can be controlled using various jumper settings. By default, all signals are controlled by GPIOs from the i.MX 8M processor. It is also possible to connect each signal to the BGA connector, allowing them to be controlled with the carrier board.

The following tables show the possible jumpers settings:

J5WLAN_ENX_GPIO1_IO10
GPIO1_IO101+21+4
X_WLAN_EN2+3

J5 Settings Options

J6BT_ENX_GPIO1_IO11
GPIO1_IO111+2
1+4
X_BT_EN2+3

J6 Settings Options

J7WIFI_HCI_UART/WAKEHOST_LX_GPIO1_IO08
GPIO1_IO081+2
1+4
X_WIFI_HCI_UART/WAKEHOST_L2+3

J7 Settings Options

J8WIFI_WLAN_RF_KILL_LX_GPIO1_IO09
GPIO1_IO091+2
1+4
X_WIFI_WLAN_RF_KILL_L2+3

J8 Settings Options

RTC

The i.MX 8M has an onboard, externally mounted RTC. The RV-3028 is the newest generation of RTC from Micro Crystal with an extremely low backup current of only 40nA. PHYTEC uses the most optimal implementation in each phyCORE design to give the most optimal usage for all customers.

The RTC is accessable over I2C1 on Address 0x52. In a normal operation state, the RTC power is supplied from the SOM voltage. If the SOM is not powered and RTC backup is needed, the VBACKUP Pin of the RTC can be supplied over the VRTC BGA ball.  The clockout of the RTC is used for the WIFI Module and must to be set to 32.768kHz.

Additional features like event input  X_RTC_EVI (X31E35) are also accessable as a RTC interrupt option. This option is, by default, connected to GPIO1_IO05 of the i.MX 8M processor but can be changed to a BGA ball connection by changing the settings on jumper J34. The settings are shown below:

J34RTC_INTX_GPIO1_IO05
GPIO1_IO051+2 (Default)
1+4
X_RTC_IN2+3

J34 Settings Options

CPU Core Frequency Scaling

The phyCORE-i.MX 8M on the phyBOARD‑Polaris is able to scale the clock frequency and voltage. This is used to save power when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as 'Dynamic Voltage and Frequency Scaling' (DVFS).

The phyCORE-i.MX 8M BSP supports the DVFS feature. The Linux kernel provides a DVFS framework that allows each CPU core to have a min/max frequency as well as the applicable voltage and a governor that governs these values depending on the system load. Depending on the i.MX 8M variant used, several different frequencies are supported. Further details on how to configure this governor can be found in the phyCORE-i.MX 8M BSP Manual.

Technical Specifications

Warning

Due to changes in functionality and design that are currently being developed, there are several values that cannot be determined in time for the release of this manual. All values with "TBD (To Be Determined)" are currently being evaluated. These values will be added in future manual editions.

The module’s profile is max. 10 mm thick, with a maximum component height of 3.0 mm on the bottom (connector) side of the PCB and approximately 5.0 mm on the top (microcontroller) side. The board itself is approximately 1.4 mm thick. The phyCORE-i.MX 8M Footprint can be seen below.

phyCORE-i.MX 8M Footprint

phyCORE-i.MX 8M Footprint

Tip

Additional specifications:

Dimensions:55 x 40mm
Weight:TBD
Storage Temperature:TBD
Operating Temperature:TBD
Humidity:TBD
Operating Voltage:3.3V
Power Consumption:TBD

Technical Specifications

These specifications describe the standard configuration of the phyCORE‑i.MX 8M as of the printing of this manual.

phyCORE-i.MX 8M Power Consumption

The values listed in the table below are a guideline to determine the required dimensions of the power supply circuitry on a carrier board. They do not take application-specific load situations into account. These values have been generated by looking at the maximum power consumption measured using different load scenarios and adding a voltage source of 3.3 V ±5 %. These values are based on internal PHYTEC testing. Customers need to consider their application power requirements to ensure they do not generate a load greater then the values listed here. 

Maximum Power RequirementsTBD
Required Supply VoltageTBD
Ramp-Up TimeTBD
Allowed Tolerance of Supply VoltageTBD

phyCORE-i.MX 8M MINI Power Consumption

Additionally, there are some values that cannot be tested. Situations such as suspending to RAM, suspend freeze, and standby mode must be tested on a case by case basis to ensure the application's power consumption stays within the guideline stated above.

Tip

For further information and assistance regarding your application's power consumption, please contact PHYTEC sales.

Product Temperature Grades

Warning

The right temperature grade for the module greatly depends on the use case. It is necessary to determine if the use case suits the temperature range of the chosen module (see below). A heat spreader can be used if temperature compensation is required.

The feasible operating temperature of the SOM highly depends on the use case of your software application. Modern high performance microcontrollers and other active parts as the ones described within this manual are usually rated by qualifications based on tolerable junction or case temperatures. Therefore, making a general statement about minimum or maximum ambient temperature ratings for the described SOM is not possible.

However, the above mentioned parts are available in different temperature qualification levels by the producers. We offer our SOM's in different configurations, making use of those temperature qualifications. To indicate which level of temperature qualification is used for active and passive parts of a SOM configuration, we have categorized our SOMs into three temperature grades.

The table Product Temperature Grades describes these grades in detail. This table describe a set of components which, in combination, add up to a useful set of product options with different temperature grades. This enables us to make use of cost optimizations depending on the required temperature range.

In order to determine the right temperature grade and whether the minimum or maximum qualification levels are met within an application, the following conditions must be defined by considering the use case:

  • Determined processing load for the given software use case
  • Maximum temperature ranges of components (Product Temperature Grades)
  • Power consumption resulting from a base load and the calculating power required (in consideration of peak loads as well as time periods for system cool down)
  • Surrounding temperatures and existing airflow in case the system is mounted into a housing
  • Heat resistance of the heat dissipation paths within the system along with the considered usage of a heat spreader or a heat sink to optimize heat dissipation

Product Temperature
Grade

Controller  Range
(Junction Temperature)

RAM
(Case Temperature)
Other
(Ambient)

I

Industrial: -40°C to +105°C 
Automotive: -40°C to+125°C

Industrial: -40°C to +95°C

Industrial: -40°C to +85°C

X

Extended Commercial:  -20 °C to +105°C

Industrial: -40°C to +95°C

Industrial: -40°C to +85°C

C

Commercial: 0°C to +95°C

Consumer: 0°C to +95°C

Consumer: 0°C to +70°C

Product Temperature Grades

phyCORE-i.MX 8M BGA Mounting

The phyCORE i.MX 8M uses of Ball Grid Array (BGA) to mount to a carrier board (for example, phyBOARD-Polaris). BGA provides several advantages:

  • An easy to produce design
  • Permanent and robust mechanical connection to the carriar application
  • Relaxed fit in regards to on board circuitry
  • Easy to design in any application
  • Low profile
  • Cost efficient

For more information about BGA soldering, please refer to the PHYTEC BGA Soldering Guide (LAN-093e.A0 i.MX 8 BGA Soldering Information).

Hints for Integrating and Handling the phyCORE‑i.MX 8M

Intergrating the phyCORE-i.MX 8M

Besides this hardware manual, more information is available to facilitate the integration of the phyCORE‑i.MX 8M into customer applications.

  1. The design of the phyBOARD‑Polaris can be used as a reference for any customer application.
  2. Many answers to common questions can be found at: https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-download/ or https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-download/
  3. The link “Carrier Board” within the category Dimensional Drawing leads to the layout data phyCORE-i.MX 8M Footprint It is available in different file formats. Use of this data allows the user to integrate the phyCORE-i.MX 8M SOM as a single component into your design.
  4. Different support packages are available for support in all stages of embedded development. Please visithttp://www.phytec.de/de/support/support-pakete.html or https://www.phytec.eu/support/support-packages/ or contact our sales team for more details.
  5. Many answers to common questions can be found at:
  6. http://www.phytec.de/support/knowledge-database/soms-system-on-modules/phycore/phycore-imx-8m/
      or
    https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-download/

Handling the phyCORE-i.MX 8M

phyCORE Module Modifications

The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board as well as surrounding components and sockets remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Warning

If any modifications to the module are performed, regardless of their nature, the manufacturer guarantee may be null and void.

Intergrating the phyCORE into a Target Application

Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. At a minimum, all GND pin neighboring signals which are being used in the application circuitry should be connected to GND.

phyCORE-i.MX 8M on the phyBOARD-Polaris

Hardware Overview

The phyBOARD‑Polaris for phyCORE-i.MX 8M is a low-cost, feature-rich software development platform supporting the NXP Semiconductors i.MX 8M microcontroller. Due to numerous standard interfaces, the phyBOARD‑Polaris i.MX 8M can serve as the bedrock for any application. At the core of the phyBOARD‑Polaris is the PCL-066/phyCORE-i.MX 8M System On Module (SOM) containing the processor, LPDDR4 RAM, eMMC Flash, power regulation, supervision, transceivers, WiFi/Bluetooth, and other core functions required to support the i.MX 8M processor. Surrounding the SOM is the PB-2419/phyBOARD‑Polaris carrier board, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals.

The PCL-066 System On Module connects to the phyBOARD‑Polaris carrier board using a Ball Grid Array (BGA). The PCL-066 SOM is directly soldered onto the phyBOARD‑Polaris using PHYTEC's Direct Solder Connect technology. This solution offers an ultra-low cost Single Board Computer for the i.MX 8M processor, while maintaining most of the advantages of the SOM concept.

phyBOARD-Polaris Concept

PHYTEC phyCORE carrier boards are fully equipped with all mechanical and electrical components necessary for a fast, secure start-up. Subsequent communication to and programming of applicable PHYTEC System on Modules (SOM) is made easy. phyCORE carrier boards are designed for evaluation, testing, and prototyping PHYTEC System on Modules in laboratory environments prior to their use in customer designed applications.

This modular development platform concept includes the following components:

  • The phyCORE-i.MX 8M Module populated with the i.MX 8M microcontroller and all applicable SOM circuitry such as LPDDR4 SDRAM, eMMC-Flash, Ethernet-PHY, and PMIC etc.
  • The phyBOARD-Polaris Carrier Board offers all essential components and connectors for start-up including: a power supply for 24 V input voltage, interface connectors such as HDMI, USB, and Ethernet, which enable the use of the SOM’s interfaces with a standard cable.

The carrier board can also serve as a reference design for developing custom target hardware in which the phyCORE SOM can be deployed. Carrier board schematics are available under a Non-Disclosure Agreement (NDA). Reuse of carrier board circuitry enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

SBCplus Concept

The SBCplus concept was developed to meet the many, small differences in customer requirements with little development effort. This greatly reduces the time-to-market. The core of the SBCplus concept is the SBC design library (a kind of construction set) that consists of a large number of function blocks (so-called "building blocks") which are continuously being refined and updated.

Recombining these function blocks allows PHYTEC to develop a customer specific SBC within a short time. We are able to deliver production-ready custom Single Board Computers within a few weeks at very low costs. The already developed SBCs, such as the phyBOARD-Polaris, each represent a combination of different customer wishes. This means all necessary interfaces are already available on the standard versions, allowing PHYTEC SBCs to be integrated in a large number of applications without modification.

For any necessary detail adjustment, extension connectors are available which enable a wide variety of functions to be added.

Tip

For further information, please contact PHYTEC sales.

phyBOARD-Polaris Features

The phyBOARD‑Polaris supports the following features :

  • Developed in accordance with PHYTEC's SBCplus concept (SBCplus Concept)
  • Populated with PHYTEC’s phyCORE-i.MX 8M SOM (via BGA mounting)
  • Pico ITX standard dimensions of 100 mm × 100 mm
  • Boot from eMMC, SD Card, or over USB with the Serial Downloader
  • Max. 1.3 GHz core clock frequency and up to four cores
  • 24 V power supply
  • 1GB RAM
  • 8GB eMMC
  • 4kB EEPROM
  • One RJ45 jack for 10/100/1000 Mbps Ethernet
  • One USB 3.0 host interface connected to a USB 3.0 4-port HUB. The 3.0 interface is brought out to an upright USB Standard-A connector. The other 3 port are connected to the Mini PCI express connector, the Audio/Video connector, and the expansion connector[3]

  • One USB OTG interface available at a USB Micro-AB connector
  • One Secure Digital / Multi Media Memory Card interface brought out to a Micro-SD connector
  • One HDMI interface brought out to a standard type-A connector
  • One MIPI-DSI brought out via an A/V Connector
  • Two MIPI-CSI-2 camera interfaces
  • One PCI interface brought out to a Mini PCI Express connector
  • RS-232 or RS-485 transceiver supporting UART3 including handshake signals with data rates of up to 1 Mbps (2×5 pin header 2.54 mm)
  • Reset button
  • ON/OFF button
  • One multicolor LED
  • SAI Audio brought out via an A/V connector
  • Digital I/O via an Expansion Connector
  • JTAG via an Evaluation Adapter connected to the Expansion Connector (X8)
  • Expansion connector for different interfaces
    • I2C
    • SPI
    • UART
    • QSPI
    • USB
    • SPDIF
  • RTC
    • Goldcap Backup supply for RTC
      3.
      There is no protective circuit for the USB interfaces brought out at the Mini PCI Express connector, expansion connector. and A/V connectors.

Block Diagram

phyBOARD-Polaris Block Diagram

phyBOARD-Polaris Block Diagram

phyBOARD-Polaris Components

Note

For easy reference, Pin 1 for each component has been highlighted.

phyBOARD-Polaris Component Placement Diagram

phyBOARD-Polaris Components (Top)

phyBOARD-Polaris Components (Bottom)

phyBOARD-Polaris Component Overview

The phyBOARD-Polaris features many different interfaces and is equipped with the components listed in the table phyBOARD-Polaris Connectors and Pin Header. For a more detailed description of each component, refer to the appropriate section listed in the table below. phyBOARD-Polaris Components (Top) and phyBOARD-Polaris Components (Bottom) highlight the location of each component for easy identification.

Connectors and Pin Header

The table below lists all available connectors on the phyBOARD‑Polaris.

Reference Designator

Description

Section

X1

Ethernet 0 connector (RJ45 with speed and link LED)

Ethernet

X2

USB On-the-Go connector (USB Micro-AB)

USB

X4

Secure Digital / Multi Media Card (Micro-slot)

Secure Digital Memory Card / MultiMedia Card

X6

PCI Express connector (Mini PCI Express)

PCIe

X8

Expansion connector (2×30 socket connector 2 mm pitch)

Expansion Connector /
UART

X9

RS-232 with RTS and CTS, or RS-485 (UART3 2×5 pin header 2.54 mm pitch)

UART

X10

Camera phyCAM-M connector (30-pole Hirose FFC-connector, 0.5 mm pitch)


Camera Connectivity

X11

Camera phyCAM-M connector (30-pole Hirose FFC-connector, 0.5 mm pitch)

X13

USB host connector (USB 3.0 Standard-A)

USB

X14

Speaker Connector


Audio Interface

X15

Line In / Line Out

X16

A/V connector #1 (2×8 dual entry connector 2 mm pitch)


Audio/Video Connectors

X18

A/V connector #2 (2×15 dual entry connector 2 mm pitch)

X30

Debug FTDI (USB Debug)

USB Debug

X31

phyCORE Connector

phyCORE Connection

X32

HDMI connector (Typ-A)

HDMI

X33

Power supply 24 V (2-pole Phoenix Contact MINI COMBICON base strip)

Power Supply

phyBOARD-Polaris Connectors and Pin Header

Warning

Ensure that all module connections do not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller User's Manual/Data Sheets. As damage from improper connections varies according to use and application, it is the user‘s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

LEDs

The phyBOARD-Polaris is populated with 2 LEDs. One to inditcate the status of the USB VBUS voltages and the power supply voltage. The other is user-programable. phyBOARD-Polaris Components (Top) and phyBOARD-Polaris Components (Bottom) show the location of the LEDs. Their functions are listed in the table below:

LED

Color

Description

Section

D11

 RGB

User programmable RGB LED

Multicolor (RGB) LED

D34

 blue

Indicates presence of VBUS Voltage from a Host at the USB Debug interface

USB Debug

 phyBOARD-Polaris LED Descriptions

Switches

The phyBOARD-Polaris is populated with two switches. The table below shows their functions:

SwitchDescriptionSection
S2RESETSystem Reset
S3ON/OFFSystem ON/OFF

phyBOARD-Polaris S2/S3 Descriptions

Additionally, S1 is a 4-port dip switch bar populated for several functions:

  • Boot Selection (see Boot Switch)
  • SD Card or WIFI Selection
  • UART3 Destination (FTDI or Expansion Connector) (see USB Debug)

Jumpers

The phyBOARD-Polaris comes pre-configured with several solder jumpers (J). The jumpers enable flexible configuration of a limited number of features for development purposes.

Warning

Due to the small footprint of the solder jumpers (J), PHYTEC does not recommend manual jumper modifications. This may also render the warranty invalid. Only the rempvable jumper (JP) is described in this section. Contact our sales team if you need jumper configurations different from the default configuration.

phyBOARD-Polaris SBC Component Detail

This section provides a more detailed look at the phyBOARD‑Polaris components. Each subsection details a particular connector/interface and associated jumpers for configuring that interface.

Tip

Where possible, we also provide useful information regarding design consideration for components. This can be used if you plan to design your own carrier board.

phyCORE Connection (X31)

phyCORE Connection (X31)

Power Supply (X33)

Warning

Do not change modules or jumper settings while the phyBOARD‑Polaris is supplied with power!

Power Supply Connector (X33)

The phyBOARD‑Polaris is available with one power supply connector, a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector (X33) suitable for a single 24 V supply voltage.

The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE mounted on the phyBOARD-Polaris, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board.

The permissible input voltage is +24 V DC if your SBC is equipped with a 2-pole Phoenix Contact MINI COMBICON base strip. A 24 V adapter with a minimum supply of 1.0 A is recommended to supply the board via the 2-pole base strip. The pin assignment for power supply connector X33:

Interface Pin #Signal

Description

1VCC_IN_24V24 V power supply
2GNDGround

X33 Pin Assignment

UART (X8 and X9)

UART Connector (X9)

The phyCORE-i.MX 8M supports up to 4 UART units. On the phyBOARD-Polaris, TTL level signals of UART1 and UART3 (the standard console) are routed to expansion connector X8 (see Expansion Connector (X8) for more information). UART4 is available at pin header connector X9 at RS-232 level, or optionally at RS-485 level. UART2 is at X18 (Audio/Video Connectors).

Tip

The Evaluation Board (PEB-EVAL-01) delivered with the kit plugs into the expansion connector and allows for the easy use of the standard console (UART2) which is required for debugging. Please find additional information on the Evaluation Board in Application Guide for phyBOARD Expansion Boards (L‑793e).

Pin header connector X9 is located next to the Ethernet connector and provides the UART4 signals of the i.MX 8M at either the RS-232 or RS-485 level. The serial interface is intended to be used with data terminal equipment (DTE) and allows for a 5-wire connection including the signals RTS and CTS for hardware flow control. The table below shows the signal mapping of the RS-232 and RS-485 level signals at connector X9:

Interface Pin #

Signal

Interface Pin #

Signal

1

NC

2

NC

3

UART4_RXD_RS232

4

UART4_RST_RS232

5

UART4_TXD_RS232

6

UART4_CTS_RS232

7

UART4_RS485_A

8

UART4_RS485_B

9

GND

10

NC

X9 (RS-232 / RS-485) Pin Assignment

UART Debug Interface

The main debug interface is UART1. The UART is connected to a UART-to-USB Converter (U66) via a Multiplexer (U61). When a USB Cable is plugged in at X30, the interface will be available at the connector. Otherwise, it is routed to the Expanison Connector (X8)

UART Design Consideration

When designing a custom carrier board, remember the TTL level is 3.3 V.

Ethernet (X1)

 

Ethernet Connector (X1)

The phyBOARD‑Polaris is equipped with an RJ45 connector supporting a 10/100/1000Base-T network connection. The LEDs for LINK (green) and SPEED (yellow) indication are integrated in the connector. The Ethernet transceiver supports Auto MDI-X, eliminating the need for a direct connect LAN or cross-over path cable. They detect the TX and RX pins of the connected device and automatically configure the PHY TX and RX pins accordingly.

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1MDCT2-Analogcenter tap transformer Pair 2
2MD2-EthernetAnalogPair 2-
3MD2+EthernetAnalogPair 2+
4MD1+EthernetAnalogPair 1+
5MD1-EthernetAnalogPair 1-
6MCDT1-Analogcenter tap transformer Pair 1
7MDCT3-Analogcenter tap transformer Pair 3
8MD3+EthernetAnalogPair 3+
9MD3-EthernetAnalogPair 3-
10MD0-EthernetAnalogPair 0-
11MD0+EthernetAnalogPair 0+
12MDCT0-Analogcenter tap transformer Pair 0
D1LED_YE_COpen Drain3.3 VCathode Yellow LED
D2LED_GR_YE_ALED Supply3.3 VAnode Yellow and Green LED
D3LED_GR_Cn.C.n.C.Cathode Green LED
D4LED_GR2_COpen Drain3.3 VCathode Green LED2
D5LED_DR2_ALED Supply3.3 VAnode Green LED2

X1 Pin Assignment

Ethernet Design Consideration

The data lanes should be routed with a differential impedance of 100 Ohm. The center taps of each pair's transformer has to be connected to GND through a 100nF capacitor. The LED pins are open drain outputs of the SOM without resistor, so they should be connected to the catodes of the LEDs through a resistor.

USB

USB Interfaces (X2 and X13)

USB Interfaces (X2 and X13)

The phyBOARD-Polaris provides one USB host and one USB OTG interface. USB1 is accessible at connector X2 (USB Micro-AB) and is configured as USB OTG. USB OTG devices are capable of initiating a session, controlling the connection, and exchanging host and peripheral roles between each other. This interface is compliant with USB revision 2.0. USB2 is accessible at connector X13(USB3.0 Standard-A) and is configured as USB host.

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1USB_OTG1_VBUSUSB VBUS+5VVBUS Voltage of USB OTG Port
2X_USB1_DNUSBAnalogUSB 2.0 Negative Lane
3X_USB1_DPUSBAnalogUSB 2.0 Positive Lane
4X_USB1_IDUSBAnalogID Pin of USB OTG Port
5GND--Ground
6SHIELD1--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
7SHIELD2--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
8SHIELD3--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
9SHIELD4--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
10SHIELD5--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
11SHIELD6--Shield connected to Ground over 2,2 nF parallel to 1 MOhm

X2 Pin Assignment

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1USB_OTG2_VBUSPower+5VVBUS Voltage of USB Port
2USB_HUB_DN1_D-USBAnalogUSB High Speed Data negative
3USB_HUB_DN1_D+USBAnalogUSB High Speed Data positive
4GND--Ground
5USB_HUB_DN1_SSRX-_CONUSBAnalogUSB Super Speed Receive Data negative
6USB_HUB_DN1_SSRX+_CONUSBAnalogUSB Super Speed Receive Data positive
7GND--Ground
8USB_HUB_DN1_SSTX-_COMUSBAnalogUSB Super Speed Transmit Data negative
9USB_HUB_DN1_SSTX+_COMUSBAnalogUSB Super Speed Transmit Data positive
10SHIELD1--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
11SHIELD2--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
12SHIELD3--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
13SHIELD4--Shield connected to Ground over 2,2 nF parallel to 1 MOhm

X13 Pin Assignment

USB Debug (X30)

USB Debug with LED (X30 / D34)

The phyBOARD-Polaris is equipped with a USB Debug interface for downloading program code into the external flash, internal controller RAM, or for debugging porgrams currently executing.

The table below show the pinout of the USB Debug connector:

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1VBUS_DEBUG_USBUSB VBUS+5VVBUS Voltage of Debug USB Port
2DEBUG_USB_DMUSBAnalogUSB 2.0 Negative Lane
3DEBUG_USB_DPUSBAnalogUSB 2.0 Positive Lane
4DEBUG_USB_IDUSBAnalogID Pin of USB Port
5GND--Ground
6SHIELD1--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
7SHIELD2--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
8SHIELD3--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
9SHIELD4--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
10SHIELD5--Shield connected to Ground over 2,2 nF parallel to 1 MOhm
11SHIELD6--Shield connected to Ground over 2,2 nF parallel to 1 MOhm

 X30 Pin Assignment

USB Design Consideration

The data lanes should be routed with a differential impedance of 90 Ohm.

Secure Digital Memory Card / MultiMedia Card (X4)

SD / MM Card Interface (X4)

The phyBOARD‑Polaris provides a standard microSDHC card slot at X4 for use with SD/MMC interface cards. It allows for a fast, easy connection to peripheral devices like SD and MMC cards. Power to the SD interface is supplied by inserting the appropriate card into the SD/MMC connector. It also features card detection, a lock mechanism, and a smooth extraction function by pushing the card in and out.

DIP switch S1 provides a toggle between eMMC and SD card boot. In order to boot from SD card, S1 must be switched ON (refer to Boot Switch for further information).

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1SD2_DATA2_EXTSD1.8 V / 3.3 VData Lane 2
2SD2_DATA3_EXTSD1.8 V / 3.3 VData Lane 3
3SD2_CMD_EXTSD1.8 V / 3.3 VCommand Lane
4VCC_3V3--3.3 V Supply
5SD2_CLK_EXTSD1.8 V / 3.3 VClock Lane
6GND--Ground
7SD2_DATA0_EXTSD1.8 V / 3.3 VData Lane 0
8SD2_DATA1_EXTSD1.8 V / 3.3 VData Lane 1
9X_SD2_CD_BSD1.8 V / 3.3 VCard Detect
10GND--Ground

X4 Pin Assignment

SD / MM Card Design Considerations

Series resistors are placed on the PCL-066 to adapt the i.MX 8's drive strength. Series resistors might be required to adapt the drive strength of the card. The trace length between CLK, CMD, and DATA lanes should be matched. The voltage of the SD2 signal lanes is NVCC_SD2 and can switch between 1.8 V and 3.3 V. The supply voltage of the SD card remains 3.3 V and should not be connected to NCVV_SD2. Even when the signal level is fixed to 3.3V, NVCC_SD2 cannot provide enough power to supply an SD card as it is only a reference voltage.

PCIe (X6)

PCIe Interface (X6)

The 1-lane PCI express interface provides PCIe Gen. 2.0 functionality, which supports 5 Gbit/s operations. The interface is fully backwards compatible with the 2.5 Gbit/s Gen. 1.1 specification. Various control signals are implemented with GPIOs. The PCIe interface is brought out at the Mini PCIe connector X6 shown above.

The table below shows in-depth information such as pin assignment and signals used to implement special features of the Mini PCIe interface.

Interface Pin #

Signal name

Signal Type

Signal Level

Description

1

X_SAI1_RXD5/BOOT_CFG5

I/O

3.3 V

nWAKE

2

VCC_3V3

-

-

3.3 V Supply

3

X_SAI1_TXD0/BOOT_CFG8

I/O

3.3 V

RSVD1

4

GND

-

-

Ground

5

X_SAI1_TXD7/BOOT_CFG15

I/O

3.3 V

RSVD2

6

VCC_1V5

-

-

1.5 V Supply

7

miniPCIe_nCLKREQ

I/O

3.3 V

Inverted Clock Request

8

NC

-

-

-

9

GND

-

-

Ground

10

NC

-

-


11

miniPCIe_REFCLK100M_N

PCIe Ref. Clock

Analog

100 MHz Reference Clock Negative Lane

12

NC

-

-

-

13

miniPCIe_REFCLK100M_P

PCIe Ref. Clock

Analog

100 MHz Reference Clock Positive Lane

14

NC

-

-

-

15

GND

-

-

Ground

16

NC

-

-

-

17

NC

-

-

-

18

GND

-

-

Ground

19

NC

-

-

-

20

NC

-

-

-

21

GND

-

-

Ground

22

X_POR_B / X_SAI1_RXD1/BOOT_CFG1

nReset

3.3 V

Select with J30

23

X_PCIE2_RXN_N

PCIe

Analog

SOM Receive Negative Lane

24

VCC_3V3

-

-

3.3 V Supply

25

X_PCIE2_RXN_P

PCIe

Analog

SOM Receive Positive Lane

26

GND

-

-

Ground

27

GND

-

-

Ground

28

VCC_1V5

-

-

1.5 V Supply

29

GND

-

-

Ground

30

X_I2C2_SCL

I2C

3.3 V

Clock

31

X_PCIE2_TXN_N

PCIe TXN

Analog

SOM Transmit Negative Lane

32

X_I2C2_SDA

I2C

3.3 V

Data

33

X_PCIE2_TXN_P

PCIe

Analog

SOM Transmit Positive Lane

34

GND

-

-

Ground

35

GND

-

-

Ground

36

USB_HUB_DN3_D-

USB

Analog

USB 2.0 Negative Lane

37

GND

-

-

Ground

38

USB_HUB_DN3_D+

USB

Analog

USB 2.0 Positive Lane

39

VCC_3V3

-

-

3.3 V Supply

40

GND

-

-

Ground

41

VCC_3V3

-

-

3.3 V Supply

42

TP1




43

GND

-

-

Ground

44

TP2

-

-

-

45

NC

-

-

-

46

TP3

-

-

-

47

NC

-

-

-

48

VCC_1V5

-

-

1.5 V Supply

49

NC

-

-

-

50

GND

-

-

Ground

51

NC

-

-

-

52

VCC_3V3

-

-

3.3 V Supply

S1

GND

-

-

Ground

S2

GND

-

-

Ground

X33 Pin Assignment

PCIe Design Considerations

100nF AC-Coupling capacitors are placed at the output of the phyCORE-i.MX 8M in series to the TX-Lanes. No further TX coupling capacitors are needed. The differential impedance should be 85 Ohm for TX and RX lanes and 100 Ohm for the clock lane.

Camera Connectivity (X10 and X11)

 

 phyCAM-M MIPI CSI-2 Camera Interfaces (X10 and X11)

The phyCORE-imMX 8M on the phyBOARD-Polaris offers 2 independant interfaces to connect digital camera boards with MIPI CSI-2 interface. The 4-lane MIPI CSI-2 interfaces are brought out as phyCAM-M camera interfaces at connectors X10 and X11. The pin assignments of connectors X10 and X11 are given below.

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1

GND

-

-

Ground

2

X_MIPI_CSI1_D0_P

MIPI CSI-2Analog

MIPI-CSI-2 Data 0 Positive Lane

3

X_MIPI_CSI1_D0_N

MIPI CSI-2Analog

MIPI-CSI-2 Data 0 Negative Lane

4

GND

-

-

Ground

5

X_MIPI_CSI1_D1_P

MIPI CSI-2Analog

MIPI-CSI-2 Data 1 Positive Lane

6

X_MIPI_CSI1_D1_N

MIPI CSI-2Analog

MIPI-CSI-2 Data 1 Negative Lane

7

GND

-

-

Ground

8

X_MIPI_CSI1_CLK_P

MIPI CSI-2Analog

MIPI-CSI-2 Clock Positive Lane

9

X_MIPI_CSI1_CLK_N

MIPI CSI-2Analog

MIPI-CSI-2 Clock Negative Lane

10

GND

-

-

Ground

11

X_MIPI_CSI1_D2_P

MIPI CSI-2Analog

MIPI-CSI-2 Data 2 Positive Lane

12

X_MIPI_CSI1_D2_N

MIPI CSI-2Analog

MIPI-CSI-2 Data 2 Negative Lane

13

GND

-

-

Ground

14

X_MIPI_CSI1_D3_P

MIPI CSI-2Analog

MIPI-CSI-2 Data 3 Positive Lane

15

X_MIPI_CSI1_D3_N

MIPI CSI-2Analog

MIPI-CSI-2 Data 3 Negative Lane

16

GND

-

-

Ground

17

X_SAI1_RXC

GPIO3.3 V

CSI2_CTRL4

18

X_SAI1_RXFS

GPIO3.3 V

CSI2_CTRL3

19

X_SAI1_MCLK

GPIO3.3 V

CSI2_CTRL2

20

X_SD2_RESET_B

GPIO3.3 V

CSI2_CTRL1

21

GND

-

-

Ground

22

X_I2C4_SCL

I2C3.3 V

Clock

23

X_I2C4_SDA

I2C3.3 V

Data

24

CSI1_I2C_ADR

GPIO3.3 V

Choose the I2C address of the Camera

25

CSI1_ nRESET

GPIO3.3 V


26

CSI1_VCC_SELECT

GPIO3.3 V

Interface voltage selection

27

GND

-

-

Ground

28

VCC_CAM_CSI1

--

Supply of Camera

29

VCC_CAM_CSI1

--

Supply of Camera

30

VCC_CAM_CSI1

--

Supply of Camera

X10  CSI-1 Pin Assignment

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1

GND

-

-

Ground

2

X_MIPI_CSI2_D0_P

MIPI CSI-2Analog

MIPI-CSI-2 Data 0 Positive Lane

3

X_MIPI_CSI2_D0_N

MIPI CSI-2Analog

MIPI-CSI-2 Data 0 Negative Lane

4

GND

-

-

Ground

5

X_MIPI_CSI2_D1_P

MIPI CSI-2Analog

MIPI-CSI-2 Data 1 Positive Lane

6

X_MIPI_CSI2_D1_N

MIPI CSI-2Analog

MIPI-CSI-2 Data 1 Negative Lane

7

GND

-

-

Ground

8

X_MIPI_CSI2_CLK_P

MIPI CSI-2Analog

MIPI-CSI-2 Clock Positive Lane

9

X_MIPI_CSI2_CLK_N

MIPI CSI-2Analog

MIPI-CSI-2 Clock Negative Lane

10

GND

-

-

Ground

11

X_MIPI_CSI2_D2_P

MIPI CSI-2Analog

MIPI-CSI-2 Data 2 Positive Lane

12

X_MIPI_CSI2_D2_N

MIPI CSI-2Analog

MIPI-CSI-2 Data 2 Negative Lane

13

GND

-

-

Ground

14

X_MIPI_CSI2_D3_P

MIPI CSI-2Analog

MIPI-CSI-2 Data 3 Positive Lane

15

X_MIPI_CSI2_D3_N

MIPI CSI-2Analog

MIPI-CSI-2 Data 3 Negative Lane

16

GND

-

-

Ground

17

X_SAI1_TXC

GPIO3.3 V

CSI2_CTRL4

18

X_SAI1_TXFS

GPIO3.3 V

CSI2_CTRL3

19

X_SAI2_RXC

GPIO3.3 V

CSI2_CTRL2

20

X_SAI2_RXFS

GPIO3.3 V

CSI2_CTRL1

21

GND

-

-

Ground

22

X_I2C4_SCL

I2C3.3 V

Clock

23

X_I2C4_SDA

I2C3.3 V

Data

24

CSI2_I2C_ADR

GPIO3.3 V

Choose the I2C address of the Camera

25

CSI2_nRESET

GPIO3.3 V


26

CSI2_VCC_SELECT

GPIO3.3 V

Interface voltage selection

27

GND

-

-

Ground

28

VCC_CAM_CSI2

--

Supply of Camera

29

VCC_CAM_CSI2

--

Supply of Camera

30

VCC_CAM_CSI2

--

Supply of Camera

X11 CSI-2 Pin Assignment

Camera Design Considerations

Regarding camera connections when designing a customer carrier board:

  1. phyCAM-M interfaces offer 3.3V or 5.0V supply voltages (selected by interface pin 26). Both voltages must be provided from the board.
  2. Each phyCAM interface has a different I2C address. R570 for the CSI-1 address is not mounted; R569 for the CSI-2 address is mounted.
  3. The strobe signal (CTRL1) of the CSI2 interface can be connected to the trigger signal (CTRL2) of the CSI1 interface. R542 has to be mounted for this to be possible.

General information and design guidelines for PHYTEC camera interfaces can be found here: https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-748e_10.pdf → phyCAM Concept and Design-In
Specific information for each PHYTEC camera module can be found in that module's download page: https://www.phytec.de/produkte/embedded-imaging/phycam/

HDMI (X32)

HDMI Connector (X32)

The phyBOARD‑Polaris provides a High-Definition Multimedia Interface (HDMI) which is compliant with HDMI 2.0a and HDCP 1.4/2.2. It supports one display at a maximum pixel clock of up to 596 MHz and a maximum resolution of 4096x2160 at 60Hz. Other resolutions are 3840x2160p60, 1920x1080p60, 1280x720p60, 720x480p60, 640x480p60. Please refer to the i.MX 8M Applications Processor ReferenceManual for more information.

The HDMI interface is brought out at a standard HDMI type A connector (X32) on the phyBOARD‑Polaris and is comprised of the following signal groups:

  • Three pairs of data signals
  • One pair of clock signals
  • The Display Data Channel (DDC)
  • The Consumer Electronics Control (CEC)
  • The Hot Plug Detect (HPD) signal
  • Audio Return Channel (ARC)

All signals are routed from the phyCORE‑Connector to the HDMI receptacle through ESD Protection Diodes.

Warning

Ensure that all module connections do not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller User's Manual/Data Sheets. As damage from improper connections varies according to use and application, it is the user‘s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1

X_HDMI_TX_P_LN_2HDMIAnalogHDMI TX Data 2 Positive Lane

2

GND

-

-

Ground

3

X_HDMI_TX_M_LN_2HDMIAnalogHDMI TX Data 2 Negative Lane

4

X_HDMI_TX_P_LN_1HDMIAnalogHDMI TX Data 1 Positive Lane

5

GND

-

-

Ground

6

X_HDMI_TX_M_LN_1HDMIAnalogHDMI TX Data 1 Negative Lane

7

X_HDMI_TX_P_LN_0HDMIAnalogHDMI TX Data 0 Positive Lane

8

GND

-

-

Ground

9

X_HDMI_TX_M_LN_0HDMIAnalogHDMI TX Data 0 Negative Lane

10

X_HDMI_TX_P_LN_3HDMIAnalogHDMI TX Clock Positive Lane

11

GND

-

-

Ground

12

X_HDMI_TX_M_LN_3HDMIAnalogHDMI TX Clock Negative Lane

13

X_HDMI_CECHDMI CEC3.3 VConsumer Electronics Control

14

X_HDMI_AUX_PUtility/ HEAC+3.3 VAudio Return Channel Positive Lane

15

X_HDMI_DDC_SCLHDMI DDC5 VClock

16

X_HDMI_DDC_SDAHDMI DDC5 VData

17

GND

-

-

Ground

18

VCC_5V_HDMI--5 V Supply for HDMI Device

19

X_HDMI_AUX_NHPD/ HEAC-5V / 3.3VHot Plug detect/ Audio Return Channel Negative Lane

20

SHIELD_1

-

-

Shield connected to Ground over 2,2 nF parallel to 1 MOhm

21

SHIELD_2

-

-

Shield connected to Ground over 2,2 nF parallel to 1 MOhm

22

SHIELD_3

-

-

Shield connected to Ground over 2,2 nF parallel to 1 MOhm

23

SHIELD_4

-

-

Shield connected to Ground over 2,2 nF parallel to 1 MOhm

X32 Pin Assignment

HDMI Design Considerations

The DDC lanes need pull-up resistors between 1.5k and 2k to 5V. The CEC lane needs a 27k pull-up resistor connected to 3.3V through a diode. This prevents leaking current in a power-off state. HPD should be pulled low with a 1M resistor.

Audio Interface (X14 and X15)

Speaker Connection (X14) / Line In - Line Out (X15)

The audio interface provides a method of exploring and using i.MX 8M's audio capabilities. The phyBOARD-Polaris is populated with an audio codec at U60. The audio codec is connected to the i.MX 8M's SAI interface to support stereo line input and output at connector X15. A direct mono speaker output (1 W) is available at Molex connector X14. The audio codec can be configured via I2C at address 0x18.

Additional signals are routed to the A/V connector X18. Refer to the section Audio/Video Connectors (X16 and X18)for more information. For additional information regarding special interface specifications, refer to the audio codec reference manual.

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1

SPOPAudioAnalogSpeaker Output Positiv Lane

2

SPOM

AudioAnalogSpeaker Output Negative Lane

X14 Pin Assignment

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1

LINE_IN_LAudioAnalogLine In left channel

2

LINE_IN_R

AudioAnalogLine In right channel
3

AGND

-

-

Analog Ground

4

AGND

-

-

Analog Ground

5HP_OUT_LAudioAnalogHeadphone output left
6HP_OUT_RAudioAnalogHeadphone output right

X15 Pin Assignment

Audio/Video Connectors (X16 and X18)

Audio/Video Connectors (X16 and X18)

The Audio/Video (A/V) connectors X16 and X18 provide an easy way to add typical A/V functions and features to the phyBOARD‑Polaris. Standard interfaces such as MIPI-DSI, I2S and I2C, as well as different supply voltages are available at the two A/V female dual entry connectors.  A special feature of these connectors are their connectivity from the top or bottom.

The A/V connector is intended to be used with phyBOARD Expansion Boardsand to add specific audio/video connectivity with custom expansion boards. A/V connector X16 makes all signals for display connectivity available, while X18 provides signals for audio and touch screen connectivity as well as an I2C bus and additional control signals. The tables below show the pin assignment of connectors X16 and X18.

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

GND

-

-

Ground

2

X_MIPI_DSI_CLK_P

MIPI DSI

Analog

MIPI DSI Clock Positive Lane

3

X_MIPI_DSI_D3_P

MIPI DSI

Analog

MIPI DSI Data 3 Positive Lane

4

X_MIPI_DSI_CLK_N

MIPI DSI

Analog

MIPI DSI Clock Negative Lane

5

X_MIPI_DSI_D3_N

MIPI DSI

Analog

MIPI DSI Data 3 Negative Lane

6

GND

-

-

Ground

7

GND

-

-

Ground

8

X_MIPI_DSI_D2_P

MIPI DSI

Analog

MIPI DSI Data 2 Positive Lane

9

X_MIPI_DSI_D1_P

MIPI DSI

Analog

MIPI DSI Data 1 Positive Lane

10

X_MIPI_DSI_D2_N

MIPI DSI

Analog

MIPI DSI Data 2 Negative Lane

11

X_MIPI_DSI_D1_N

MIPI DSI

Analog

MIPI DSI Data 1 Negative Lane

12

GND

-

-

Ground

13

GND

-

-

Ground

14

X_MIPI_DSI_D0_P

MIPI DSI

Analog

MIPI DSI Data 0 Positive Lane

15

VCC_IN_24V

-

-

Input Supply of phyBOARD Polaris

16

X_MIPI_DSI_D0_N

MIPI DSI

Analog

MIPI DSI Data 0 Negative Lane

X16 Pin Assignment

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

USB_HUB_DN2_D+

USB

Analog

USB 2.0 Data postive

2

USB_HUB_DN2_D-

USB

Analog

USB 2.0 Data negative

3

X_nRESET_IN

Reset

3.3 V

Reset Input to SOM

4

GND

-

-

Ground

5

X_SAI3_RXD

SAI3

3.3 V

RXD

6

X_SAI3_TXFS

SAI3

3.3 V

TXFS

7

X_SAI3_TXC

SAI3

3.3 V

TXC

8

X_SAI3_TXD

SAI3

3.3 V

TXD

9

X_SAI3_MCLK

SAI3

3.3 V

MCLK

10

X_SAI3_RXFS

SAI3

3.3 V

RXFS

11

GND

-

-

Ground

12

X_SAI3_RXC

SAI3

3.3 V

RXC

13

X_SAI5_RXD3

SAI5

3.3 V

RXD3

14

GND

-

-

Ground

15

X_SAI5_RXFS

SAI5

3.3 V

RXFS

16

X_SAI5_RXD2

SAI5

3.3 V

RXD2

17

X_SAI5_RXC

SAI5

3.3 V

RXC

18

X_SAI3_RXD1

SAI3

3.3 V

RXD1

19

X_SAI3_MCLK

SAI3

3.3 V

MCLK

20

X_SAI3_RXD0

SAI3

3.3 V

RXD0

21

GND

-

-

Ground

22

X_I2C2_SDA

I2C

3.3 V

Data

23

X_UART2_RXD

UART

3.3 V

SOM Receive

24

X_I2C2_SCL

I2C

3.3 V

Clock

25

X_UART2_TXD

UART

3.3 V

SOM Transmit

26

GND

-

-

Ground

27

VCC_5V

-

-

5.0 V Supply

28

VCC_3V3

-

-

3.3 V Supply

29

VCC_5V

-

-

5.0 V Supply

30

VCC_3V3

-

-

3.3 V Supply

X18 Pin Assignment

Expansion Connector (X8)

Expansion Connector (X8)

The expansion connector X8 provides an easy way to add other functions and features to the phyBOARD‑Polaris. Standard interfaces such as QSPI, USB, SPDIF, JTAG, UART, SPI, and I2C are avaiable at the expansion connector. The expansion connector is intended to be used with a phyBOARD Evaluation Adapter. The expansion connector can also add specific functions with custom expansion boards. Information on the Evaluation Adapter for the expansion connector can be found in the Application Guide for phyBOARD Expansion Boards (L‑793e).

The pinout of the expansion connector is shown in the table below:

Interface Pin #

Signal Name

Signal Type

Signal Level

Description

1

VCC_3V3

-

-

3.3 V supply

2

VCC_5V

-

-

5.0 V supply

3

VCC_1V5

-

-

1.5 V supply

4

GND

-

-

Ground

5

X_ECSPI1_SS0

SPI

3.3 V

Slave Select

6

X_ECSPI1_MOSI

SPI

3.3 V

MOSI

7

X_ECSPI1_MISO

SPI

3.3 V

MISO

8

X_ECSPI1_SCLK

SPI

3.3 V

Clock

9

GND

-

-

Ground

10

UART1_RX_EXP

UART

3.3 V

SOM Receive

11

X_I2C2_SDA

I2C

3.3 V

Data

12

UART1_TX_EXP

UART

3.3 V

SOM Transmit

13

X_I2C2_SCL

I2C

3.3 V

Clock

14

GND

-

-

Ground

15

X_JTAG_TMS

JTAG

3.3 V

TMS

16

X_JTAG_TRST_B

JTAG

3.3 V

nTRST

17

X_JTAG_TDI

JTAG

3.3 V

TDI

18

X_JTAG_TDO

JTAG

3.3 V

TDO

19

GND

-

-

Ground

20

X_JTAG_TCK

JTAG

3.3 V

TCK

21

USB_HUB_DN4_D+

USB

Analog

USB 2.0 Data positive

22

USB_HUB_DN4_D-

USB

Analog

USB 2.0 Data Negative

23

X_nRESET_IN

Reset

3.3 V

Reset Input to SOM

24

GND

-

-

Ground

25

X_SPDIF_TX

SPDIF

3.3 V

SOM transmit

26

X_SPDIF_RX

SPDIF

3.3 V

SOM receive

27

X_SPDIF_EXT_CLK

SPDIF

3.3 V


28

X_NAND_DATA07

GPIO

3.3 V


29

GND

-

-

Ground

30

X_NAND_DATA06

GPIO

3.3 V


31

UART3_RXD_EXP

UART

3.3 V

SOM receive

32

X_NAND_DATA05

GPIO

3.3 V


33

UART3_TXD_EXP

UART

3.3 V

SOM transmit

34

GND

-

-

Ground

35

X_NAND_CE3_B

GPIO

3.3 V


36

X_NAND_DATA04

GPIO

3.3 V


37

X_NAND_CLE

GPIO

3.3 V


38

X_NAND_DATA03

GPIO

3.3 V

Only available when SOM is without NOR Flash

39

X_NAND_WE_B

GPIO

3.3 V


40

X_NAND_DATA02

GPIO

3.3 V

Only available when SOM is without NOR Flash

41

GND

-

-

Ground

42

X_NAND_DATA01

GPIO

3.3 V

Only available when SOM is without NOR Flash

43

X_POR_B

nPOR

3.3 V

POR_B Pin of i.MX 8M

44

X_NAND_DATA00

GPIO

3.3 V

Only available when SOM is without NOR Flash

45

X_NAND_READY_B

GPIO

3.3 V


46

GND

-

-

Ground

47

X_NAND_CE0_B

GPIO

3.3 V

Only available when SOM is without NOR Flash

48

X_NAND_CE2_B

GPIO

3.3 V


49

X_NAND_CE1_B

GPIO

3.3 V


50

X_NAND_ALE

GPIO

3.3 V

Only available when SOM is without NOR Flash

51

GND

-

-

Ground

52

X_NAND_RE_B

GPIO

3.3 V


53

USB_HUB_nPWRCTL4

USB nPWR

3.3 V

Inverted Power Contorl Pin of USB HUB

54

USB_HUB_nOVERCUR4

USB nOC

3.3 V

Inverted Overcurrent Pin of USB HUB

55

X_NAND_DQS

GPIO

3.3 V


56

GND

-

-

Ground

57

VCC_IN_24V

-

-

Input Supply of phyBOARD

58

X_NAND_WE_B

GPIO

3.3 V


59

GND

-

-

Ground

60

VCC_5V_REG

-

-

5.0 V Supply

X8 Expansion Pinout

Multicolor (RGB) LED (D11)

The phyBOARD-Polaris provides one multicolor (RGB) LED (D11) (see phyBOARD-Polaris Components (Top)). The table below shows the signals that control colors:

Color

Signal

Description

Red

X_GPIO1_IO01

PWM1

Green

X_SAI1_RXD6/BOOT_CFG6

No PWM at this pin.

Blue

X_I2C3_SCL

PWM4

Multicolor LED Configuration

Switches

phyBOARD-Polaris Switch Locations

Boot Switch (S1)

The phyBOARD‑Polaris has three defined boot sources which can be selected with DIP switch S1.

Boot ModeDescription
S1 Pos 1= OFF, S4 Pos 4 = OFFSOM Boot Configuration (eMMC)
S1 Pos 1= ON, S4 Pos 4 = OFFBoot from SD Card
S4 Pos 4 = ONSerial Downloader

Boot Switch Configuration Options (S1)

Boot Mode Design Considerations

Bootpin voltages have to be valid when X_POR_B is released.

System Reset Button (S2)

The phyBOARD‑Polaris is equipped with a system reset button at S2. Pressing this button will toggle the X_nRESET_IN pin (X31 Pin A64) of the phyCORE SOM low, causing the module to reset with a complete power cycle.

System ON/OFF Button (S3)

The phyBOARD-Polaris is equipped with an ON/OFF button at S3. For more information, refer to the i.XM 8M Reference Manual.

Additional System Level Hardware Information

I2C Connectivity

The I2C1 interface of the i.MX 8M is only available on the phyCORE module and is not connected to the phyBOARD‑Polaris. The table below provides a list of the connectors and pins with I2C connectivity:

Interface 

Location

I2C2 at X8

Pin 11(SDA)/13(SCL)

I2C2 at X18

Pin 22(SDA)/24(SCL)

I2C2 at X6

Pin 32(SDA)/30(SCL)

I2C4 at X10

Pin 22(SCL)/23(SDA)

I2C4 at X11

Pin 22(SCL)/23(SDA)

I2C2 and I2C4 Connectivity

To avoid any conflicts when connecting external I2C devices to the phyBOARD‑Polaris, the addresses of the on-board I2C devices must be considered. The table below lists the addresses already in use and shows only the default address. The I²C addresses are hexadecimal in 8 bit representation. In Linux, 7-bit representation may be used. In this case, the address value must be shifted one digit to the right. The specification refers to the write address (bit 0 = 0), the read address is increased by 1 to bit 1 = 1.

Board

Prod. No.

Device

Address used (7 MSB)

I2C4

phyCAM-P monochrome / color

VM-016-COL-x

Camera (X10)0x20 and 0xAC at VM-016, check your camera board
Camera (X11)0x30 and 0xAE at VM-016, check your camera board


Expansion Connector-
I2C2
Onboard

Audio Codec (U60)

0x18

Onboard

USB-Hub (U74)

0x44 (! SMBus)

OnboardminiPCIe Con. (X6)check your miniPCIe card (! SMBus)
Display AdapterPEB_AV_09A/V-CON. (X18) with PEB-AV-090x2C

I2C Addresses in Use

Revision History

Changes in this manual

Version #

Changes in this manual



25.10.2019



L-863e-A0

Preliminary Manual
Describes the phyCORE‑i.MX 8M
SOM Version: 1497.2
Describes the phyBOARD-Polaris
PCB Version: 1501.2