Preface

As a member of PHYTEC's phyCORE^® product family the phyCORE‑i.MX 6 is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers and, hence, offers various functions and configurations. PHYTEC supports a variety of 8-/16- and 32-bit controllers in two ways:

1. as the basis for Rapid Development Kits which serve as a reference and evaluation platform
2. as insert-ready, fully functional phyCORE^® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows you to focus on hardware peripherals and firmware without expending resources to "re-invent" microcontroller circuitry. Furthermore, much of the value of the phyCORE^® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce your development time and risk and allow you to focus on your product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative full system solution, you will be able to bring your new ideas to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Ordering Information

The part numbering of the phyCORE has the following structure:

Product Specific Information and Technical Support

In order to receive product-specific information on changes and updates in the best way also in the future, we recommend registering at:

http://www.phytec.de/support/registrierung.htmlor http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.

https://www.phytec.de/produkte/system-on-modules/phycore-imx-6/#downloads/

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 6

PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly with respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Product Change Management and Information Regarding Parts Populated on the SOM / SBC

With the purchase of a PHYTEC SOM / SBC, you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCNs (Product Change Notifications) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.

Our general philosophy here is: We never discontinue a product as long as there is a demand for it.

Therefore, we have established a set of methods to fulfill our philosophy:

Avoidance strategies:

• Avoid changes by evaluating the longevity of parts during the design-in phase.
• Ensure the availability of equivalent second source parts.
• Stay in close contact with part vendors to be aware of roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

• Ensure long-term availability by stocking parts through last-time buy management according to product forecasts.
• Offer long-term frame contracts to customers.

Change management in case of functional changes:

• Avoid impacts on product functionality by choosing equivalent replacement parts.
• Avoid impacts on product functionality by compensating for changes through hardware redesign or backward-compatible software maintenance.
• Provide early change notifications concerning functional, relevant changes to our products.

We refrain from providing detailed part-specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

• Quickstart Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a BSP, the device tree, and accessing peripherals.
• Hardware Manual:  A detailed description of the System on Module and accompanying carrier board. 
• Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; an introduction, installing, and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
• BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
• Development Environment Guide:  This guide shows how to work with the Virtual Machine (VM) Host PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running demo projects for these programs on a phyCORE product as well. Information on how to build a Linux host PC yourself is also a part of this guide.
• Pin Muxing Table:  phyCORE SOMs have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case-by-case basis. Most of the documentation can be found on the applicable download page of our products.

Conventions, Abbreviations, and Acronyms

This hardware manual describes the PCM-058 System on Module in the following referred to as phyCORE^®-i.MX 6. The manual specifies the phyCORE^®-i.MX 6's design and function. Precise specifications for the NXP® Semiconductor i.MX 6 micro­controllers can be found in the enclosed Microcontroller Data Sheet/User's Manual.

Conventions

The conventions used in this manual are as follows:

• Signals that are preceded by an "n", "/", or “#” character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low or are driving low.
• A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
• The hex numbers are given for addresses of I²C devices always represent the 7 MSB of the address byte. The correct value of the LSB which depends on the desired command (read (1), or write (0)) must be added to get the complete address byte. E.g.  given address in this manual 0x41 => complete address byte = 0x83 to read from the device and 0x82 to write to the device
• Tables that describe jumper settings show the default position in bold,bluetext.
• Text in blue indicates a hyperlink within, or external to the document. Click these links to quickly jump to the applicable URL, part, chapter, table, or figure.

References made to the phyCORE-Connector always refer to the high-density Samtec connector on the undersides of the phyCORE‑i.MX 6 System on Module.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of a signal.

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document.

phyCORE-i.MX 6 Introduction

The phyCORE‑i.MX 6 belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, the phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

As independent research indicates that approximately 70 % of all EMI (Electro-Magnetic Interference) problems stem from insufficient supply voltage grounding of electronic components in high-frequency environments, the phyCORE board design features an increased pin package. The increased pin package allows the dedication of approximately 20 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards even in high-noise environments.

phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In accordance with the complexity of the module, 0402-packaged SMD components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 6 is a subminiature (40 mm x 50 mm) insert-ready System on Module populated with the NXP® Semiconductor i.MX 6 microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch (0.5 mm) connectors aligning two sides of the board, allowing it to be plugged like a "big chip" into a target application.

Precise specifications for the controller populating the board can be found in the applicable controller reference manual or datasheet. The descriptions in this manual are based on the NXP® Semiconductor i.MX 6. No description of com­patible microcontroller derivative functions is included, as such func­tions are not relevant for the basic functioning of the phyCORE‑i.MX 6.

Features of the phyCORE-i.MX 6

The phyCORE‑i.MX 6 offers the following features:

• Insert-ready, sub-miniature (40mm x 50 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology
• Populated with the NXP® Semiconductor i.MX 6 microcontroller (BGA624 packaging)
• 1.0 GHz core clock frequency (optional 1.2 GHz)
• Boot from different memory devices (NAND Flash (standard))
• Controller signals and ports extend to two high-density (0.5mm) Samtec connectors aligning two sides of the board, enabling the phyCORE‑i.MX 6 to be plugged like a "big chip" into the target application
• Single supply voltage of +3.3 V with on-board power management
• All controller-required supply voltages are generated onboard
• Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins

• 512MB (up to 2 GB^[1]) DDR3 SDRAM

• 256 MB (up to 16 GB^[1]) onboard NAND Flash
• Alternatively 2 GB (up to 32GB^[1]) onboard eMMC
• 16 MB2 on-board serial Flash (bootable)
• 4kB2 I²C EEPROM
• 2x serial interfaces (TTL). One with 4 lines allows a simple hardware handshake
• 1x High-Speed USB OTG interface
• 1x High-Speed USB HOST interface

• 1x 10/100/1000 Mbit Ethernet interface. Either with Ethernet transceiver on the phyCORE-i.MX 6 allowing for direct connection to an existing Ethernet network, or without onboard transceiver and provision of the RMII signals at TTL-level at the phyCORE-Connector instead^[2]

• 1x I²C interface
• 2x  SPI interfaces
• 1x PCIe interface
• 1x I²S interface
• 1x SPDIF interface
• 1x PWM output
• 1x CAN interface
• 2x 4-channel LVDS (24-bit) LCD-interfaces
• 1x Parallel LCD interface with up to 24-bit
• 1x HDMI interface
• Up to 2x parallel camera interfaces
• 1x MIPI CSI camera interface
• 2x SD/MMC card interfaces (1 x 8 bit, 1 x 4 bit)
• 1x SATA interface
• 1x JTAG interface
• 1x user-programmable LED
• Tamper detection

• Several dedicated GPIOs^[3]

• Power Management IC (PMIC)
• Available for different temperature grades (Product Temperature Grades)

Block Diagram

phyCORE-i.MX 6 Component Placement

Minimum Requirements to Operate the phyCORE-i.MX 6

The basic operation of the phyCORE‑i.MX 6 only requires a supply of a +3.3 V input voltage with a typical 2.5 A load and the corresponding GND connection.

These supply pins are located at the phyCORE-Connector X1:

     VDD_3V3:                           X1       A1, A2, A3, A4, B1, B2, B3, B4

Connect all +3.3 V VCC input pins to your power supply and at least the matching number of GND pins.

     Corresponding GND:           X1      A6, A11, A16, A21, B6, B12, B17, B22

Please refer to Pin Description for information on additional GND Pins located at the phyCORE-Connector X1.

Pin Description

Please note that all module connections are not to exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller manuals/datasheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

As Pinout of the phyCORE-Connector (top view) indicates, all controller signals selected extend to surface mount technology (SMT) connectors (0.5 mm) lining two sides of the module (referred to as phyCORE‑Connector). This allows the phyCORE‑i.MX 6 to be plugged into any target application like a "big chip".

The numbering scheme for the phyCORE‑Connector is based on a two-dimensional matrix in which column positions are identified by a letter and row positions by a number. The pin numbering values increase moving down on the board (Pinout of the phyCORE-Connector (top view)).

The numbered matrix can be aligned with the phyCORE‑i.MX 6 (viewed from above; phyCORE‑Connector pointing down) or with the socket of the corresponding phyCORE Carrier Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin X1C1) is thus covered with the corner of the phyCORE‑i.MX 6. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.

The numbering scheme is thus consistent for both the module’s phyCORE-Connector as well as the mating connector on the phyCORE Carrier Board or target hardware, thereby considerably reducing the risk of pin identification errors.

Since the pins are exactly defined according to the numbered matrix previously described, the phyCORE-Connector is usually assigned a single designator for its position (X1 for example). In this manner, the phyCORE‑Connector comprises a single, logical unit regardless of the fact that it could consist of more than one physical socketed connector.

The following figure illustrates the numbered matrix system. It shows a phyCORE‑i.MX 6 with both SMT phyCORE-Connectors on its underside (defined as dotted lines) mounted on a carrier board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a cross-view of the phyCORE‑i.MX 6 module showing the phyCORE-Connector mounted on the underside of the module’s PCB.

The following tables provide an overview of the pinout of phyCORE-Connector X1 with signal names and descriptions specific to phyCORE‑i.MX 6. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type includes also information about the signal direction. A description of the signal types can be found in Types of Signals.

Jumpers

For configuration purposes, the phyCORE‑i.MX 6 has several solder jumpers, some of which have been installed prior to delivery. Typical Jumper Pad Numbering Scheme illustrates the numbering of the solder jumper pads, while Jumper Locations (PCB 1429.3, top view) and Jumper Locations (PCB 1429.3, bottom view) indicate the location and the default configuration of the solder jumpers on the board.

The table below provides a functional summary of the solder jumpers which can be changed to adapt the phyCORE‑i.MX 6 to your needs. It shows their default positions, and possible alternative positions and functions. A detailed description of each solder jumper can be found in the applicable chapter listed in the table.

If manual jumper modification is required please ensure that the board, as well as surrounding components and sockets, remain undamaged while de-soldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. Carefully heat neighboring connections in pairs. After a few alternations, components can be removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and loosen the bonds.

Please pay special attention to the “TYPE” column to ensure you are using the correct type of jumper (0 Ohms, 10k Ohms, etc…). The jumpers are 0402 packages with a 1/8 W or better power rating.

The jumpers (J = solder jumper) have the following functions:

Power

The phyCORE‑i.MX 6 operates off of a single power supply voltage. The following sections of this chapter discuss the primary power pins on the phyCORE‑Connector X1 in detail.

Primary System Power (VDD_3V3)

The phyCORE‑i.MX 6 operates off of a primary voltage supply with a nominal value of +3.3 V. On-board switching regulators generate the 2.5 V, 1.375 V, 1.5 V, 0.75 V, 1.2 V, and 3 V voltage supplies required by the i.MX 6 MCU and on-board components from the primary 3.3 V supplied to the SOM.

For proper operation the phyCORE‑i.MX 6 must be supplied with a voltage source of 3.3 V ±5 % with a 2.5 A load connected to the VCC pins of phyCORE-Connector X1.

     VDD_3V3:                               X1      A1, A2, A3, A4, B1, B2, B3, B4

Connect all +3.3 V VCC input pins to your power supply and at least the matching number of GND pins.

     Corresponding GND:           X1      A6, A11, A16, A21, B6, B12, B17, B22

Please refer to Pin Description for information on additional GND Pins located at the phyCORE‑Connector X1.

Special attention and testing have to be done for very slow ramping-up and -down power supplies like battery backup systems. PMIC (U16) prevents the processor and itself from continuing power-on / -off cycling. If the module power supply VDD_3V3 goes on and off in a range between 2.3V and 3.3V within the first 16 sec. after every start attempt three times in a row, a shutdown is initiated which needs a following special user wake-up event (X_PMIC_nONKEY) to start again. A complete power-off with VDD_3V3 = 0V will also reset the behavior.
For detailed information please check the PMIC datasheet or contact us.

Power Management IC (PMIC) (U16)

The phyCORE-i.MX 6 provides an onboard Power Management IC (PMIC) at position U16 to generate different voltages required by the microcontroller and the onboard components. Powering Scheme of the phyCORE- i.MX 6presents a graphical depiction of the powering scheme.

The PMIC supports many functions like on-chip RTC and different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 6 via the onboard I²C bus (I2C3). The I²C address of the PMIC is 0x58 (pages 0 and 1) and 0x59 (pages 2 and 3).

Power Domains

External voltages:

• VDD_3V3 3 V main supply voltage
• USB0_VBUS USB0 Bus voltage must be supplied with 5 V if USB0 is used
• USB1_VBUS USB1 Bus voltage must be supplied with 5 V if USB1 is used
• VDD_BAT Backup supply (connected to PMIC_VBBAT or VDD_MX6_SNVS via J3 (Jumper Settings))

Internally generated voltages:  

Supply Voltage for External Logic

The voltage level of the phyCORE’s logic circuitry is VDD_3V3_LOGIC (3.3 V), derived from the SOM's main input voltage VDD_3V3. In order to follow the power-up and power-down sequencing mandatory for the i.MX 6 external devices must be supplied by the I/O supply voltage VDD_3V3_LOGIC which is brought out at pin X1B5 of the phyCORE-Connector. VDD_3V3_LOGIC ensures that external components are only supplied when the supply voltages of the i.MX 6 are stable.

If used to control, or supply bus switches on the phyCORE side VDD_3V3_LOGIC also serves to strictly separate the supply voltages generated on the phyCORE‑i.MX 6 and the supply voltages used on the carrier board/custom application. That way, voltages at the IO pins of the phyCORE-i.MX 6 which are sourced from the supply voltage of peripheral devices attached to the SOM are avoided. These voltages can cause a current flow into the controller especially if peripheral devices attached to the interfaces of the i.MX 6 are supposed to be powered while the phyCORE‑i.MX 6 is in suspend mode or turned off. The bus switches can either be supplied by VDD_3V3_LOGIC on the phyCORE side, or the bus switches' output enable to the SOM can be controlled by X_3V3_GOOD to prevent these voltages from occurring.

The use of level shifters supplied with VDD_3V3_LOGIC allows converting the signals according to the needs of the custom target hardware. Alternatively, signals can be connected to an open drain circuitry with a pull-up resistor attached to VDD_3V3_LOGIC.

Backup Power (PMIC_VBAT / VDD_MX6_SNVS)

To back up the PMIC's RTC and some of its critical registers, or the i.MX 6's low power domain (SNVS_LP) and its RTC, a secondary voltage source of 3 V can be attached to the phyCORE‑i.MX 6 at pin X1A5. Jumper J3 selects either the backup voltage domain PMIC_VBAT (J3:1+2) or the i.MX6's voltage domain VDD_MX6_SNVS (J3:2+3) to be supplied when the primary system power (VDD_3V3) is removed.

Reset

Pin X1D32 on the phyCORE‑Connector is designated as reset input/output.

If used as reset input a hard reset of the module can be triggered. In this case, the external reset signal is connected to the nRESETREQ signal of the DA9062 PMIC which triggers a hard reset of the module with a debouncing time of 10.24 ms.

When used as reset output, the nRESET signal of the DA9062 PMIC is brought out to allow resetting devices on the carrier board.

In case of a hard reset, no matter if it was triggered externally or internally, the PMIC holds down the nRESET signal until the module voltages are generated. The nRESET signal is released 2 ms after the last module voltage is generated correctly.

System Configuration and Booting

Although most features of the i.MX 6 microcontroller are configured and/or pro­grammed during the initialization routine, other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

• Boot mode selection
• Boot device selection
• Boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 6 after POR. The ROM code detects the boot mode by using the boot mode pins (BOOT_MODE[1:0]), while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO input pins (BOOT_CFGx[7:0]).

Boot Mode Selection

The boot mode of the i.MX 6 microcontroller is determined by the configuration of two boot mode inputs BOOT_MODE[1:0] during the reset cycle of the operational system. These inputs are brought out at the phyCORE‑Connector pins X_BOOT_MODE[1:0] (X1D1, X1C1). Boot Modes of the phyCORE‑i.MX 6 shows the possible settings of pins X_BOOT_MODE0 (X1C1) and X_ BOOT_MODE1 (X1D1) and the resulting boot configuration of the i.MX 6.

The BOOT_MODE[1:0] lines have 10 kΩ pull‑up and pull-down resistors populated on the module. Hence leaving the two pins unconnected sets the controller to boot mode 2, internal boot.

For serial boot (boot mode = 1) the ROM code polls the communication interface selected, initiates the download of the code into the internal RAM, and triggers its execution from there. Please refer to the i.MX 6 Reference Manual for more information.

In boot modes 0 and 2, the ROM code finds the bootstrap in permanent memories such as NAND-Flash or SD-Cards and executes it. The selection of the boot device and the configuration of the interface required are accomplished with the help of the eFUSEs and/or the corresponding GPIO input pins.

Boot Device Selection and Configuration

In normal operation (boot mode 0, or 2), the boot ROM uses the state of BOOT_MODE and eFUSEs to determine the boot device.

During development, it is advisable to set the boot type to “Internal boot” (BOOT_MODE[1:0]=1014 to allow choosing and configuring the boot device by using GPIO pin inputs. The input pins are sampled at boot, and override the values of the corresponding eFUSEs BOOT_CFGx[7:0], if the BT_FUSE_SEL fuse is not blown.

Boot Configuration Pins at the phyCORE‑Connector list the eFUSEs BOOT_CFGx[7:0] and the corresponding input pins.

On the phyCORE‑i.MX 6 the GPIOs have 10 kΩ pull‑up and pull-down resistors preinstalled to configure eFUSEs BOOT_CFGx[7:0] in accordance with the module features.

However, the specific boot configuration settings, which are set by the on-board configuration resistors, can be changed by modifying the resistors on the module or by connecting a configuration resistor (e.g. 10 kΩ) to the configuration signal. Please consider that any change of the default BCFG configuration can also influence other boot modes, which might result in faulty boot behavior.

Please refer to the i.MX 6 Reference Manual for further information about the eFUSEs and the impact of the settings at the BCFG pins.

System Memory

The phyCORE‑i.MX 6 provides four types of on-board memory:

The following sections of this chapter detail each memory type used on the phyCORE‑i.MX 6.

DDR3-SDRAM (U4-U7)

The RAM memory of the phyCORE‑i.MX 6 is comprised of one 64-bit wide bank with four 16-bit wide DDR3-SDRAM chips (U4-U7). The chips are connected to the special DDR interface called Multi-Mode DDR Controller (MMDC) of the i.MX 6 microcontroller.

The DDR3 memory is accessible starting at address 0x1000 0000.

Typically the DDR3-SDRAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the SDRAM must be initialized by accessing the appropriate SDRAM configuration registers on the i.MX 6 controller. Refer to the i.MX 6 Reference Manual for accessing and configuring these registers.

NAND Flash Memory (U12)

Use of Flash as non-volatile memory on the phyCORE‑i.MX 6 provides an easily reprogramm­able means of code storage.

The NAND Flash memory at U12 is connected to the General Purpose Media Interface (GPMI). Dependent on the memory size one or more of the chip enable signals NANDF_CS0, NANDF_CS1, NANDF_CS2 and NANDF_CS3 of the GPMI interface select the NAND Flash.

The Flash devices are programmable with 3.3 V. No dedicated programming voltage is required.

As of the printing of this manual these NAND Flash devices generally have a life expectancy of at least 100,000 erase/program cycles and a data retention rate of 10 years.

Any parts that are footprint (TSOP-48-50-C3) and functionally compatible may be used with the phyCORE-i.MX 6.

eMMC Flash Memory (U14)

Alternatively to the NAND flash memory at U12, an eMMC can be populated at U14.

The eMMC device is programmable with 3.3 V. No dedicated programming voltage is required.

The eMMC Flash memory is connected to the SD4 interface of the i.MX 6.

Any parts that are footprint (BGA153) and functionally compatible may be used with the phyCORE-i.MX 6.

I²C EEPROM (U11)

The phyCORE‑i.MX 6 is populated with a non-volatile 4 kB I²C^[13]EEPROM at U11. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I²C port 3 on the i.MX 6. The control registers for I²C port 3 are mapped between addresses 0x021A 8000 and 0x021A BFFF. Please see the i.MX 6 Reference Manual for detailed information on the registers.

The three lower address bits are fixed to zero which means that the EEPROM can be accessed at I²C address 0x50.

Write protection to the device is accomplished via jumper J4. Refer to EEPROM Write Protection Control (J4) for further details.

EEPROM Write Protection Control (J4)

Jumper J4 controls write access to the EEPROM (U11) device. Closing this jumper enables write access to the device, while removing this jumper will cause the EEPROM to enter write-protect mode, thereby disabling write access to the device.

The following configurations are possible:

SPI Flash Memory (U9)

The SPI Flash Memory of the phyCORE‑i.MX 6 at U9 can be used to store configuration data or any other general-purpose data. Besides this, it can also be used as a boot device^[14]and recovery boot device^[14]. The device is accessed through eCSPI1 SS1 on the i.MX 6. The control registers for eCSPI1 are mapped between addresses 0x0200 8000 and 0x0200 BFFF. Please see the i.MX 6 Reference Manual for detailed information on the registers.

The SPI Flash can be write-protected. The active-low signal SPI_NOR_nWP/GPIO1_12 connects to GPIO1_12 of the i.MX 6 allows control of the SPI Flash's write protection.

As of the printing of this manual these SPI Flash devices generally have a life expectancy of at least 100,000+ erase/program cycles and a data retention rate of 20 years. This makes the SPI Flash a reliable and secure solution to store the first and second-level bootloaders.

SD/MM Card Interfaces

The phyCORE bus features two SD/MM Card interfaces. On the phyCORE‑i.MX 6, the interface signals extend from the controller's third and first Ultra Secured Digital (uSDHC3 / uSDHC1) Host Controller to the phyCORE-Connector. Location of the SD/MM Card Interface Signals shows the location of the different interface signals on the phyCORE-Connector. The MMC/SD/SDIO Host Controller is fully compatible with the SD Memory Card Specification 3.0 and SD I/O Specification, Part E1, v1.10. SDC / MMC interface SD3 (uSDHC3 of the i.MX 6), supports 8 data channels and SD1 (uSDHC1 of the i.MX 6) 4 data channels. Both interfaces have a maximum data rate of up to 104 MB/s (refer to the i.MX 6Reference Manual for more information).

The interfaces do not provide dedicated card-detect or write-protect signals. The card detects and write-protect function can be implemented easily by using four GPIOs of the i.MX 6.

Serial Interfaces

The phyCORE‑i.MX 6 provides numerous dedicated serial interfaces some of which are equipped with a transceiver to allow direct connection to external devices:

1. 2x high-speed UARTs (TTL, derived from UART2 and UART3 of the i.MX 6) with up to 4 MHz and one with hardware flow control (RTS and CTS signals)
2. 1x High-speed USB OTG interface (extended directly from the i.MX 6’s USB OTG PHY (USBPHY1))
3. 1x High-speed USB HOST interface (extended directly from the i.MX 6 USB HOST PHY (USBPHY2))
4. 1x Auto-MDIX enabled 10/100/1000 Mbit Ethernet interface
5. 1x I²C interface (derived from I²C port 1 of the i.MX 6)
6. 2x Serial Peripheral Interface (SPI) interface (extended from the first and second SPI module (eCSPI1 and eCSPI2) of the i.MX 6)
7. 1x I²S audio interface (originating from the i.MX 6’s Synchronous Serial Interface (SSI) and muxed through port 5 of the Digital Audio Multiplexer (AUDMUX5))
8. 1x CAN 2.0B interface (extended directly from the i.MX 6 FlexCAN1 module)
9. 1x SATA II, 3.0 Gbps (extended directly from the i.MX 6 SATA PHY)
10. 1x PCI Express Gen. 2.0 (extended directly from the i.MX 6 PCIe PHY)

The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers.

Universal Asynchronous Interface

The phyCORE‑i.MX 6 provides two high-speed universal asynchronous interfaces with up to 4 MHz and one with additional hardware flow control (RTS and CTS signals). The following table shows the location of the signals on the phyCORE-Connector.

The signals extend from UART2 respectively UART3 of the i.MX 6 directly to the phyCORE-Connector without conversion to RS-232 level. External RS-232 transceivers must be attached by the user if RS-232 levels are required.

USB OTG Interface

The phyCORE‑i.MX 6 provides a high-speed USB OTG interface that uses the i.MX 6 embedded HS USB OTG PHY. An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for USB OTG) connector is all that is needed to interface the phyCORE‑i.MX 6 USB OTG functionality. The applicable interface signals can be found on the phyCORE‑Connector X1 as shown below.

USB Host Interface

The phyCORE‑i.MX 6 provides a high-speed USB host interface that uses the i.MX 6 embedded HS USB host PHY.

An external USB Standard-A (for USB host) connector is all that is needed to interface the phyCORE‑i.MX 6 USB host functionality. The applicable interface signals (D+/D- and VBUS) can be found on the phyCORE‑Connector X1.

If overcurrent and power enable signals are needed for the USB host interface, the functionality can be easily implemented with GPIOs.

Ethernet Interface

Connection of the phyCORE‑i.MX 6 to the world wide web or a local area network (LAN) is possible using the onboard GbE PHY at U2. It is connected to the RGMII interface of the i.MX 6. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s.

Alternatively, the RMII (ENET) interface which is available on the phyCORE‑Connector can be used to connect an external PHY. In this case, the onboard GbE PHY (U2) must not be populated (RMII Interface).

Ethernet PHY (U2)

With an Ethernet PHY mounted at U2, the phyCORE‑i.MX 6 has been designed for use in 10Base-T, 100Base-T, and 1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE‑Connector X1.

The on-board GbE PHY supports HP Auto-MDIX technology, eliminating the need for the consideration of a direct-connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an Auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface of the i.MX 6. Please refer to the i.MX 6 Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network adding an RJ45 connector and appropriate magnetic devices to your design is required. The required termination resistors on the analog signals (ETH0_A±, ETH0_B±, ETH0_C±, ETH0_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C- and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.

Software Reset of the Ethernet Controller

The Ethernet PHY at U2 can be reset by software. The reset input of the Ethernet PHY is permanently connected to pad SD2_DAT1 (GPIO1_14) of the i.MX 6.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the Internet, a table is used to convert the assigned IP number to the hardware’s MAC address.

In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 6 is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

RMII Interface

In order to use an external Ethernet PHY instead of the on-board GbE PHY at U2 the RMII interface (ENET) of the i.MX 6 is brought out at phyCORE‑Connector X1 as shown in Location of the RMII Interface Signals.

SPI Interface

The Serial Peripheral Interface (SPI) interface is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI interfaces on the phyCORE‑Connector X1. The SPI interfaces provide one respectively two chip select signals. The Enhanced Configurable SPI (eCSPI) of the i.MX 6 has five separate modules (eCSPI1, eCSPI2, eCSPI3, eCSPI4 and eCSPI5) which support data rates of up to 20 Mbit/s. The interface signals of the first and second modules (eCSPI1, eCSPI2) are made available on the phyCORE-Connector. These modules are master/slave configurable. The following table lists the SPI signals on the phyCORE-Connector.

I²C Interface

The Inter-Integrated Circuit (I²C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 6 contains three identical and independent Multimaster fast-mode I²C modules. The interface of the first module (I2C1) is available on the phyCORE-Connector.

The following table lists the I²C ports on the phyCORE-Connector.

The third I²C module (I2C3) connects to the on-board EEPROM (I2C EEPROM (U11)) and to the PMIC at U16 (Power Management IC (PMIC) (U16)). 

I²S Audio Interface (SSI)

The Synchronous Serial Interface (SSI) of the phyCORE‑i.MX 6 is a full-duplex serial interface that allows communication with a variety of serial devices, such as standard codecs, digital signal processors (DSPs), microprocessors, peripherals, and popular industry audio codecs that implement the Inter-IC sound bus standard (I²S) and Intel AC’97 standard. The i.MX 6 provides three instances of the SSI module. On the phyCORE‑i.MX 6 SSI is brought out to the phyCORE-Connector through port 5 of the i.MX 6's D

The main purpose of this interface is to connect to an external codec, such as I²S. The AUDMUX port is intended to be used in synchronous mode (4-wire interface). Hence, the receive data timing is determined by TXC and TXFS. The four signals extending from the i.MX 6 SSI module to the phyCORE-Connector are RXD, TXC, TXFS, and TXD.

CAN Interface

The CAN interface of the phyCORE‑i.MX 6 is connected to the first FlexCAN module (FlexCAN1) of the i.MX 6 which is a full implementation of the CAN protocol specification Version 2.0B. It supports standard and extended message frames and programmable bit rates of up to 1 Mb/s.

The following table shows the position of the signals on the phyCORE‑Connector.

SATA Interface

The SATA II interface of the phyCORE‑i.MX 6 is a high-speed serialized ATA data link interface compliant with SATA Revision 3.0 (physical layer complies with SATA Revision 2.5) which supports data rates of up to 3.0 Gbit/s. The interface includes an internal DMA engine, command layer, transport layer, link layer, and physical layer. The interface itself supports only one SATA device.

The phyCORE‑i.MX 6 provides a SATA II Interface at the following pins of the phyCORE‑Connector.

As the signals extend directly from the i.MX 6's SATA PHY a standard SATA connector is all that is needed to interface the phyCORE‑i.MX 6's SATA functionality.

PCI Express Interface

The 1-lane PCI Express interface of the phyCORE‑i.MX 6 provides PCIe Gen. 2.0 functionality which supports 5 Gbit/s operations. Furthermore, the interface is fully backward compatible with the 2.5 Gbit/s Gen. 1.1 specifications. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented with GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Mira i.MX 6) for a circuit example.

The table shows the position of the PCIe signals on the phyCORE‑Connector X1.

General Purpose I/Os

The table below lists all pins not used by any other of the interfaces described explicitly in this manual and which therefore can be used as GPIO without harming other features of the phyCORE‑i.MX 6.

Besides these pins, most of the i.MX 6 signals which are connected directly to the module connector can be configured to act as GPIO, due to the multiplexing functionality of most controller pins.

User-programmable LED

The phyCORE‑i.MX 6 provides one green user-programmable LED (D1) on board. It can be controlled by setting GPIO1_04 to the desired output level. A high-level turns the LED on, a low-level turns it off.

Debug Interface

The phyCORE‑i.MX 6 is equipped with a JTAG interface for downloading program code into the external flash, internal controller RAM, or for debugging programs currently executing.

The table below shows the location of the JTAG pins on the phyCORE-Connector X1.

Display Interfaces

Parallel Display Interface

The signals from the LCD interface of the i.MX 6 are brought out at phyCORE‑Connector X1. Thus an LCD interface with up to 24-bit bus width can be connected directly to the phyCORE‑i.MX 6. The table below shows the location of the applicable interface signals.

LVSD Display Interface

The LVDS-Signals from both channels of the on-chip LVDS Display Bridge (LDB) on the i.MX 6 are brought out at phyCORE‑Connector X1. Thus up to two LVDS-Displays, with up to four data lanes each, can be connected directly to the phyCORE‑i.MX 6. The location of the applicable interface signals can be found in the table below.

Supplementary Signals

In addition, signal X_PWM1_OUT can be used as PWM output to control the display brightness.

High-Definition Multimedia Interface (HDMI)

The High-Definition Multimedia Interface (HDMI) of the phyCORE‑i.MX 6 is compliant with HDMI 1.4 and DVI 1.0. It supports a maximum pixel clock of up to 340 MHz for up to 720p at 100 Hz and 720i at 200 Hz, or 1080p at 60 Hz and 1080i/720i at 120 Hz HDTV display resolutions and a graphic display resolution of up to 2048x1536 (QXGA). Please refer to the i.MX 6 Reference Manual for more information.

The following table shows the location of the HDMI signals on the phyCORE‑Connector.

As the signals extend directly from the i.MX 6's HDMI PHY a standard HDMI connector, a 5 V level shifter for the DDC and the CEC signals, and an optional ESD circuit protection device is all that are needed to interface the phyCORE‑i.MX 6's HDMI functionality.

Camera Interfaces

The phyCORE-i.MX 6 SOM offers various interfaces to connect digital cameras. Up to two parallel camera interfaces (IPU1_CSI0 and IPU2_CSI1^[15]), as well as the interface to the MIPI CSI-2 Host Controller, are supported and brought out in different ways. All signals (including control signals and an I²C interface) to use the camera interfaces according to PHYTEC's phyCAM‑S+, or phyCAM‑P standard are available at the phyCORE‑Connector.

The i.MX 6 (Solo), and i.MX 6 (DualLite) microcontrollers are equipped with one parallel camera port (IPU1_CSI0) and one image processing unit (version 3H) (IPU #1) to process the signals from the parallel, or the MIPI camera interface (Camera Connectivity of the i.MX 6 (Solo/DualLite)). The i.MX 6D (dual-core), and i.MX 6Q (quad-core) provides an additional parallel camera port (IPU2_CSI1) and a second image processing unit (IPU #2 ^[15](Camera Connectivity of the i.MX 6 (Dual-Core/Quad-Core)). The second, independent image processing unit of the i.MX 6D (dual-core), and the i.MX 6Q (quad-core) allows two cameras to operate at the same time.

On the phyCORE-i.MX 6 SOM camera port IPU1_CSI0 is brought out as parallel interfaces (Parallel 0) with 16 data bits, HSYNC, VSYNC, and PIXCLK. Camera port IPU2_CSI1 is also available as parallel interfaces (Parallel 1) with 20 data bits, HSYNC, VSYNC, and PIXCLK. The MIPI CSI-2 interface connects to the phyCORE‑Connector with four data lanes and one clock lane (Camera Interfaces at the phyCORE‑Connector (Parallel 0(CSI0 of IPU#1), Parallel 1(CSI1 of IPU#2), and MIPI CSI-2)).

The camera interfaces of the phyCORE‑i.MX 6 include all signals and are prepared to be used as phyCAM‑S(+), phyCAM‑P, or MIPI CSI-2 interface on an appropriate carrier board. Please refer to Utilizing the Camera Interfaces on a Carrier Board for more information on how to use the camera interfaces on a carrier board with different interface options.

Parallel 0 Camera Interface (CSIO of IPU#1)

The camera interfaces of the phyCORE‑i.MX 6 include all signals and are prepared to be used as phyCAM‑S(+), phyCAM‑P, or MIPI CSI-2 interface on an appropriate carrier board. Please refer to Utilizing the Camera Interfaces on a Carrier Board for more information on how to use the camera interfaces on a carrier board with different interface options.