L-875e.A0 phyCORE-STM32MP1 / phyBOARD-Sargas (1534.1/1517.2) Hardware Manual

Table of Contents

L-875e.A0 phyCORE-STM32MP1 / phyBOARD-Sargas (1534.1/1517.2) Hardware Manual
Document TitleL-875e.A0 phyCORE-STM32MP1 / phyBOARD-Sargas (1534.1/1517.2) Hardware Manual
Article NumberL-875e.A0
Release Date15.06.2020
SOM Prod. No.PCM-068
SOM PCB No.1534.1


SBC Prod. No.:PCM-939
CB PCB No.: 1517.2


Edition:June 2020

Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (™ or ®) and copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents and trademarks are similarly not expressly indicated in this manual.

The information in this document has been carefully checked and is considered to be entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result.

Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so.

@ Copyright 2020 PHYTEC Messtechnik GmbH, D-55129 Mainz.

Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH.

 

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Web Site:

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http://www.phytec.eu

http://www.phytec.com

http://www.phytec.fr

http://phytec.inhttp://www.phytec.cn

Conventions, Abbreviations, and Acronyms

This hardware manual describes the PCM-068 System on Module, referred to as phyCORE-STM32MP1, and the corresponding single-board computer PCM-939, the phyBOARD-Sargas STM32MP1. The manual specifies phyCORE-STM32MP1 and phyBOARD-Sargas's design and function. Precise specifications for the STMicroelectronics®  STM32MP1 microcontrollers can be found in the enclosed Microcontroller Data Sheet/User's Manual.

Note

We refrain from providing detailed, part-specific information within this manual (due to part maintenance for our products), which can be subject to continuous changes. Please read Product Change Management and Information Regarding Parts Populated on the SOM / Carrier Board within the Preface.

Note

The BSP delivered with the phyCORE®-STM32MP1 usually includes drivers and/or software for controlling all components such as interfaces, memory, etc. Programming close to hardware at the register level is not necessary in most cases. For this reason, this manual contains no detailed description of the controller's registers or information relevant to software development. Please refer to the STM32MP157C Reference Manual, if such information is needed to connect customer designed applications.

Conventions

The conventions used in this manual are as follows:

  • Signals that are preceded by an "n", "/", or “#” character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name are designated as active low signals. That is, their active state is when they are driven low or are driving low.
  • A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
  • The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the address byte. The correct value of the LSB which depends on the desired command (read (1), or write (0)) must be added to get the complete address byte. E.g.  given address in this manual 0x41 => complete address byte = 0x83 to read from the device and 0x82 to write to the device
  • Tables that describe jumper settings show the default position in bold,bluetext.
  • Text in blue italic indicates a hyperlink within, or external to the document. Click these links to quickly jump to the applicable URL, part, chapter, table, or figure.
  • References made to the phyCORE-Connector always refer to the high-density Samtec connector on the undersides of the phyCORE-STM32MP1 System on Module.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of a signal.

Signal Type

Description

Abbr.

Power

Supply voltage input

PWR_I

Power

Supply voltage output

PWR_O

Ref-Voltage

Reference voltage output

REF_O

Input

Digital input

I

Output

Digital output

O

IO

Bidirectional input/output

I/O

OC-Bidir PU

Open collector input/output with pull up

OC-BI

OC-Output

Open collector output without pull up requires an external pull up

OC

OD-Output

Open-drain output without pull up requires an external pull up

OD

5V Input PD

5 V tolerant input with a pull-down

5V_PD

LVDS Input

Differential line pairs 100 Ohm LVDS level input

LVDS_I

LVDS Output

Differential line pairs 100 Ohm LVDS level output

LVDS_O

TMDS Output

Differential line pairs 100 Ohm TMDS level output

TMDS_O

USB IO

Differential line pairs 90 Ohm USB level bidirectional input/output

USB_I/O

ETHERNET Input

Differential line pairs 100 Ohm Ethernet level input

ETH_I

ETHERNET Output

Differential line pairs 100 Ohm Ethernet level output

ETH_O

ETHERNET IO

Differential line pairs 100 Ohm Ethernet level bidirectional input/output

ETH_I/O

MIPI DSI Output

Differential line pairs 100 Ohm MIPI DSI level output

DSI_O

Signal Types

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use this table to navigate unfamiliar terms used in this document.

AbbreviationDefinition

BSP

Board Support Package (Software delivered with the Development Kit including an operating system (Windows, or Linux) preinstalled on the module and Development Tools).

CB

Carrier Board; used in reference to the phyCORE Development Kit Carrier Board.

DFF

D flip-flop.

EMB

External memory bus.

EMI

Electromagnetic Interference.

GPI

General-purpose input.

GPIO

General-purpose input and output.

GPO

General-purpose output.

IRAM

Internal RAM; the internal static RAM on the STMicroelectronics® STM32MP1 microcontroller.

J

Solder jumper; these types of jumpers require solder equipment to remove and place.

JP

Solderless jumper; these types of jumpers can be removed and placed by hand with no special tools.

PCB

Printed circuit board.

PDI

PHYTEC Display Interface; defined to connect PHYTEC display adapter boards, or custom adapters

PEB

PHYTEC Extension Board

PMIC

Power management IC

PoE

Power over Ethernet

POR

Power-on reset

RTC

Real-time clock.

SMT

Surface mount technology.

SOM

System on Module; used in reference to the PCM-068 /phyCORE®-STM32MP1 module

Sx

User button Sx (e.g. S1, S2, etc.) used in reference to the available user buttons, or DIP-Switches on the carrier board.

Sx_y

Switch y of DIP-Switch Sx; used in reference to the DIP-Switch on the carrier board.

Abbreviations and Acronyms

Preface

As a member of PHYTEC's phyCORE® product family, the phyCORE‑STM32MP1 is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers and, therefore, offers various functions and configurations. PHYTEC supports a variety of 8/16/32/64 bit controllers in two ways:

(1)     As the basis for Rapid Development Kits which serve as a reference and evaluation platform

(2)     As insert-ready, fully functional phyCORE® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "re-invent" microcontroller circuitry. Furthermore, much of the value of the phyCORE® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative full system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html

or

http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Ordering Information

The part numbering of the phyCORE has the following structure:

Ordering Information

Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our web site which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
https://www.phytec.de/produkt/system-on-modules/phycore-stm32mp1/ 
or
https://www.phytec.eu/product-eu/system-on-modules/phycore-stm32mp1/

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑STM32MP1 

PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

Warning

PHYTEC products lacking protective enclosures are subject to damage by ESD and, therefore, must be unpacked, handled, or operated in environments in which sufficient precautionary measures have been taken with respect to ESD-dangers. It is also necessary that only appropriately trained personnel (such as electricians, technicians, and engineers) handle and/or operate these products. Moreover, PHYTEC products should not be operated without protection circuitry if connections to the product's pin header rows are longer than 3 m.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity only in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector and serial interface to a host-PC).

Implementation of PHYTEC products into target devices, as well as user modifications and extensions of PHYTEC products, is subject to renewed establishment of conformity to, and certification of, Electro Magnetic Directives. Users should ensure conformance following any modifications to the products as well as the implementation of the products into target systems.

Product Change Management and Information Regarding Parts Populated on the SOM / Carrier Board

With the purchase of a PHYTEC SOM / Carrier Board, you will, in addition to our HW and SW offerings, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) Team of developers, is continuously processing, all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts that are used in our products.

Possible impacts on the functionality of our products, due to changes in functionality or obsolesce of a certain part, are constantly being evaluated in order to take the right measures in purchasing or within our hardware/software design.

Our general philosophy here is: We never discontinue a product as long as there is a demand for it.

Therefore, we have established a set of methods to fulfill our philosophy:

Avoiding strategies:

  • Avoid changes by evaluating the longevity of parts during the design-in phase.
  • Ensure the availability of equivalent second source parts.
  • Stay in close contact with part vendors to be aware of roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

  • Ensure long term availability by stocking parts through last time buy management according to product forecasts.
  • Offer long term frame contracts to customers.

Change management in case of functional changes:

  • Avoid impacts on product functionality by choosing equivalent replacement parts.
  • Avoid impacts on product functionality by compensating changes through HW redesign or backward-compatible SW maintenance.
  • Provide early change notifications concerning functional relevant changes to our products.

Therefore, we refrain from providing detailed part specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

  • QS Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a BSP, the device tree, and accessing peripherals.
  • Hardware Manual:  A detailed description of the System on Module and accompanying carrier board. 
  • Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; an introduction, installing and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
  • BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
  • Development Environment Guide:  This guide shows how to work with the pre-programmed programs Eclipse and Qt Creator. It includes instructions for running demo projects for these programs on a phyCORE product. Information on how to set up a Linux host PC is also included.
  • Pin Muxing Table:  Starting in 2019, all phyCORE SOMs will have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case by case basis. All documentation can be found in the applicable download page of our products.

phyCORE-STM32MP1 Introduction

The phyCORE‑STM32MP1 belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of the PHYTEC System on Module technology. Like its mini-, micro-, and nano MODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a sub-miniature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all EMI (Electro-Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which provides for the dedication of approximately 20 % of all connector pinson the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high noise environments.

phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In accordance with the complexity of the module, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design.

The phyCORE‑STM32MP1 is a sub-miniature (40 mm x 44 mm) insert-ready System on Module populated with the STMicroelectronics®  STM32MP1 microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch, or surface mount technology (SMT) connectors (all pitch 0.5 mm) aligning two sides of the board, allowing it to be plugged or soldered into any target application like a "big chip"

The descriptions in this manual are based on the STMicroelectronics STM32MP157C. No description of compatible microcontroller derivative functions is included as such functions are not relevant for the basic functioning of the phyCORE‑STM32MP1. Precise specifications for the controller populating the board can be found in the applicable controller Technical Reference Manual or datasheet.

Note

Most of the controller pins have multiple multiplexed functions. As most of these pins are connected directly to the phyCORE-Connector, the alternative functions are available by using the STM32MP1's pin muxing options. However, the following list of features is in regard to the specification of the phyCORE‑STM32MP1 and the functions defined therein. Therefore, theindicatednumberofcertaininterfaces,CSsignals,etc.isperhapssmallerthanavailableonthecontroller. Please refer to the STM32MP157C Reference Manual to learn more about alternative functions. In order to utilize a specific pin's alternative function, the corresponding registers and the device tree must be configured within the appropriate driver of the BSP.

Tip

STMicroelectronics provides software for pin muxing. For further information about the pin muxing tool, refer to STM32CubeMX.

phyCORE-STM32MP1 Features

The phyCORE‑STM32MP1 offers the following features:

  • Insert-ready, sub-miniature (44 mm x 40 mm) System on Module (SOM) sub-assembly in low EMI design, achieved through advanced SMT technology
  • Populated with the STMicroelectronics® STM32MP157C[1]microcontroller (TFBGA361 packaging)

  • Up to 2 ARM-Cortex-A7 cores (clock frequency up to 800 MHz) + ARM-Cortex-M4 core up to 209 MHz
  • Boot from different memory devices (SD card, QSPI NOR-Flash, NAND-Flash, eMMC)
  • Controller signals and ports extend to two high-density pitch (0.5 mm) Samtec connectors aligning two sides of the board, enabling the phyCORE-STM32MP1 to be plugged into any target applications like a "big chip"
  • Single supply voltage of +5.0 V with on-board power management
  • All controller required supplies are generated on-board
  • Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins
  • 256 MB (up to 1 GB[2]) 32-bit wide DDR3L RAM

  • 4 GB (up to 32 GB[2]) on-board eMMC, or 128 MB (up to 1 GB[2]) on-board SLC NAND flash
  • 4 MB (up to 16 MB[2]) Quad SPI NOR flash  (bootable)
  • 4 kB[2] (up to 32 kB[2]) I2C EEPROM
  • Three UART interfaces
  • Two High-speed USB 2.0 interfaces (1 x USB host and 1 x USB OTG)
  • 10/100/1000 Mbit/s Ethernet interface. Either with Ethernet transceiver on the phyCORE-STM32MP1 allowing for direct connection to an existing Ethernet network or without on-board transceiver and provision of the RGMII signals at TTL-level (10/100/1000 Mbit/sat the phyCORE-Connector instead[1]
  • Two I2C interfaces
  • Two SPI interfaces (one QSPI, one SPI, up to 6 /or 3x I2S from STM32MP1)
  • One CAN FD interface
  • One MIPI DSI interface
  • One Parallel 18-bit RGB display interface with HDMI-CEC
  • One 10-bit parallel camera interface
  • One SAI Audio interface
  • One MDIO interface
  • Several dedicated GPIOs[3]

  • Several AD conversion and filter inputs digital (DFSDM)
  • Two 12-bit DAC outputs
  • One JTAG/Serial-wire debug interface with trace ports and debug trigger I/Os
  • I2C Real-Time Clock[1]with a very low-power operation, independent from CPU-supply

Warning

Samtec connectors guarantee optimal connection and proper insertion of the phyCORESTM32MP1. Please make sure that the STM32MP1 module is fully plugged into the mating connectors of the carrier board. Otherwise, individual signals may have bad contact or no contact at all.

1.

Please refer to the order options described in the Preface or contact PHYTEC for more information about additional modules configurations.

2.

The maximum memory size listed as of the printing of this manual. Please contact PHYTEC for more information about additional or new module configurations available.

3.

Almost every controller port that connects directly to the phyCORE-Connector may be used as GPIO by using the STM32MP1's pin muxing options.

phyCORE-STM32MP1 Block Diagram

 phyCORE-STM32MP1 Block Diagram

phyCORE-STM32MP1 Block Diagram

phyCORE-STM32MP1 Component Placement

  

phyCORE-STM32MP1 Component Placement (Top View)

phyCORE-STM32MP1 Component Placement (Bottom View)

phyCORE-STM32MP1 Component Placement (Bottom View)

phyCORE-STM32MP1 Minimum Operating Requirements

Warning

We recommend connecting all available +5 V input pins to the power supply system on a custom carrier board housing the phyCORE-STM32MP1 and, at minimum, the matching number of GND balls neighboring the +5 V balls. In addition, proper implementation of the phyCORE-STM32MP1 module into a target application also requires connecting all GND pins. Refer to section Power for more information.

Pin Description

Warning

Module connections must not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller manuals/datasheets. As damage from improper connections varies according to use and application, it is the user's responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals. 

As the image Pinout of the phyCORE-Connector indicates, all controller signals selected extend to surface mount technology (SMT) connectors (0.5 mm). These connectors line two sides of the module (referred to as phyCORE-Connectors). This enables the phyCORE‑STM32MP1 to be plugged into any target application like a "big chip".

The numbered scheme for the phyCORE‑Connector is based on a two-dimensional matrix in which column positions are identified by a letter and row position by a number. The pin numbering values increase as you move across the board from left to right. The numbered matrix can be aligned with the phyCORE‑STM32MP1 (viewed from above; phyCORE‑Connector pointing down) or with the socket of the corresponding phyCORE carrier board/user target circuitry. The upper left-hand corner of the numbered matrix (pin X1A1) is covered by the corner of the phyCORE‑STM32MP1. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.

The numbering scheme is consistent for both the module's phyCORE‑Connector as well as the mating connector on the phyCORE carrier board or target application. This reduces the risk of pin identification errors considerably.

Since the pins are precisely defined according to the numbered matrix described above, the phyCORE‑Connector is usually assigned a single designator for its position (X1 for example). This way, the phyCORE‑Connector comprises a single, logical unit regardless of the fact that it could consist of more than one physically socketed connector.

The following figure illustrates the numbered matrix system. It shows a phyCORE‑STM32MP1 with SMT phyCORE‑Connectors on its underside (defined with dotted lines) as it would be mounted on a carrier board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a cross-view of the phyCORE module showing these phyCORE‑Connectors mounted on the underside of the module’s PCB.

Pinout of the phyCORE-Connector (top view)

The Pinout table below provides an overview of the pinout of the phyCORE‑Connector X1 with signal names and descriptions specific to the phyCORE‑STM32MP1.  It also provides the appropriate signal level interface voltages listed in the (Signal) Level column, (Signal) Type, as well as information regarding the controller pin. The signal type includes also information about the signal direction.[4]A description of the signal types can be found in the table Signal Types.

In addition to the table below, PHYTEC provides a complete pinout table for the phyCORE‑STM32MP1 and PHYTEC carrier board as a downloadable Excel file (phyCORE-STM32MP1_Pinout_Table.A0_public.xls). This table includes signal names, pin muxing paths, and descriptions specific to the phyCORESTM32MP1 and the phyBOARDSargas. It also provides the appropriate signal type, a functional grouping of the signals, and information about the signal direction. A table describing the signal types can be found on a second tab in the Excel file.

4. 1

The specified direction indicated refers to the standard phyCORE use of the pin.

Warning

  • The STMicroelectronics® STM32MP1 is a multi-voltage operated microcontroller and, as such, special attention should be paid to the interface voltage levels to avoid unintentional damage to the microcontroller and other on-board components. Please refer to the STMicroelectronics STM32MP15x Reference Manual for details on the functions and features of controller signals and port pins.
  • The phyCORE-STM32MP1 has three dedicated boot signals which are brought out on the phyCORE-Connector and are used to configure specific boot options. Please make sure that these signals are not driven by any device on the baseboard during reset. The signals which may affect the boot configuration described in section Boot Mode Selection.
  • It is necessary to avoid voltages at the IO pins of the phyCORE-STM32MP1 which are sourced from the supply voltage of peripheral devices attached to the SOM during power-up or power-down. These voltages can cause a current flow into the controller, especially if peripheral devices attached to the interfaces of the STM32MP1 are supposed to be powered while the phyCORE‑STM32MP1 is in suspend mode or turned off. To avoid this, bus switches either supplied by VDD (3.3 V) on the phyCORE side or having their output enabled to the SOM controlled by the VDD signal, must be used (seeSupply Voltage for External Logic).

Tips

  • Most of the controller pins have multiple, multiplexed functions. As most of these pins are connected directly to the phyCORE-Connector, the alternative functions are available by using the STM32MP1's pin muxing options. Signal names and descriptions in the accompanying table, however, are in regard to the specification of the phyCORE‑STM32MP1 and the functions defined. Please refer to the STMicroelectronics STM32MP15x Reference Manual or the schematic to get to know about alternative functions. In order to utilize a specific pin's alternative function, the corresponding registers must be configured within the appropriate driver of the BSP.
  • The following tables describe the full set of signals available at the phyCORE‑Connector according to the phyCORE-STM32MP1 specification. However, the availability of some interfaces is order-specific (e.g. SDMMC2, RGMII). This means some signals might not be available on your module.
  • If the phyCORE-STM32MP1 is delivered with the carrier board, the pin muxing might be changed within the appropriate BSP in order to support all features of the carrier board. If so, information on the differences from the pinout given in the following tables can be found in the carrier board's documentation (see phyCORE-STM32MP1 on the phyBOARD-Sargas).

Pin No.Signal NameLevelTypePin NameBGA361-PadDescription
A1X_MIPI_DSI_CLKN1.2 VDSI_ODSI_CKNA16MIPI DSI clock negative output
A2X_MIPI_DSI_CLKP1.2 VDSI_ODSI_CKPB16MIPI DSI clock positive output
A3GND




A4X_MIPI_DSI_DATA0N1.2 VDSI_ODSI_D0NB15MIPI DSI data0 negative output
A5X_MIPI_DSI_DATA0P1.2 VDSI_ODSI_D0PC15MIPI DSI data0 positive output
A6GND




A7X_MIPI_DSI_DATA1N1.2 VDSI_ODSI_D1NA17MIPI DSI data1 negative output
A8X_MIPI_DSI_DATA1P1.2 VDSI_ODSI_D1PB17MIPI DSI data1 positive output
A9X_MIPI_DSIHOST_TE/PD133.3 VIPD13AA19MIPI DSI tearing effect input
A10GND




A11X_SDMMC2_DATA0/PB143.3 VI/OPB14C13SD/SDIO/eMMC card data line 0
A12X_SDMMC2_DATA1/PB153.3 VI/OPB15B12SD/SDIO/eMMC card data line 1
A13X_SDMMC2_DATA2/PB33.3 VI/OPB3A11SD/SDIO/eMMC card data line 2
A14X_SDMMC2_DATA3/PB43.3 VI/OPB4B13SD/SDIO/eMMC card data line 3
A15X_SDMMC2_DATA4/PA83.3 VI/OPA8A13SD/SDIO/eMMC card data line 4
A16X_SDMMC2_DATA5/PA93.3 VI/OPA9A8SD/SDIO/eMMC card data line 5
A17X_SDMMC2_DATA6/PC63.3 VI/OPC6B14SD/SDIO/eMMC card data line 6
A18X_SDMMC2_DATA7/PD33.3 VI/OPD3D14SD/SDIO/eMMC card data line 7
A19GND




A20X_SDMMC2_CMD/PG63.3 VI/OPG6A10SD/SDIO/eMMC card bidirectional command/response signal
A21X_SDMMC2_CLK/PE33.3 VOPE3C9SD/SDIO/eMMC card clock
A22GND




A23X_SDMMC3_D0/PF03.3 VI/OPF0D8SDIO SDMMC3 interface
A24X_SDMMC3_D1/PF43.3 VI/OPF4D9
A25X_SDMMC3_D2/PF53.3 VI/OPF5D7
A26X_SDMMC3_D3/PD73.3 VI/OPD7D10
A27X_SDMMC3_CMD/PF13.3 VI/OPF1A5
A28X_SDMMC3_CK/PG153.3 VOPG15B7
A29GND




A30X_DCMI_HSYNC/PH83.3 VIPH8D5DCMI Horizontal synchronization / Data valid
A31X_DCMI_VSYNC/PB73.3 VIPB7D11DCMI Vertical synchronization
A32X_DCMI_PIXCLK/PA63.3 VIPA6AC8DCM Pixel clock
A33GND




A34X_DCMI_DATA5/PI43.3 VIPI4E4DCMI data5
A35X_DCMI_DATA6/PE53.3 VIPE5C11DCMI data6
A36X_DCMI_DATA7/PI73.3 VIPI7F2DCMI data7
A37X_DCMI_DATA8/PI13.3 VIPI1E3DCMI data8
A38X_DCMI_DATA9/PH73.3 VIPH7W4DCMI data9
A39GND




A40X_LCD_R2/PC103.3 VOPC10D15LCD data red2
A41X_LCD_R3/PB03.3 VOPB0AB6LCD data red3
A42X_LCD_R4/PH103.3 VOPH10C2LCD data red4
A43X_LCD_R5/PH113.3 VOPH11C4LCD data red5
A44X_LCD_R6/PH123.3 VOPH12B2LCD data red6
A45X_LCD_R7/PE153.3 VOPE15D3LCD data red7
A46GND




A47X_LCD_G2/PH133.3 VOPH13D1LCD data green2
A48X_LCD_G3/PE113.3 VOPE11A4LCD data green3
A49X_LCD_G4/PH153.3 VOPH15B1LCD data green4
A50X_LCD_G5/PH43.3 VOPH4B3LCD data green5
A51X_LCD_G6/PI113.3 VOPI11P4LCD data green6
A52X_LCD_G7/PI23.3 VOPI2E2LCD data green7
A53GND




A54X_UART4_RX/PB23.3 VIPB2Y16UART4 serial data receive signal
A55X_USART1_TX/PZ73.3 VOPZ7J3USART1 serial data transmit signal
A56X_SPI16_MOSI/PZ23.3 VI/OPZ2Z2SPI1 master output/slave input
A57X_SPI16_NSS/PZ33.3 VI/OPZ3G4SPI1 slave select (active low)
A58X_LCD_BL_PWM/PI03.3 VOPI0C1PWM output (e.g. to control the brightness)
A59X_PI33.3 VI/OPI3E1GPIO PI3 (LCD Touch-IRQn in)
A60X_PD93.3 VI/OPD9K1GPIO PD9 (LCD Reset out)
Pin No.Signal NameLevelTypePin NameBGA361-PadDescription
B1GND




B2X_JTAG_nTRST3.3 VINJTRSTB19JTAG test reset (active low)
B3X_JTAG_TDI3.3 VIJTDIA20JTAG test data input
B4X_JTAG_TMS/SWDIO3.3 VI / I/OJTMS-SWDIOC20JTAG test mode select / Serial wire data in/out
B5X_JTAG_TCK/SWCLK3.3 VIJTCK-SWCLKB20JTAG test clock / Serial wire clock
B6X_JTAG_TDO/TRACESWO3.3 VOJTDO-TRACESWOA19

JTAG test data output / Trace asynchronous data out

B7GND




B8X_SDMMC1_D0/PC83.3 VI/OPC8D18SDMMC1 interface normally used for external SD-Card (boot option)
B9X_SDMMC1_D1/PC93.3 VI/OPC9D17
B10X_SDMMC1_D2/PE63.3 VI/OPE6C10
B11X_SDMMC1_D3/PC113.3 VI/OPC11D16
B12X_SDMMC1_CMD/PD23.3 VI/OPD2D12
B13GND




B14X_SDMMC1_CK/PC123.3 VOPC12D13SDMMC1 interface clock out
B15X_SDMMC1_CKIN/PE43.3 VIPE4D19SDMMC1 clock feedback in
B16X_SDMMC1_CDIR/PB93.3 VOPB9B10UART4 TXD
B17X_SDMMC1_D0DIR/PF23.3 VOPF2A14SDMMC1 dat0 direction out
B18X_SDMMC1_D123DIR/PE143.3 VOPE14C6SDMMC1 dat123 direction out
B19GND




B20X_FMC_DATA0/PD143.3 VI/OPD14L3Address / Data 0
B21X_FMC_DATA1/PD153.3 VI/OPD15J2Address / Data 1
B22X_FMC_DATA2/PD03.3 VI/OPD0B8Address / Data 2
B23X_FMC_DATA3/PD13.3 VI/OPD1B9Address / Data 3
B24X_FMC_DATA4/PE73.3 VI/OPE7AA11Address / Data 4
B25X_FMC_DATA5/PE83.3 VI/OPE8AC13Address / Data 5
B26X_FMC_DATA6/PE93.3 VI/OPE9AA9Address / Data 6
B27X_FMC_DATA7/PE103.3 VI/OPE10Y15Address / Data 7
B28GND




B29X_FMC_nWAIT/PD63.3 VIPD6D2Input for external ready/busy (wait) signal (active low)
B30X_FMC_nOE/PD43.3 VOPD4B6Output enable/ Read enable (active low)
B31X_FMC_nCE/PG93.3 VOPG9Y13Chip select 1
B32X_FMC_CLE/PD113.3 VOPD11AC10Command latch enable
B33X_FMC_ALE/PD123.3 VOPD12Y18Address latch enable
B34X_FMC_nNWE/PD53.3 VOPD5A7Write enable (active low)
B35GND




B36X_DCMI_DATA0/PH93.3 VIPH9C5DCMI data0
B37X_DCMI_DATA1/PC73.3 VIPC7B11DCMI data1
B38X_DCMI_DATA2/PE03.3 VIPE0D6DCMI data2
B39X_DCMI_DATA3/PE13.3 VIPE1C8DCMI data3
B40X_DCMI_DATA4/PH143.3 VIPH14C3DCMI data4
B41GND




B42X_LCD_B2/PG103.3 VOPG10AB11LCD data blue2
B43X_LCD_B3/PG113.3 VOPG11Y7LCD data blue3
B44X_LCD_B4/PE123.3 VOPE12B4LCD data blue4
B45X_LCD_B5/PI53.3 VOPI5F3LCD data blue5
B46X_LCD_B6/PB83.3 VOPB8AB10LCD data blue6
B47X_LCD_B7/PD83.3 VOPD8K3LCD data blue7
B48GND




B49X_LCD_HSYNC/PI103.3 VOPI10T1LCD horizontal sync
B50X_LCD_VSYNC/PI93.3 VOPI9H4LCD vertical sync
B51X_LCD_DE/PE133.3 VOPE13A3LCD data enable
B52X_LCD_CLK/PG73.3 VOPG7AC14LCD clock
B53GND




B54X_SPI16_SCK/PZ03.3 VI/OPZ0G3SPI1 clock signal
B55X_USART1_RX/PZ63.3 VIPZ6H1USART1 RXD serial data receive signal
B56X_SPI16_MISO/PZ13.3 VI/OPZ1G1SPI1 master input/slave output
B57X_SPI1_MOSI/PB53.3 VIPB5Y8CAN FD2 serial data receive signal
B58X_SPI1_NSS/PA153.3 VI/OPA15C19HDMI-CEC
B59GND




B60X_PI83.3 VI/OPI8L4GPIO PI8
Pin No.Signal NameLevelTypePin NameBGA361-PadDescription
C1X_FDCAN1_RX/PA113.3 VIPA11AA18CAN FD1 serial data receive signal
C2X_FDCAN1_TX/PA123.3 VOPA12AB19CAN FD1 serial data transmit signal
C3GND




C4X_QSPI_BK1_DATA0/PF83.3 VI/OPF8AC11QSPI Bidirectional IO0
C5X_QSPI_BK1_DATA1/PF93.3 VI/OPF9AA14QSPI Bidirectional IO1
C6X_QSPI_BK1_DATA2/PF73.3 VI/OPF7AB12QSPI Bidirectional IO2
C7X_QSPI_BK1_DATA3/PF63.3 VI/OPF6AA13QSPI Bidirectional IO3
C8X_QSPI_BK1_nCS/PB63.3 VOPB6Y14QSPI chip select for bank 1 (low active)
C9X_QSPI_CLK/PF103.3 VOPF10Y12QSPI clock signal
C10GND




C11X_ADC1_INN10 V - VREFANA_IANA0U3ADC1 IN1-
C12X_ADC1_INP10 V - VREFANA_IANA1U4ADC1 IN1+
C13X_ADC1_INN2/PF120 V - VREFANA_IPF12Y9ADC1 IN2-
C14X_PVD_IN/ADC1_INN15/PA30 V - VREFANA_IPA3U2ADC1 IN15-
C15VREF1.8 V - VDDAPWR_I
R4Analog Reference in/out
C16X_DACOUT1/PA40 V - VREFANA_OPA4V4DAC OUT1
C17X_DACOUT2/PA50 V - VREFANA_OPA5V3DAC OUT2
C18GND




C19X_BOOT03.3 V5V_PDBOOT0N1BOOT0 config in
C20X_BOOT13.3 V5V_PDBOOT1N4BOOT1 config in
C21X_BOOT23.3 V5V_PDBOOT2M2BOOT2 config in
C22GND




C23X_DFSDM1_DATIN0/PG03.3 VIPG0AC2DFSDM1 data0 in
C24X_DFSDM1_DATIN1/PC33.3 VIPC3W2DFSDM1 data1 in
C25X_DFSDM1_DATIN3/PF133.3 VIPF13Y5DFSDM1 data2 in
C26X_DFSDM1_CKIN1/PG33.3 VIPG3T4DFSDM1 clock in
C27X_DFSDM1_CKOUT/PD103.3 VOPD10B5DFSDM1 clock out
C28GND




C29X_ETH1_RGMII_RXD0/PC43.3 VIPC4AC7ETH1 RGMII receive data 0
C30X_ETH1_RGMII_RXD1/PC53.3 VIPC5AB7ETH1 RGMII receive data 1
C31X_ETH1_RGMII_RXD2/PH63.3 VIPH6Y11ETH1 RGMII receive data 2
C32X_ETH1_RGMII_RXD3/PB13.3 VIPB1AA7ETH1 RGMII receive data 3
C33X_ETH1_RGMII_RX_CTL/PA73.3 VIPA7AB8ETH1 RGMII receive control (RX_DV + RX_ER)
C34X_ETH1_RGMII_RX_CLK/PA13.3 VIPA1AA4ETH1 RGMII receive clock
C35GND




C36X_ETH1_RGMII_TXD0/PG133.3 VOPG13AA2ETH1 RGMII transmit data 0
C37X_ETH1_RGMII_TXD1/PG143.3 VOPG14AA1ETH1 RGMII transmit data 1
C38X_ETH1_RGMII_TXD2/PC23.3 VOPC2Y2ETH1 RGMII transmit data 2
C39X_ETH1_RGMII_TXD3/PE23.3 VOPE2Y1ETH1 RGMII transmit data 3
C40X_ETH1_RGMII_TX_CTL/PB113.3 VI/OPB11AB1ETH1 RGMII transmit control (TX_EN + TX_ER)
C41X_ETH1_RGMII_GTX_CLK/PG43.3 VOPG4AB2ETH RGMII transmit clock
C42GND




C43X_ETH1_MDC/PC13.3 VOPC1AA6Ethernet management data clock
C44X_ETH1_MDIO/PA23.3 VI/OPA2AC3Ethernet management data I/O
C45X_ETH1_nINT/PG123.3 VIPG12K4Ethernet interrupt  (low active)
C46X_ETH1_RGMII_CLK125/PG53.3 VIPG5Y6External clock RX provided by the Ethernet PHY
C47GND




C48X_RTC_EVI3.3 VI-PDRTC_EVI
RTC external event input; 10 kΩ pull-down
C49X_nRTC_INT3.3 VODRTC_INTn
RTC interrupt output; open-drain; active low
C50X_RTC_CLKOUT3.3 VORTC_CLKO
RTC Clock output
C51X_PWR_ON3.3 VOPWR_ONR2Power-ON output
C52VBUS_SW5.0 VPWR_OPMIC-SWOUT
5 V / 500 mA USB-host power out
C53VBUS_OTG5.0 VPWR_OPMIC-VBUSOTG
5 V / 500 mA USB-OTG power out
C54GND




C55VDD_BUCK43.3 VPWR_OPMIC-BUCK4
3.3 V / 1 A PMIC-BUCK4 out
C56VDD_BUCK43.3 VPWR_OPMIC-BUCK4
3.3 V / 1 A PMIC-BUCK4 out
C57GND




C58VCC5V_IN5.0 VPWR_IPMIC-VIN
5 V main supply voltage
C59VCC5V_IN5.0 VPWR_IPMIC-VIN
5 V main supply voltage
C60VCC5V_IN5.0 VPWR_IPMIC-VIN
5 V main supply voltage
Pin No.Signal NameLevelTypePin NameBGA361-PadDescription
D1GND




D2X_USB_OTG_VBUS5.0 VPWR_IOTG_VBUSAC19USB OTG VBUS input
D3X_USB_OTG_D2P3.3 VUSB_I/OUSB_DP2AC16USB OTG data plus
D4X_USB_OTG_D2M3.3 VUSB_I/OUSB_DM2AB16USB OTG data minus
D5GND




D6X_USB_HOST_D1M3.3 VUSB_I/OUSB_DM1AB17USB host data minus
D7X_USB_HOST_D1P3.3 VUSB_I/OUSB_DP1AC17USB OTG data plus
D8X_USB_OTG_ID/PA103.3 VIPA10Y17USB OTG ID Pin
D9GND




D10X_USART3_RX/PB123.3 VIPB12AC5USART3 RXD in
D11X_USART3_TX/PB103.3 VOPB10Y3USART3 TXD out
D12X_USART3_RTS/PG83.3 VOPG8AB9USART3 RTS out
D13X_USART3_CTS/PB133.3 VIPB13AA10USART3 CTS in  / CAN FD2 RXD
D14GND




D15X_SAI2_SD_A/PI63.3 VI/OPI6F4SAI2 SDA
D16X_SAI2_SD_B/PF113.3 VI/OPF11Y10SAI2 SDB
D17X_SAI2_SCK_B/PH23.3 VI/OPH2AB4SAI2 SCKB
D18X_SAI2_MCLK_B/PH33.3 VI/O-OPH3AA3SAI2 MCLKB
D19X_SAI2_FS_B/PC03.3 VI/OPC0AB5SAI2 FSB
D20GND




D21X_I2C4_SCL/PZ43.3 VOPZ4G2I2C4 used for internal I2C devices
D22X_I2C4_SDA/PZ53.3 VI/OPZ5H2
D23X_I2C1_SCL/PF143.3 VI/OPF14AC4I2C1 SCL out
D24X_I2C1_SDA/PF153.3 VI/OPF15Y4I2C1 SDA I/O
D25X_I2C2_SDA/PH53.3 VI/OPH5A2GPIO PH5
D26GND




D27X_DBTRGI/PA143.3 VIPA14T2External trigger input to the cross trigger interface (CTI)
D28X_DBTRGO/PA133.3 VOPA13N2External trigger output from the cross trigger interface (CTI)
D29GND




D30X_ETH_A+3.3 VETH_I/OETH-PHY
Ethernet data A+
D31X_ETH_A-3.3 VETH_I/OETH-PHY
Ethernet data A-
D32GND




D33X_ETH_B+3.3 VETH_I/OETH-PHY
Ethernet data B+
D34X_ETH_B-3.3 VETH_I/OETH-PHY
Ethernet data B-
D35GND




D36X_ETH_C+3.3 VETH_I/OETH-PHY
Ethernet data C+
D37X_ETH_C-3.3 VETH_I/OETH-PHY
Ethernet data C-
D38GND




D39X_ETH_D+3.3 VETH_I/OETH-PHY
Ethernet data D+
D40X_ETH_D-3.3 VETH_I/OETH-PHY
Ethernet data D-
D41GND




D42X_ETH_LED0_LINK3.3 VODETH-PHY_LED0
Ethernet link LED output
D43X_ETH_LED1_GBIT3.3 VODETH-PHY_LED1
Ethernet Gb indication LED output
D44X_ETH_LED2_ACT3.3 VODETH-PHY_LED2
Ethernet traffic LED output
D45X_ETH_GPIO03.3 VI/OETH-PHY_GPIO0
Ethernet PHY GPIO0 (Ethernet PHY (U3))
D46X_ETH_GPIO13.3 VI/OETH-PHY_GPIO1
Ethernet PHY GPIO1 (Ethernet PHY (U3))
D47X_PG13.3 VI/OPG1W1GPIO PG1
D48X_PF33.3 VI/OPF3U1GPIO PF3
D49X_MCO2/PG23.3 VOPG2V2Master clock out
D50GND




D51X_nRESET3.3 VI/O-ODNRSTM3Reset in/out open drain with 10 kΩ pull-up 
D52X_nPMIC_INT/PA03.3 VIPA0AB3Input for interrupt from PMIC or external
D53X_WAKEUP3/PC133.3 VI/OPC13K2GPIO PC13 (PMIC-Wakeup in)
D54X_nPONKEY3.3 VIPMIC-PONKEYn
PMIC power-on key (active low)
D55VDD_LDO1
PWR_OPMIC-LDO1
PMIC-LDO1 programmable output
D56VDD3.3 VPWR_OVDD
3.3 V VDD out (only for reference)
D57VBAT1.8 V - 3.6 VPWR_IRTC_VBKUP
1.8 V to 3.6 V backup supply
D58GND




D59VCC5V_IN5.0 VPWR_IPMIC-VIN
5 V main supply voltage
D60VCC5V_IN5.0 VPWR_IPMIC-VIN
5 V main supply voltage

Pinout at X1 of the phyCORE-STM32MP1

Jumpers

For configuration purposes, the phyCORE-STM32MP1 has several solder jumpers, some of which have been installed prior to delivery. The figure below, Typical Jumper Pad Numbering Scheme, illustrates the numbering scheme for the various solder jumper pads.Jumper Locations (Top View)and  Jumper Locations (Bottom View) indicate the location and the default configuration of the solder jumpers on the board.

TableJumper Settings provides a functional summary of the solder jumpers which can be changed to adapt the phyCORE‑STM32MP1 to specific design needs. It shows their default positions, and possible alternative positions and functions. A detailed description of each solder jumper can be found in the applicable chapter listed in the table.

Tip

Jumpers not listed should not be changed as they are installed with regards to the configuration of the phyCORE‑STM32MP1.

Typical Jumper Pad Numbering Scheme

If manual jumper modification is required, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable.  If soldered jumpers need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Warning

If any modifications to the module are performed, regardless of their nature, the manufacturer guarantee is voided.


Jumper Locations (Top View)

Jumper Locations (Top View)


Jumper Locations (Bottom View)

Jumper Locations (Bottom View)

Pay special attention to the “TYPE” column to ensure you are using the correct type of jumper (0 Ohms, 10k Ohms, etc…). The jumpers are 0402 packages with a 1/8 W or better power rating.

The jumpers (J = solder jumper) have the following functions.

JumperPositionDescriptionTypeSection
J1

1+2
PDR_ON connected to VDD, VDD OK detector enabled
0402



Power Supply Supervisor

2+3PDR_ON connected to GND, VDD OK detector disabled
J21+2PDR_ON_CORE connected to VDD, VDDCORE OK detector enabled
0402
2+3PDR_ON_CORE connected to GND, VDDCORE OK detector disabled
J3openInterrupt output  from PMIC not used, PA0 freely available at X1D52
0402


closedInterrupt output from PMIC connected to X_nPMIC_INT/PA0
J4openWake-up input from PMIC  not used, PC13 freely available at X1D53
0402


closedWake-up input from PMIC  connected to X_WAKEUP3/PC13
J51+2Only external RTC s supplied through VBAT input (D57), whileSTM32MP1 backup domain Vsw supplied by the main system power VDD



0402


Backup Power Supply

2+3External RTC and STM32MP1 backup domain Vsw supplied via backup supply input pin VBAT (D57)
J91+2Voltage resulting from jumper J10 configuration (VDD or VDD_BUCK4) connected to  PMIC's LDO regulators 2 and 5 input

0402



2+3VCC5V_IN selected as the supply voltage for the PMIC's LDO regulators 2 and 5
J101+2VDD_BUCK4 used as Ethernet supply voltage (VDD_ETH_3V3) and jumper J9 input (pin 1)

0402
2+3VDD used as Ethernet supply voltage (VDD_ETH_3V3) and jumper J9 input (pin 1)
J131+2write protection of the NAND flash device U10 is only
enabled during RESET


0402


NAND Flash

2+3write protection of the NAND flash device U10
permanently enabled
J14openVREF not connected to VDDA (for STM32MP1 internal reference or external VREF from X1C15)
0402


closedVREF connected to VDDA (supplied by VDD (J16) or VDDA (J15) of the PMIC's LDO5)
J15openSTM32MP1's VDDA not connected to PMIC's VDDA (J16 must be closed!)
0402
closedVDDA connected to VDDA of the PMIC's LDO5 (J16 must be open!)
J16openVDDA not connected to VDD (J15 must be closed!)
0805
closedVDDA connected to VDD (J15 must be open!)
J171+2Boot configuration input BOOT0 connected to VDD10 k
0402




Boot Mode Selection

2+3Boot configuration input BOOT0 connected to GND
J181+2Boot configuration input BOOT1 connected to VDD10 k
0402
2+3Boot configuration input BOOT1 connected to GND
J191+2Boot configuration input BOOT2 connected to VDD10 k
0402
2+3Boot configuration input BOOT2 connected to GND

Jumper Settings

Power

The phyCORE-STM32MP1 operates off of a single power supply voltage. The following sections discuss the primary power pins on the phyCORE‑Connector X1 in detail.

Primary System Power (VCC5V_IN)

The phyCORE-STM32MP1 is powered by a primary voltage supply with a nominal value of +5 V. On-board switching regulators generate the voltage supplies required by the STM32MP1 MCU and on-board components from the primary 5 V supplied to the SOM. For proper operation, the phyCORE‑STM32MP1 must be supplied with a voltage source of 5 V ±5 % with 3 A load at the VCC5V_IN pins on the phyCORE-Connector X1.

                VCC5V_IN:     X1 →  C58, C59, C60, D59, D60

Connect all +5 V VCC input pins to your power supply and all available GND pins. Please refer to section Pin Description for information on additional GND Pins located at the phyCORE‑Connector X1.

Warning

As a general design rule, all GND pins must be connected to a solid ground plane.

Power Management IC (PMIC) (U7)

The phyCORE-STM32MP1 provides an on-board Power Management IC (PMIC) at position U7 to generate different voltages required by the microcontroller and the on-board components. The PMIC supports many functions such as different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the STM32MP1 via the on-board I2C bus (I2C4). The I2C address of the PMIC is 0x33.

External voltages:

  • VCC5V_IN 5 V main supply voltage
  • VBAT 3 V Backup Supply for RTC and STM32MP1 backup domain Vsw (optionally)
  • VDD I/O supply voltage output
  • VDD_BUCK4 PMIC BUCK4 converter output
  • VDD_LDO1 PMIC LDO1 output

Supply Voltage for External Logic

The voltage level of the phyCORE’s logic circuitry is VDD (3.3 V), which is derived from the SOM main input voltage VDD5V_IN. In order to follow the power-up and power-down sequencing mandatory for the STM32MP1, external devices have to be supplied by the I/O supply voltage VDD or VDD_BUCK4 (3.3 V) which is brought out at pin X1D56 (VDD) and pins X1C55 + X1C56 (VDD_BUCK4) of the phyCORE-Connector. Using VDD ensures that external components are only supplied when the supply voltages of the STM32MP1 are stable.

VDD_BUCK4 (3.3 V / max. 1 A) output at pins X1C55 and X1C56 can be used also to supply external circuits connected to the phyCORE-STM32MP1.

Warning

  • The current draw for VDD must not exceed 10 mA. Consequently, this voltage should only be used as a reference, for level shifters or switch supply voltage from other sources, not for supplying purpose. If devices with higher power consumption are connected to the phyCORE‑STM32MP1, their supply voltage should be switched on and off by the use of the VDD or VDD_BUCK4 signal. This way, the power-up, and power-down sequencing will be considered even if the devices are not supplied directly by VDD. Additionally, a voltage supervisor should be added to the carrier board. This supervisor should be powered by VDD and hold X_nRESET (X1D51) low, as long as the externally generated voltages are not in proper shape. 
  • Take care not to overload the VDD_BUCK4 output or exceed the thermal limits of the PMIC on the phyCORE‑STM32MP1!

Backup Power (VBAT)

To back up the RTC at U13 and, optionally, the STM32MP1's backup domain Vsw, an external voltage source of 1.8 V to 3.6 V can be connected to VBAT pin D57. If jumper J5 is closed at 1+2 (default setting) only the RTC at U13 which has an extremely low backup current consumption of typ. 40 nA  @3 V (max. 500 nA) is supplied by the backup source.

Additionally, it is possible to supply the STM32MP1's internal RTC,  some registers and SRAM  via backup domain Vswby the VBAT voltage if jumper J5 is set to 2+3.

Tip

In order to get the minimum power consumption to back up the RTC while the main supply voltage is not available, jumper J5 must be closed at 1+2 (default configuration). Otherwise, the STM32MP1's backup domain Vsw will be supplied by the backup voltage source, too.

Power Supply Supervisor

The STM32MP1 has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. Two jumpers (J1 and J2) allow the configuration of the power supply supervisor.

  • J1 connects PDR_ON either to VDD or to GND, enabling or disabling the power-down reset (PDR). If PDR is enabled the PDR supervisor monitors the VDD power supply. A reset is generated when VDD drops below a fixed threshold.
  • J2 connects PDR_ON_CORE either to VDD or to GND, enabling or disabling the power-down reset VDDCORE (PDR_VDDCORE). If PDR_VDDCORE is enabled the PDR_VDDCORE supervisor monitors the VDDCORE power supply. A VDDCORE domain reset is generated when VDDCORE drops below a fixed threshold.

The following configurations are possible:

J1PDR supervisor enable/disable
1+2PDR_ON connected to VDD, VDD OK detector enabled
2+3PDR_ON connected to GND, VDD OK detector disabled
J2PDR_ON_CORE supervisor enable/disable
1+2PDR_ON_CORE connected to VDD, VDDCORE OK detector enabled
2+3PDR_ON_CORE connected to GND, VDDCORE OK detector disabled

Warning

When the PDR_ON pin is connected to GND (internal reset OFF), the VBAT functionality is no more available and the VBAT pin must be connected to VDD by ensuring that jumper J5 is closed in the default position 1+2.

Reset

The X_nRESET signal (Pin X1D61) on the phyCORE-Connector is designated as the reset input/output. Holding this pin low triggers a hard reset of the module. X_nRESET can be used to prevent the boot-up of the STM32MP1.

System Boot Configuration

Most features of the STM32MP1 microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

  • Boot mode selection
  • Boot device selection
  • Boot device configuration

The internal ROM code is the first code executed during the initialization process of the STM32MP1 after POR. The ROM code detects the boot mode and configuration by using the boot mode pins (BOOT[2:0]).

Boot Mode Selection

The boot mode of the STM32MP1 microcontroller is determined by the configuration of three boot mode inputs BOOT[2:0] of the STM32MP1 during the reset cycle of the operational system.

Configuration circuitry (10 kΩ pull-up and pull-down resistors on jumpers J17 to J19 connected to BOOT[2:0]) is located on the phyCORE‑STM32MP1 so no further settings are necessary. The boot configuration of pins BOOT[2:0] on the standard phyCORE‑STM32MP1 module is 0b010. Consequently, the system will try to boot from eMMC first.

Additionally, the boot mode inputs are brought out at the phyCORE‑Connector pins X_BOOT[2:0] (X1C21, X1C20, X1C19). Hence, the specific boot configuration settings, which are set by the on-board configuration resistors, can be changed by modifying jumpers J17 to J19 on the module or by connecting a configuration resistor (e.g. <1 kΩ pull-up) to the BOOT signal pins at the phyCORE-Connector.

The table phyCORE-STM32MP1 Boot Modes shows the possible settings and the resulting boot configuration of the STM32MP1.

Boot ModeBOOT2 (J19 / X1C21)BOOT1 (J18 / X1C20)BOOT0 (J17 / X1C19)
UART/USB-HS device0     (J19: 2+3)0     (J18: 2+3)0     (J17: 2+3)
QSPI NOR Flash on QSPI-BK1 0     (J19: 2+3)0     (J18: 2+3)1     (J17: 1+2)
eMMC on SDMMC20     (J19: 2+3)1     (J18: 1+2)0     (J17: 2+3)
SLC NAND Flash on FMC 0     (J19: 2+3)1     (J18: 1+2)1     (J17: 1+2)
Reserved 1     (J19: 1+2)0     (J18: 2+3)0     (J17: 2+3)
SD card on SDMMC11     (J19: 1+2)0     (J18: 2+3)1     (J17: 1+2)
UART/USB-OTG-HS device 1     (J19: 1+2)1     (J18: 1+2)0     (J17: 2+3)
Reserved1     (J19: 1+2)1     (J18: 1+2)1     (J17: 1+2)

 phyCORE-STM32MP1 Boot Modes


Warning

Make sure that the boot mode inputs X_BOOT[2:0] (X1C21, X1C20, X1C19) are not driven by any device on the carrier board during reset. This is to avoid accidental change of the boot configuration.

System Memory

The phyCORE-STM32MP1 provides five types of on-board memory:

  • One bank of 32-bit DDR3L RAM: 256 MB (up to 1 GB)
  • eMMC: 4 GB (up to 128 GB), or
    SLC NAND flash: 128 MB (up to 1 GB)
  • Quad SPI NOR flash: 4 MB (up to 16 MB)
  • I²C-EEPROM: 4 kB (up to 32 kB)

Details for each memory type used on the phyCORE-STM32MP1 are described below.

DDR3L-SDRAM (U8, U9)

The RAM memory of the phyCORE-STM32MP1 is comprised of two 16-bit wide DDR3L-SDRAM chips (U8, U9). The memory devices are connected to the dedicated DDRPHYC SDRAM interface of the STM32MP1 microcontroller.

The DDR3-SDRAM memory is accessed starting at address 0xC000 0000.

The DDR memory subsystem of the STM32MP1 is composed of the  DDRCTRL and the DDRPHYC and provides a complete memory interface. Typically, the DDR3-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the DDRPHYC SDRAM interface and the DDRCTRL must be initialized by accessing the appropriate configuration registers on the STM32MP1 controller. Refer to the STM32MP1 Reference Manual to access and configure these registers.

Flash Memory (U1, U10)

Use of Flash as non-volatile memory on the phyCORE-SM32MP1 provides an easily reprogrammable means of code storage. The phyCORE-STM32MP1 can be equipped with either an eMMC (U1) memory device or a NAND flash (U10) as non-volatile memory.

eMMC Memory (U1)

The main flash memory of the STM32MP1 is a managed NAND (eMMC) flash device populated at U1. The eMMC device is programmable with 3.3 V. No dedicated programming voltage is required. The eMMC Flash memory is connected to the second Secure digital input/output MultiMediaCard interface (SDMMC2) of the STM32MP1. For more information about the SDMMC interfaces, please refer to the STM32MP1 Reference Manual.

If the phyCORE-STM32MP1 is equipped with a NAND flash at U10 instead of the eMMC device (see next section), SDMMC2 is available at the phyCORE-Connector X1.

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A11X_SDMMC2_DATA0/PB143.3 VI/OSD/SDIO/eMMC card data line 0
A12X_SDMMC2_DATA1/PB153.3 VI/OSD/SDIO/eMMC card data line 1
A13X_SDMMC2_DATA2/PB33.3 VI/OSD/SDIO/eMMC card data line 2
A14X_SDMMC2_DATA3/PB43.3 VI/OSD/SDIO/eMMC card data line 3
A15X_SDMMC2_DATA4/PA83.3 VI/OSD/SDIO/eMMC card data line 4
A16X_SDMMC2_DATA5/PA93.3 VI/OSD/SDIO/eMMC card data line 5
A17X_SDMMC2_DATA6/PC63.3 VI/OSD/SDIO/eMMC card data line 6
A18X_SDMMC2_DATA7/PD33.3 VI/OSD/SDIO/eMMC card data line 7
A20X_SDMMC2_CMD/PG63.3 VI/OSD/SDIO/eMMC card bidirectional command/response signal
A21X_SDMMC2_CLK/PE33.3 VOSD/SDIO/eMMC card clock

SDMMC2 Interface Signal Location at X1


Note

Other interface signals (SDMMC_CKIN, SDMMC_CDIR, SDMMC_D0DIR, SDMMC_D123DIR) belonging to the second Secure digital input/output MultiMediaCard interface (SDMMC2) are also available at different pins of the phyCORE-Connector. However, the standard pin muxing of the phyCORE-STM32MP1 assigns other functions to these pins. Hence the pin muxing must be changed if signals SDMMC_CKIN, SDMMC_CDIR, SDMMC_D0DIR, and SDMMC_D123DIR are needed.

Please refer to the STM32MP1 Data Sheet for details on the pin-muxing options.

NAND Flash Memory (U10)

Alternatively to the eMMC memory at U1, an SLC NAND flash can be populated at U10. The NAND Flash memory is connected to the STM32MP1's Flexible Memory Controller (FMC) interface with a bus-width of 8-bits. NCE1 (FMC_NCE/PG9) of the FMC interface selects the NAND Flash at U10. The FMC interface is also available at the phyCORE-Connector and can be used if no NAND flash is mounted on U10. These signals are available without changing the pin multiplexing of the phyCORE-STM32MP1.

SOM Connector Pin 

SOM Signal Name

Signal Level

Signal Type

Description

B20X_FMC_DATA0/PD143.3 VI/OAddress / Data 0
B21X_FMC_DATA1/PD153.3 VI/OAddress / Data 1
B22X_FMC_DATA2/PD03.3 VI/OAddress / Data 2
B23X_FMC_DATA3/PD13.3 VI/OAddress / Data 3
B24X_FMC_DATA4/PE73.3 VI/OAddress / Data 4
B25X_FMC_DATA5/PE83.3 VI/OAddress / Data 5
B26X_FMC_DATA6/PE93.3 VI/OAddress / Data 6
B27X_FMC_DATA7/PE103.3 VI/OAddress / Data 7
B29X_FMC_nWAIT/PD63.3 VIInput for external ready/busy (wait) signal (active low)
B30X_FMC_nOE/PD43.3 VOOutput enable/ Read enable (active low)
B31X_FMC_nCE/PG93.3 VOChip select 1
B32X_FMC_CLE/PD113.3 VOCommand latch enable
B33X_FMC_ALE/PD123.3 VOAddress latch enable
B34X_FMC_nNWE/PD53.3 VOWrite enable (active low)

FMC Interface Signal Location at X1
The flash devices are programmable with 3.3 V. No dedicated programming voltage is required.

As of the printing of this manual, these NAND flash devices generally have a life expectancy of at least 100,000 erase/program cycles and a data retention rate of 10 years.

Any parts that are footprint (TSOP48) and functionally compatible may be used with the phyCORE-STM32MP1.

NAND Flash Write Protection Control (J13)

Jumper J13 controls the write protection feature of the NAND flash at U10. Setting this jumper to position 1+2 protects the flash against write access during a power-on reset cycle. Setting this jumper to 2+3 protects the NAND flash permanently against write cycles.

The following configurations are possible:

J13NAND Flash Write Protection State
1+2Write protection enabled during power-on reset
2+3Write protection enabled permanently

Quad SPI NOR Flash (U11)

The QSPI NOR flash memory of the phyCORE-STM32MP1 at U11 is available on most standard configurations of the SOM and can be used to store configuration data or any other general-purpose data. Besides this, it can also be used as a boot device and recovery boot device and is, therefore, suitable for applications that require a small code footprint or small RTOSes.

Tips

Using a QSPI Flash can eliminate the need to install eMMC or NAND flash memory on the SOM. This could reduce BOM costs, free up the ports used as SDMMC2 or FMC interface for other devices to be connected to the phyCORE-STM32MP1, and remove the need for doing the bad block management that is required when using NAND flash.


The device is connected to bank 1 of the STM32MP1's Quad-SPI interface (QUADSPI) and can be accessed through QUADSPI_BK1_NCS. The control registers for QSPI are mapped between addresses 0x58003000 and 0x58003FFF. Please see the STM32MP15x Reference Manual for detailed information on the registers.

If the phyCORE-STM32MP1 comes without an on-board Quad SPI flash, the QSPI signals are available at phyCORE-Connector X1In order to connect an external Quad SPI flash.

SOM Connector Pin 

SOM Signal Name

Signal Level

Signal Type

Description

C4X_QSPI_BK1_DATA0/PF83.3 VI/OQSPI Bidirectional IO0
C5X_QSPI_BK1_DATA1/PF93.3 VI/OQSPI Bidirectional IO1
C6X_QSPI_BK1_DATA2/PF73.3 VI/OQSPI Bidirectional IO2
C7X_QSPI_BK1_DATA3/PF63.3 VI/OQSPI Bidirectional IO3
C8X_QSPI_BK1_nCS/PB63.3 VOQSPI chip select for bank 1 (low active)
C9X_QSPI_CLK/PF103.3 VOQSPI clock signal

QSPI Interface Signal Location at X1

Note

The interface signals for the second bank of the Quad-SPI interface (QUADSPI) are also available at different pins of the phyCORE-Connector. However, the standard pin muxing of the phyCORE-STM32MP1 assigns other functions to these pins. Hence the pin muxing must be changed if a second QSPI flash should be connected.

Please refer to the STM32MP1 Data Sheet for details on the pin-muxing options.

As of the printing of this manual, these SPI Flash devices generally have a life expectancy of at least 100,000+ erase/program cycles and a data retention rate of 20 years. This makes the OSPI NOR flash a reliable and secure solution to store the first and second level bootloaders.

I2C EEPROM (U12)

The standard configuration of the phyCORE-STM32MP1 is populated with a non-volatile 4 kB I2C EEPROM at U12. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I2C port 4 on the STM32MP1. The control registers for I2C port 4 are mapped between addresses 0x5C002000 and 0x5C0023FF. Please see the STM32MP1 Reference Manual for detailed information on the registers.

The I²C EEPROM populating the phyCORE-STM32MP1 has the ability to configure the address for the memory area and the additional ID page using chip-enabled signals E0 to E2. The four upper address bits of the device are fixed at ‘1010’ (see M24C32 datasheet). Chip-enable signals E0 to E2 are fixed connected to GND. Thus the resulting addresses are 0x50 for the memory array and 0x58 for the additional ID page.

EEPROM Write Protection Control (R23)

Mounting a 10 kΩ resistor at R23 will cause the EEPROM to enter write-protect mode, thereby disabling write access to the device. In the default configuration resistor, R23 is not mounted which means write access to the device is allowed.

The following configurations are possible:

R23EEPROM Write Protection State
openWrite access allowed
10 kΩ resistor mountedEEPROM is write-protected

EEPROM write protection states via R23

Serial Interfaces

The phyCORE-STM32MP1 provides numerous dedicated serial interfaces, some of which are equipped with a transceiver/PHY to allow direct connection to external devices, others can be muxed to other pins. The STM32MP1 has some more interfaces that can be used by individual pin muxing. This chapter only describes the predefined interfaces.

  1. High-speed USB OTG interface (extended directly from the second port of the STM32MP1's USB high-speed PHY)
  2. High-speed USB host interface (extended directly from the first port of the STM32MP1's USB high-speed PHY)
  3. One Gbit Ethernet interface
  4. Two I2C interfaces
  5. One Serial Peripheral Interfaces (SPI)
  6. Three UART interfaces
  7. Two CAN FD interfaces
  8. Three SDIO interfaces
  9. One SAI interface

The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers.

USB OTG Interface

The phyCORE-STM32MP1 provides a high-speed USB OTG interface that uses the STM32MP1's embedded high-speed USB OTG IP-Core connected to the second port of the embedded USB high-speed PHY. The USB OTG IP-Core supports both device and host functions and is fully compliant with the On-The-Go Supplement to the USB 2.0 specification. It can also be configured as a host-only or device-only controller. An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for USB OTG) connector is all that is needed to interface the phyCORE-STM32MP1 USB OTG functionality. The applicable interface signals can be found on the phyCORE-Connector X1 as shown in the following table.

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

D2X_USB_OTG_VBUS5.0 VPWR_IUSB OTG VBUS input
D3X_USB_OTG_D2P3.3 VUSB_I/OUSB OTG data plus
D4X_USB_OTG_D2M3.3 VUSB_I/OUSB OTG data minus
D8X_USB_OTG_ID/PA103.3 VIUSB OTG ID Pin
C53VBUS_OTG5.0 VPWR_OVBUS supply voltage from PMIC

Location of the USB OTG Signals at X1

Warning

X_USB_OTG_VBUS must be supplied with 5 V for proper USB functionality.

USB Host Interface

The phyCORE-STM32MP1 provides a high-speed USB OTG interface that uses the STM32MP1's embedded high-speed USB OTG IP-Core connected to the second port of the embedded USB high-speed PHY. The USB OTG IP-Core supports both device and host functions and is fully compliant with the On-The-Go Supplement to the USB 2.0 specification. It can also be configured as a host-only or device-only controller. An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for USB OTG) connector is all that is needed to interface the phyCORE-STM32MP1 USB OTG functionality. The applicable interface signals can be found on the phyCORE-Connector X1 as shown in the following table.

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

D6X_USB_HOST_D1M3.3 VUSB_I/OUSB host data minus
D7X_USB_HOST_D1P3.3 VUSB_I/OUSB OTG data plus
C52VBUS_SW5.0 VPWR_OVBUS supply voltage from PMIC

Location of the USB host Signals at X1

Ethernet Interface

Connection of the phyCORE‑STM32MP1 to the World Wide Web or a local area network (LAN) is possible using the on-board GbE PHY at U3. It is connected to the RGMII interface (ETH1) of the STM32MP1. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s.

Alternatively, the RGMII (ETH1) interface which is available on the phyCORE-Connector can be used to connect an external PHY. In this case, the on-board GbE PHY (U3) must not be populated (sectionRGMII Interface).

Ethernet PHY (U3)

With an Ethernet PHY mounted at U3, the phyCORE‑STM32MP1 has been designed for use in 10Base‑T, 100Base‑T, and 1000Base‑T networks. The 10/100/1000Base‑T interface with its LED signals extends to phyCORE‑Connector X1.

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

D30X_ETH_A+3.3 VETH_I/OEthernet data A+
D31X_ETH_A-3.3 VETH_I/OEthernet data A-
D33X_ETH_B+3.3 VETH_I/OEthernet data B+
D34X_ETH_B-3.3 VETH_I/OEthernet data B-
D36X_ETH_C+3.3 VETH_I/OEthernet data C+
D37X_ETH_C-3.3 VETH_I/OEthernet data C-
D39X_ETH_D+3.3 VETH_I/OEthernet data D+
D40X_ETH_D-3.3 VETH_I/OEthernet data D-
D42X_ETH_LED0_LINK3.3 VODEthernet link LED output
D43X_ETH_LED1_GBIT3.3 VODEthernet Gb indication LED output
D44X_ETH_LED2_ACT3.3 VODEthernet traffic LED output

Location of the Ethernet Signals at X1

The on-board GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface (ETH1) of the STM32MP1. Please refer to the STMicroelectronics STM32MP1 Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (X_ETH_A±, X_ETH_B±, X_ETH_C±, X_ETH_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.

Warning

Please refer to the Ethernet PHY datasheet when designing the Ethernet transformer circuitry or request the schematic of the applicable carrier board (phyBOARD-Sargas STM32MP1).

Ethernet PHY GPIOs

The Ethernet PHY mounted on the phyCORE-STM32MP1 provides two additional GPIOs. These are available at pins D45 (X_ETH_GPIO0) and D46 (X_ETH_GPIO1) of the phyCORE‑Connector X1. They can be configured by the appropriate registers of the Ethernet PHY.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑STM32MP1 can be found on a  sticker (with 2D matrix code) attached to the module. This number is a 12-digit HEX value. 

The MAC address of the module is also programmed in the appropriate OTP (STM32MP1's on-chip one-time programmable memory). Assigned OTP-registers in the STM32MP1:
OTP_57[31:0] = MAC_ADDR[31:0]
OTP_58[15:0] = MAC_ADDR[47:32]

RGMII Interface

In order to use an external Ethernet PHY instead of the on-board GbE PHY at U3, the RGMII interface (ETH1) of the STM32MP1 is brought out at phyCORE‑Connector X1.

Warning

The GbE PHY (U3) must not be populated on the module if the RGMII interface is used.

Anyway, it is not recommended to remove the Ethernet PHY and other components affecting the use of an Ethernet PHY externally connected to the module, as this will void the manufacturer's warranty. The phyCORE-STM32MP1 can be ordered without Ethernet PHY if an external Ethernet PHY is to be connected.


SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

C29X_ETH1_RGMII_RXD0/PC43.3 VIETH1 RGMII receive data 0
C30X_ETH1_RGMII_RXD1/PC53.3 VIETH1 RGMII receive data 1
C31X_ETH1_RGMII_RXD2/PH63.3 VIETH1 RGMII receive data 2
C32X_ETH1_RGMII_RXD3/PB13.3 VIETH1 RGMII receive data 3
C33X_ETH1_RGMII_RX_CTL/PA73.3 VIETH1 RGMII receive control (RX_DV + RX_ER)
C34X_ETH1_RGMII_RX_CLK/PA13.3 VIETH1 RGMII receive clock
C36X_ETH1_RGMII_TXD0/PG133.3 VOETH1 RGMII transmit data 0
C37X_ETH1_RGMII_TXD1/PG143.3 VOETH1 RGMII transmit data 1
C38X_ETH1_RGMII_TXD2/PC23.3 VOETH1 RGMII transmit data 2
C39X_ETH1_RGMII_TXD3/PE23.3 VOETH1 RGMII transmit data 3
C40X_ETH1_RGMII_TX_CTL/PB113.3 VI/OETH1 RGMII transmit control (TX_EN + TX_ER)
C41X_ETH1_RGMII_GTX_CLK/PG43.3 VOETH RGMII transmit clock
C43X_ETH1_MDC/PC13.3 VOEthernet management data clock
C44X_ETH1_MDIO/PA23.3 VI/OEthernet management data I/O
C45X_ETH1_nINT/PG123.3 VIEthernet interrupt  (low active)
C46X_ETH1_RGMII_CLK125/PG53.3 VIExternal clock RX provided by the Ethernet PHY

Location of the RGMII Interface Signals at X1

Note

It is strongly recommended to place the Ethernet PHY on the Carrier Board close to the pins of the SOM's Ethernet interface to achieve a trace length of less than 100 mm.

Tip

ETH_CLK is available at pins X1B57 (X_SPI1_MOSI/PB5 and X1D12 (X_USART3_RTS/PG8) of the phyCORE-Connector if an external Ethernet PHY is to be connected without quartz.

I2C Interface

The Inter-Integrated Circuit (I2C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The STM32MP1 contains several identical and independent multi-master fast-mode plus I2C modules. They are multiplexed with other signals. Please check the STMicroelectronics STM32MP15x Reference Manual for further information.

One of these I2C modules (I2C4) is used on the phyCORE STM32MP1 and is available at phyCORE-Connector X1. A second one (I2C1) is predefined for external usage. The following table lists the I2C ports on the phyCORE-Connector:

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

D21X_I2C4_SCL/PZ43.3 VOI2C4 SCL (clock out) with  internal 2 kΩ pull-up to VDD, used for internal I2C devices (PMIC, RTC, EEPROM)
D22X_I2C4_SDA/PZ53.3 VI/OI2C4 SDA (data I/O) with internal 2 kΩ pull-up to VDD, used for internal I2C devices (PMIC, RTC, EEPROM)





D23X_I2C1_SCL/PF143.3 VOI2C1 SCL (clock out) for external I2C devices, an external pull up resistor is needed.
D24X_I2C1_SDA/PF153.3 VI/OI2C1 SDA (data I/O) for external I2C devices, an external pull up resistor is needed.

I2C2 Interface Signal Locations at X1

I2C4 is used for SOM internal PMIC communication and should not be used for external devices.

SDIO Interface

The SDIO interfaces can be used to connect external SD cards, eMMC, or any other device requiring SDIO interface (i.e Wi‑Fi, I/O expansion, etc.) The phyCORE bus features three SDIO interfaces. One of the phyCORE‑STM32MP1 SD interfaces (SDMMC2) supports 8-bit bus width and is internally used for eMMC.

The tables below show the location of the different interface signals on the phyCORE-Connector. 

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A11X_SDMMC2_DATA0/PB143.3 VI/OSDMMC2 D0 /eMMC  (do not connect this pin if eMMC is used on the SOM) 
A12X_SDMMC2_DATA1/PB153.3 VI/OSDMMC2 D1 /eMMC  (do not connect this pin if eMMC is used on the SOM) 
A13X_SDMMC2_DATA2/PB33.3 VI/OSDMMC2 D2 /eMMC  (do not connect this pin if eMMC is used on the SOM) 
A14X_SDMMC2_DATA3/PB43.3 VI/OSDMMC2 D3 /eMMC  (do not connect this pin if eMMC is used on the SOM) 
A15X_SDMMC2_DATA4/PA83.3 VI/OSDMMC2 D4 /eMMC  (do not connect this pin if eMMC is used on the SOM) 
A16X_SDMMC2_DATA5/PA93.3 VI/OSDMMC2 D5 /eMMC  (do not connect this pin if eMMC is used on the SOM) 
A17X_SDMMC2_DATA6/PC63.3 VI/OSDMMC2 D6 /eMMC  (do not connect this pin if eMMC is used on the SOM) 
A18X_SDMMC2_DATA7/PD33.3 VI/OSDMMC2 D7 /eMMC  (do not connect this pin if eMMC is used on the SOM) 
A20X_SDMMC2_CMD/PG63.3 VI/OSDMMC2 CMD /eMMC  (do not connect this pin if eMMC is used on the SOM) 
A21X_SDMMC2_CLK/PE33.3 VOSDMMC2 CLK /eMMC  (do not connect this pin if eMMC is used on the SOM) 





B8X_SDMMC1_D0/PC83.3 VI/O

SDMMC1 D0  (to boot from external SDCARD)

B9X_SDMMC1_D1/PC93.3 VI/OSDMMC1 D1  (to boot from external SDCARD)
B10X_SDMMC1_D2/PE63.3 VI/OSDMMC1 D2   (to boot from external SDCARD)
B11X_SDMMC1_D3/PC113.3 VI/OSDMMC1 D3   (to boot from external SDCARD)
B12X_SDMMC1_CMD/PD23.3 VI/OSDMMC1 CMD  (to boot from external SDCARD)
B14X_SDMMC1_CK/PC123.3 VOSDMMC1 CLK   (to boot from external SDCARD)
B15X_SDMMC1_CKIN/PE43.3 VI/O-IGPIO PE4
B16X_SDMMC1_CDIR/PB93.3 VI/O-OGPIO PB9  / UART4 TXD
B17X_SDMMC1_D0DIR/PF23.3 VI/O-OGPIO PF2
B18X_SDMMC1_D123DIR/PE143.3 VI/O-OGPIO PE14





A23X_SDMMC3_D0/PF03.3 VI/OSDMMC3 D0
A24X_SDMMC3_D1/PF43.3 VI/OSDMMC3 D1
A25X_SDMMC3_D2/PF53.3 VI/OSDMMC3 D2
A26X_SDMMC3_D3/PD73.3 VI/OSDMMC3 D3
A27X_SDMMC3_CMD/PF13.3 VI/OSDMMC3 CMD
A28X_SDMMC3_CK/PG153.3 V

O

SDMMC3 CLK

SDMMC1, SDMMC2, and SDMMC3 Interface Locations at X1

Universal Asynchronous Interface

The phyCORE‑STM32MP1 provides several high speed universal asynchronous interfaces. Only three are described here as U(S)ARTs. Please refer to the STMicroelectronics STM32MP15x Reference Manual or Pin Muxing Tool if you need more U(S)ARTs. The following tables show the location of the signals on the phyCORE-Connector.

SOM Connector Pin

SOM Signal Name

Signal Level

Signal TypeDescription
D10X_USART3_RX/PB123.3 VIUSART3 RXD in
D11X_USART3_TX/PB103.3 VOUSART3 TXD out
D12X_USART3_RTS/PG83.3 VOUSART3 RTS out
D13X_USART3_CTS/PB133.3 VIUSART3 CTS in

USART3 Signal Locations at X1

SOM Connector Pin

SOM Signal Name

Signal Level

Signal TypeDescription
A55X_USART1_TX/PZ73.3 VOUSART1 TXD out
B55X_USART1_RX/PZ63.3 VIUSART1 RXD in





A54X_UART4_RX/PB23.3 VIUART4 RXD in
B16X_SDMMC1_CDIR/PB93.3 VOUART4 TXD out

USART1 and UART4 Signal Locations at X1

CAN FD Interface

The STM32MP1 provides two CAN FD interfaces (FDCAN1 and FDCAN2). These CAN FD interfaces are available on the phyCORE-STM32MP1 connector X1.

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

C1X_FDCAN1_RX/PA113.3 VICAN FD1 RXD in
C2X_FDCAN1_TX/PA123.3 VOCAN FD1 TXD out





B57X_SPI1_MOSI/PB53.3 VIGPIO PB5 / CAN FD2 RXD in
D13X_USART3_CTS/PB133.3 VOUSART3 CTS in / CAN FD2 TXD out

CAN FD Interface Signal Locations at X1

SPI Interface

The STM32MP1 provides one dual-mode Quad-SPI interface (QSPI) and up to six SPI interfaces. The Quad interface (QSPI-BK1) is directly connected to an optional on-board OSPI Flash (U11) see chapter 9.4.  One SPI interface (SPI1) is predefined on the connector X1.

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A56X_SPI16_MOSI/PZ23.3 VOSPI1 MOSI out
A57X_SPI16_NSS/PZ33.3 VOSPI1 nSlaveSlect out
B54X_SPI16_SCK/PZ03.3 VOSPI1 SCLK out
B56X_SPI16_MISO/PZ13.3 VISPI1 MISO in

SPI1 Interface Signal Locations at X1

Audio Interface (SAI)

The Synchronous Audio Interface (SAI) on the phyCORE-STM32MP1 is a full-duplex, serial interface that enables communication with a variety of serial devices such as standard codecs signal digital processors (SDPs), microprocessors peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S), PDM and SPDIF standard. The STM32MP1 provides different possibilities of using the SAI modules.

The main purpose of this interface is to connect to an external codec, such as I2S. The SAI is intended to be used in synchronous mode. The tables below show the locations of the SAI2 sources:

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

D15X_SAI2_SD_A/PI63.3 VI/OSAI2 SDA
D16X_SAI2_SD_B/PF113.3 VI/OSAI2 SDB
D17X_SAI2_SCK_B/PH23.3 VI/OSAI2 SCKB
D18X_SAI2_MCLK_B/PH33.3 VI/O-OSAI2 MCLKB
D19X_SAI2_FS_B/PC03.3 VI/OSAI2 FSB

SAI2 Interface Signal Locations at X1

General Purpose I/Os

All STM32MP1 port pins not used by any of the other interfaces can be muxed and used as GPIO without harming other features of the phyCORE‑STM32MP1:

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A58X_PI03.3 VI/OGPIO PI0 (LCD dim PWM out)
A59X_PI33.3 VI/OGPIO PI3 (LCD Touch-IRQn in)
A60X_PD93.3 VI/OGPIO PD9 (LCD Reset out)
B15X_SDMMC1_CKIN/PE43.3 VI/O-IGPIO PE4 / SDMMC1 clock in
B16X_SDMMC1_CDIR/PB93.3 VI/O-OGPIO PB9 / UART4 TXD
B17X_SDMMC1_D0DIR/PF23.3 VI/O-OGPIO PF2 / SDMMC1 dat0 direction out
B18X_SDMMC1_D123DIR/PE143.3 VI/O-OGPIO PE14 / SDMMC1 dat123 direction out
B57X_SPI1_MOSI/PB53.3 VI/OGPIO PB5 / CAN FD2 RXD in
B58X_SPI1_NSS/PA153.3 VI/OGPIO PA15 / HDMI-CEC
C23X_DFSDM1_DATIN0/PG03.3 VI/O-IGPIO PG0 / DFSDM1 D0
C24X_DFSDM1_DATIN1/PC33.3 VI/O-IGPIO PC3 / DFSDM1 D1
C25X_DFSDM1_DATIN3/PF133.3 VI/O-IGPIO PF13 / DFSDM1 D2
C26X_DFSDM1_CKIN1/PG33.3 VI/O-IGPIO PG3 / DFSDM1 CK-in
C27X_DFSDM1_CKOUT/PD103.3 VI/O-OGPIO PD10 / DFSDM1 CK-out
D25X_I2C2_SDA/PH53.3 VI/OGPIO PH5
D27X_DBTRGI/PA143.3 VI/O-IDebug Trigger-In / GPIO PA14
D28X_DBTRGO/PA133.3 VI/O-ODebug Trigger-out / GPIO PA13
D47X_PG13.3 VI/OGPIO PG1
D48X_PF33.3 VI/OGPIO PF3
D49X_MCO2/PG23.3 VI/O-OGPIO PG2
D52X_nPMIC_INT/PA03.3 VI/O-IGPIO PA0 (PMIC-IRQn out)
D53X_WAKEUP3/PC133.3 VI/OGPIO PC13 (PMIC-Wakeup in)

GPIO Pin Locations at X1

Beside these pins, most of the STM32MP1 signals which are connected directly to the module connector can be configured to act as GPIOs, due to the multiplexing functionality of most controller pins. Normally, pins with signal type I/O are able to work as a GPIO.

ADC, DAC, and Filter Inputs

The STM32MP1 provides analog-to-digital conversation and vice versa as well as digital filters for sigma-delta modulators (DFSDM). The pin muxing and the pin assignment of the phyCORE-Connector allow these features to be used.

Analog-to-Digital Conversion Inputs

The Analog-to-Digital conversion inputs provide 4 analog input signals. The table below lists the location of the analog input signals and possible functions assigned to them[3].

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

C11X_ADC1_INN1analogANA_IADC1 IN1- analog input
C12X_ADC1_INP1analogANA_IADC1 IN1+ analog input 
C13X_ADC1_INN2/PF12analog / 3.3 VANA_IADC1 IN2- analog input
C14X_PVD_IN/ADC1_INN15/PA3analog / 3.3 VANA_IADC1 IN15- analog input
C15VREFanalogANA-REFAnalog Reference in/out 





C16X_DACOUT1/PA4analog / 3.3 VANA_ODAC OUT1  analog output
C17X_DACOUT2/PA5analog / 3.3 VANA_ODAC OUT2 analog output

Location of the Analog Inputs and Outputs in X1

Jumper J14 allows the voltage source for the analog inputs' reference voltage (VREF) at X1C15 to be connected directly on the SOM to the analog supply (VDDA).  VDDA can be supplied by VDD (J16=default) or via VDDA from PMIC-LDO5 (J15). see Jumper J14, J15, and J16 in section 5.

3.

Almost every controller port that connects directly to the phyCORE-Connector may be used as GPIO by using the STM32MP1's pin muxing options.

DFSDM Interface

The STM32MP1 provides a filter for sigma-delta modulator (DFSDM) with up to 8 channels/6 filters. On the phyCORE-STM32MP1 are 3 data inputs with clock signal to use the DFSDM interface at X1.

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

C23X_DFSDM1_DATIN0/PG03.3 VIDFSDM1 D0 input
C24X_DFSDM1_DATIN1/PC33.3 VIDFSDM1 D1 input
C25X_DFSDM1_DATIN3/PF133.3 VIDFSDM1 D2 input
C26X_DFSDM1_CKIN1/PG33.3 VIDFSDM1 CK input 
C27X_DFSDM1_CKOUT/PD103.3 VODFSDM1 CK output

DFSDM1 Interface Signal Locations at X1

Debug Interface

The phyCORE‑STM32MP1 is equipped with a JTAG/Serial-wire debug interface to control the STM32MP1's debug features with industry-standard debugging tools. It allows downloading program code into the external flash, internal controller RAM, or debugging programs currently being executed.

A trace port allows data to be captured for logging and analysis. Additionally, trigger pins and two LEDs facilitate debugging.

JTAG/Serial-Wire Debug Interface

The location of the JTAG and Serial-wire debug interface pins on the phyCORE-Connector X1 are shown in the table below:

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

B2X_JTAG_nTRST3.3 VIJTAG test reset (active low)
B3X_JTAG_TDI3.3 VIJTAG test data input
B4X_JTAG_TMS/SWDIO3.3 VI / I/OJTAG test mode select / Serial wire data in/out
B5X_JTAG_TCK/SWCLK3.3 VIJTAG test clock / Serial wire clock
B6X_JTAG_TDO/TRACESWO3.3 VO

JTAG test data output / Trace asynchronous data out[5]

JTAG/Serial-Wire Interface Signal Locations at X1

Note

The single wire trace on TRACESWO pin is only available for Cortex-M4 core. To trace all core activities, a parallel trace port must be used. Please refer to the STM32MP1 Datasheet for information regarding ports providing the trace port signals TRACED[15:0] and TRACECLK. 

5.

TRACESWO is multiplexed with JTDO. This means that a single wire trace is only available when using the serial wire debug interface, not when using JTAG.

Debug Trigger / Status LEDs

The phyCORE‑STM32MP1 features two debug trigger pins and two status LEDs. 

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

D27X_DBTRGI/PA143.3 VIExternal trigger input to the cross trigger interface (CTI)
D28X_DBTRGO/PA133.3 VOExternal trigger output from the cross trigger interface (CTI)

Debug Trigger Signal Locations at X1

The two LEDs D1 (green) and D2 (red) are connected to PA14 and PA13, respectively.

D1 indicates the following statuses:

  • During boot phase, in case of boot failure, the PA13 pin is set to low open-drain, LED D2 lights bright.
  • During UART/USB boot, the PA13 pin toggles open-drain at a rate of about 5 Hz until a connection is started, LED D2 blinks fast.
  • With BOOT[2:0] = 0b100 (no boot, used for specific debug), PA13 toggles open-drain at a rate of about 5 kHz, LED D2 lights weak.
  • In all other cases, the PA13 is kept in its reset value, which is high-z until software setting, LED D2 is off.

Please refer to application note AN5031 from ST for more information regarding the use of the debug trigger ports.

UART Virtual Com Port

The phyCORE‑STM32MP1 uses UART4 to support debugging if a virtual com port is needed as an addition to the JTAG interface. UART4 also works as a standard console in the Linux BSP. 

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A54X_UART4_RX/PB23.3 VIUART4 serial data receive signal
B16X_SDMMC1_CDIR/PB93.3 VOUART4 serial data transmit signal

Debug UART Signal Locations at X1

Hardware Debug Port (HDP)

The Hardware Debug Port allows the observation of internal signals. By using multiplexers, up to 16 signals for each of 8-bit output can be observed. All STM32MP1 hardware debug port signals are available at the phyCORE‑Connector as an alternate function. Please make sure that a port is not mandatory for the function of the phyCORE-STM32MP1 before changing the muxing to use the Hardware Debug Port feature. More information about the Hardware Debug Port can be found in the STM32MP1 Reference Manual.

Display Interfaces

The phyCORE‑STM32MP1 provides an 18-bit parallel digital RGB (Red, Green, Blue) and a MIPI DSI interface to connect appropriate displays to the module.

Parallel Display Interface

The STM32MP1 provides a 24-bit parallel digital RGB (Red, Green, Blue) display interface and delivers signals up to WXGA (1366×768) @60 fps resolution. All signals are available at different controller ports as alternate functions. As some of the controller ports are needed for other functions, the parallel display interface of the phyCORE‑STM32MP1 is specified as 18-bit interface only. The table below shows the location of the specified display interface signal on the phyCORE-Connector.

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A40X_LCD_R2/PC103.3 VOLCD data red2
A41X_LCD_R3/PB03.3 VOLCD data red3
A42X_LCD_R4/PH103.3 VOLCD data red4
A43X_LCD_R5/PH113.3 VOLCD data red5
A44X_LCD_R6/PH123.3 VOLCD data red6
A45X_LCD_R7/PE153.3 VOLCD data red7
A47X_LCD_G2/PH133.3 VOLCD data green2
A48X_LCD_G3/PE113.3 VOLCD data green3
A49X_LCD_G4/PH153.3 VOLCD data green4
A50X_LCD_G5/PH43.3 VOLCD data green5
A51X_LCD_G6/PI113.3 VOLCD data green6
A52X_LCD_G7/PI23.3 VOLCD data green7
B42X_LCD_B2/PG103.3 VOLCD data blue2
B43X_LCD_B3/PG113.3 VOLCD data blue3
B44X_LCD_B4/PE123.3 VOLCD data blue4
B45X_LCD_B5/PI53.3 VOLCD data blue5
B46X_LCD_B6/PB83.3 VOLCD data blue6
B47X_LCD_B7/PD83.3 VOLCD data blue7
B49X_LCD_HSYNC/PI103.3 VOLCD horizontal sync
B50X_LCD_VSYNC/PI93.3 VOLCD vertical sync
B51X_LCD_DE/PE133.3 VOLCD data enable
B52X_LCD_CLK/PG73.3 VOLCD clock

 Parallel Display Interface Signal Locations

Note

All parallel display signals are available as alternate functions at other pins of the phyCORE‑Connector, too. Hence, by changing the pin muxing and the device tree even a full 24-bit parallel display interface can be implemented. Further information about other ports and therefore other pins of the phyCORE‑STM32MP1 providing signals of the display interface can be found in the STM32MP15x datasheet.

Supplementary Signals

In addition, signal X_LCD_BL_PWM/PI0 can be used as PWM output to control the display backlight.

The STM32MP1 embeds an HDMI-CEC controller that provides hardware support for the consumer electronics control (CEC) protocol. Te HDMI-CEC signal is available at the phyCORE‑Connector and can be used together with the parallel RGB display signals to build an HDMI interface with CEC feature. 

The table below shows the location of the two supplementary signals on the phyCORE‑Connector.

SOM  Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A58X_LCD_BL_PWM/PI03.3 VOPWM output (e.g. to control a backlight)
B58X_SPI1_NSS/PA153.3 VI/O

HDMI-CEC[6]

Supplementary Signals to support the Display Connectivity

6.

To use the HDMI-CEC signal a 27 kΩ resistor must be added externally.

MIPI DSI (Display Serial Interface)

If the phyCORE‑STM32MP1 is equipped with an STM32MP157x  microprocessor a MIPI DSI interface with 2 data lanes up to 1 GHz each is also available to connect a display to the module. The table below shows the locations of the MIPI display interface signals on the phyCORE‑Connector.

SOM  Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A1X_MIPI_DSI_CLKN1.2 VDSI_OMIPI DSI clock negative output
A2X_MIPI_DSI_CLKP1.2 VDSI_OMIPI DSI clock positive output
A4X_MIPI_DSI_DATA0N1.2 VDSI_OMIPI DSI data0 negative output
A5X_MIPI_DSI_DATA0P1.2 VDSI_OMIPI DSI data0 positive output
A7X_MIPI_DSI_DATA1N1.2 VDSI_OMIPI DSI data1 negative output
A8X_MIPI_DSI_DATA1P1.2 VDSI_OMIPI DSI data1 positive output
A9X_MIPI_DSIHOST_TE/PD133.3 VIMIPI DSI tearing effect input

MIPI DSI Signal Locations at X1

Tip

Connecting a MIPI-DSI to FlatLink (LVDS) converter to the MIPI display interface on a custom carrier board leads to a larger selection of displays and the possibility to connect cheaper displays.

Parallel Camera Interface (DCMI)

The STM32MP1 offers one synchronous parallel camera interface (DCMI) that can receive high-speed data flows with up to 14 data lines (D13-D0) and a pixel clock line (DCMI_PIXCLK) with a programmable polarity so that data can be captured on either the rising or the falling edge of the pixel clock.

On the phyCORE‑STM32MP1  the camera interface is brought out as parallel interfaces with 10 data bits, HSYNC, VSYNC, and PIXCLK. The upper DCMI data bits D13... D10 are used for other features of the phyCORE‑STM32MP1.

The locations of the parallel camera interface signals are shown below:

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A30X_DCMI_HSYNC/PH83.3 VIDCMI Horizontal synchronization / Data valid
A31X_DCMI_VSYNC/PB73.3 VIDCMI Vertical synchronization
A32X_DCMI_PIXCLK/PA63.3 VIDCM Pixel clock
A34X_DCMI_DATA5/PI43.3 VIDCMI data5
A35X_DCMI_DATA6/PE53.3 VIDCMI data6
A36X_DCMI_DATA7/PI73.3 VIDCMI data7
A37X_DCMI_DATA8/PI13.3 VIDCMI data8
A38X_DCMI_DATA9/PH73.3 VIDCMI data9
B36X_DCMI_DATA0/PH93.3 VIDCMI data0
B37X_DCMI_DATA1/PC73.3 VIDCMI data1
B38X_DCMI_DATA2/PE03.3 VIDCMI data2
B39X_DCMI_DATA3/PE13.3 VIDCMI data3
B40X_DCMI_DATA4/PH143.3 VIDCMI data4

Parallel Camera Interface Signal Locations

Note

All parallel camera interface signals, including DCMI data bits D13... D10,  are available as alternate functions at other pins of the phyCORE‑Connector, too. Hence, by changing the pin muxing and the device tree even a full 14-bit parallel camera interface can be implemented. Further information about other ports and therefore other pins of the phyCORE‑STM32MP1 providing signals of the camera interface can be found in the STM32MP15x datasheet.

Tip

Using the phyCORE's parallel camera interface DCIM, together with an I²C bus, an additional clock and a GPIO facilitates easy implementation of a CMOS camera interface compliant with PHYTEC's camera interface standards phyCAM-P or phyCAM-S+ (requires an external deserializer) on a custom carrier board.

Real-Time Clocks (RTCs)

For real-time or time-driven applications, the phyCORE-STM32MP1 provides two RTCs. Besides the internal RTC of the STM32MP1, the phyCORE-STM32MP1 has an external RTC mounted at U13.

The RTCs are supplied by the main system power if available. When the main system power is off they can also be powered by a secondary voltage source of 1.8 V to 3.6 V (typ. 3 V) connected to VBAT (D57). The VBACKUP input of the external RTC is permanently connected to VBAT while jumper J5 must be closed at 2+3 to connect the STM32MP1's VBAT input, too. 

RTC of the STM32MP1

The signals of the STM32MP1's on-chip RTC are available at phyCORE-Connector X1. 

The following table lists the signals of the RTC  on the phyCORE-Connector:

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

A12X_SDMMC2_DATA1/PB153.3 VIRTC 50 or 60 Hz reference clock input
A54X_UART4_RX/PB23.3 VORTC output 2
B60X_PI83.3 VO

RTC output 2[7]/ RTC low-speed clock output

C27X_DFSDM1_CKOUT/PD103.3 VIRTC 50 or 60 Hz reference clock input
D53X_WAKEUP3/PC133.3 VI/O

RTC output 1[7]/ RTC timestamp input[7]
RTC low-speed clock output[7]

STM32MP1 RTC Interface Signal Locations at X1

Note

As can be seen from the signal names, by default most RTC pins are assigned to other functions within the included BSP. Thus the pin muxing must be changed and the device tree must be adapted in order to use the RTC's signals.

7.

These signals are also available in VBAT mode.

External RTC (U13)

The standard configuration of the SOM provides an additional, external RTC at U13. The newest generation of RTC from Micro Crystal is characterized by an extremely low backup current of only 40 nA. As the external RTC uses less power than the STM32MP1's internal RTC ( > 1 μA) it is recommended to be used for applications that require backing-up the RTC for a long time.

In a normal operation state, the RTC power is supplied from the SOM voltage VDD.

To back up the external RTC when the main supply voltage VDD is not available, a secondary voltage source of 1.8 V to 3.6 V (typ. 3.3 V) must be attached to the phyCORE‑STM32MP1 at VBAT pin D57.

In order to get the minimum power consumption to back up the RTC while the main supply voltage is not available, jumper J5 must be closed at 1+2 (default configuration). Otherwise, the STM32MP1's backup domain Vsw will also be supplied by the backup voltage source.

The RTC is programmed via I2C4 at address 0x52.

All three signals of the RTC (clockout, external event input, and interrupt output) are available at the phyCORE-Connector

SOM Connector Pin

SOM Signal Name

Signal Level

Signal Type

Description

C48X_RTC_EVI3.3 VI-PDExternal event input; 10 kΩ pull-down; remains active also in VBACKUP power state.
C49X_nRTC_INT3.3 VODInterrupt output; open-drain; active low; requires a pull-up resistor
C50X_RTC_CLKOUT3.3 VOClock output; low in VBACKUP power state.
D57VBAT1.8 V - 3.6 VPWR_I3 V  / <1 µA RTC Backup Supply 

RTC Signal Locations at X1

Technical Specifications

The physical dimensions of the phyCORE-STM32MP1 are represented in the figures phyCORE-STM32MP1 Mechanical Dimensions (profile view) and phyCORE-STM32MP1 Mechanical Dimensions (top view). The module’s profile is approximately 4.8 mm thick from the tallest component on the top to the tallest component on the bottom (excluding the phyCORE connectors). The maximum component height (excluding connectors X1 and X2) is approximately 1.25 mm on the bottom (connector) side of the PCB and approximately 2 mm on the top (microcontroller) side. The PCB is approximately 1.55 mm thick. The distance from the surface of the carrier board to the highest component on the top side of the board is approximately 8.55 mm.

phyCORE-STM32MP1 Mechanical Dimensions (profile view)

phyCORE-STM32MP1 Mechanical Dimensions (top view)

Tip

To facilitate the integration of the phyCORE‑STM32MP1 into your design, the footprint of the phyCORE‑STM32MP1 can be downloaded (Integrating the phyCORE-STM32MP1).

Additional specifications:

Dimensions:40 mm x 44 mm x 4.8 mm (excluding the phyCORE‑Connectors)
Weight:11.3 g
Storage Temperature:-40 °C to +125 °C
Operating Temperature:

Refer to Product Temperature Grades

Humidity:95 % r.F. not condensed
Operating Voltage:5 V +/- 5%         
Power Consumption:2.2 W (typ)

Technical Specifications

These specifications describe the standard configuration of the phyCORE‑STM32MP1 as of the printing of this manual.

phyCORE-STM32MP1 Power Consumption

The values listed in the table below are a guideline to determine the required dimensions of the power supply circuitry on a carrier board. They do not take application-specific load situations into account. These values have been generated by looking at the maximum power consumption measured using different load scenarios and adding a voltage source of 5 V. These values are based on internal PHYTEC testing. Customers need to consider their application power requirements to ensure they do not generate a load greater than the values listed here. 

Maximum Power Requirements3 W without external load
Required Supply Voltage (VCC5V_IN)4.75 V to 5.5 V  / 3 A
Ramp-Up Time< 1 sec.
Backup Supply Voltage (VBAT)

1.2 V to 5.5 V / 1 uA (ULP-RTC only,)
1.4 V to 3.6 V / 2.5 mA (with STM32MP1 VBAT Supply)

phyCORE-STM32MP1 Power Consumption

Additionally, there are some values that cannot be tested. Situations such as suspending to RAM, suspend freeze, and standby mode must be tested on a case by case basis to ensure the application's power consumption stays within the guideline stated above.

Tip

For further information and assistance regarding your application's power consumption, please contact PHYTEC sales.

Product Temperature Grades

Warning

The right temperature grade for the module greatly depends on the use case. It is necessary to determine if the use case suits the temperature range of the chosen module (see below). A heat spreader can be used if temperature compensation is required.

The feasible operating temperature of the SOM highly depends on the use case of your software application. Modern high-performance microcontrollers and other active parts as the ones described within this manual are usually rated by qualifications based on tolerable junction or case temperatures. Therefore, making a general statement about minimum or maximum ambient temperature ratings for the described SOM is not possible.

However, the above-mentioned parts are available in different temperature qualification levels by the producers. We offer our SOM's in different configurations, making use of those temperature qualifications. To indicate which level of temperature qualification is used for active and passive parts of a SOM configuration, we have categorized our SOMs into three temperature grades.

The table below describes these grades in detail. These grades describe a set of components that, in combination, add up to a useful set of product options with different temperature grades. This enables us to make use of cost optimizations depending on the required temperature range.

In order to determine the right temperature grade and whether the minimum or maximum qualification levels are met within an application, the following conditions must be defined by considering the use case:

  • Determined the processing load for the given software use case
  • Maximum temperature ranges of components (see table below)
  • Power consumption resulting from a baseload and the calculating power required (in consideration of peak loads as well as time periods for system cooldown)
  • Surrounding temperatures and existing airflow in case the system is mounted into a housing
  • Heat resistance of the heat dissipation paths within the system along with the considered usage of a heat spreader or a heat sink to optimize heat dissipation

Product Temperature
Grade

Controller  Temperature Range
(Junction Temperature)

RAM
(Case Temperature)
Other
(Ambient)

I

Industrial:     -40 °C to +125 °C 

Industrial: -40 °C to +95 °C

Industrial: -40°C to +85 °C

X

Extended Commercial:  -20 °C to +105 °C

Industrial: -40 °C to +95 °C

Industrial: -40 °C to +85 °C

C

Commercial: 0 °C to +95 °C

Consumer: 0 °C to +95 °C

Consumer: 0 °C to +70 °C

Product Temperature Grades

Connectors on the phyCORE-STM32MP1


ManufacturerSamtec
phyCORE-Connector (X1)
Number of pins per contact rows 240 pins (4 rows of 60 pins each)
Samtec part number (lead-free)REF-177857-02
PHYTEC part number (lead-free)VB211
Height5 mm

Information on the receptacle sockets that correspond to the connectors populating the underside of the phyCORE-STM32MP1 is provided below. The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board. In order to get the exact spacing, the maximum component height (1.25 mm) on the bottom side of the phyCORE must be subtracted.

Mating Connector

ManufacturerSamtec
phyCORE-Connector (X1)
Number of pins per contact rows 240 pins (4 rows of 60 pins each)
Samtec part number (lead-free)REF-177862-03
PHYTEC part number (lead-free)VM240
Height5 mm

Please refer to the corresponding data sheets and mechanical specifications provided within the category Module Connector in the download section of the phyCORE-STM32MP1 web page.

Hints for Integrating and Handling the phyCORE‑STM32MP1

Integrating the phyCORE-STM32MP1

Design Rules

Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, we recommend as a general design rule to connect all GND pins to a solid ground plane. But at least all GND pins neighboring signals which are being used in the application circuitry should be connected to GND.

Additional Information and Reference Design

Besides this hardware manual, more information is available to facilitate the integration of the phyCORE‑STM32MP1 into customer applications.

  1. The design of the phyBOARD Sargas STM32MP1 can be used as a reference for any customer application.
  2. Many answers to common questions can be found at https://www.phytec.de/produkt/system-on-modules/phyCORE‑STM32MP1-download/or https://www.phytec.eu/product-eu/system-on-modules/phyCORE‑STM32MP1-download/
  3. The links within the categories Dimensioned Drawing and Altium lead to the layout data as shown in the imagebelow. The use of this data allows the phyCORE‑STM32MP1 SOM to be integrated into your design as a single component.
  4. Different support packages are available for support in all stages of embedded development. Please visithttps://www.phytec.de/support/ueberblick/ or https://www.phytec.eu/support/support-packages/or contact our sales team for more details.
  5. Many answers to common questions can be found at:
  6. https://www.phytec.de/produkt/system-on-modules/phycore-stm32mp1/
    or
    https://www.phytec.eu/product-eu/system-on-modules/phycore-stm32mp1/

Footprint of the phyCORE-STM32MP1

Handling the phyCORE-STM32MP1

phyCORE Module Modifications

The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station, or other desoldering methods is strongly recommended.  Please carefully follow the instructions for the method of removal chosen.

Warning

If any modifications to the module are performed, regardless of their nature, the manufacturer guarantee is null and void.

phyCORE-STM32MP1 on the phyBOARD-Sargas SBC

Hardware Overview

The phyBOARD-Sargas STM32MP1 single-board computer (SBC) for phyCORE-STM32MP1 is a low-cost, feature-rich software development platform supporting the STMicroelectronics STM32MP1 microcontroller. Due to numerous standard interfaces, the phyBOARD-Sargas STM32MP1 can serve as the bedrock for any application. At the core of the phyBOARD-Sargas is the PCM-068/phyCORE-STM32MP1 System On Module (SOM) containing the processor, DDR3L RAM, eMMC Flash, power regulation, supervision, and other core functions required to support the STM32MP1 processor. Surrounding the SOM is the PCM-939/phyBOARD-Sargas STM32MP1, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals.

The PCM-068 System On Module connects to the phyBOARD-Sargas STM32MP1 by using two high-density connectors. 

phyBOARD-Sargas Single Board Computer Concept

PHYTEC Single Board Computers (phyBOARDS) are fully equipped with all mechanical and electrical components necessary for a fast, secure start-up. Subsequent communication to and programming of applicable PHYTEC System on Modules (SOM) is made easy. phyBOARDs are designed for evaluation, testing, and prototyping PHYTEC System on Modules in laboratory environments prior to their use in customer designed applications.

This modular development platform concept includes the following components:

  • The phyCORE-STM32MP1 Module populated with the STM32MP1 microcontroller and all applicable SOM circuitry such as LPDDR3 SDRAM, eMMC-Flash, Ethernet-PHY, and PMIC, etc.
  • The phyBOARD-Sargas Carrier Board offers all essential components and connectors for a start-up including interface connectors such as USB, Ethernet, or Audio which enable the use of the SOM’s interfaces with a standard cable.

The carrier board can also serve as a reference design for developing custom target hardware in which the phyCORE SOM can be deployed. Carrier board schematics are available under a Non-Disclosure Agreement (NDA). Reuse of carrier board circuitry enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

SBCplus Concept

The SBCplus concept was developed to meet the many, small differences in customer requirements with little development effort. This greatly reduces the time-to-market. The core of the SBCplus concept is the SBC design library (a kind of construction set) that consists of a large number of function blocks (so-called "building blocks") which are continuously being refined and updated.

Recombining these function blocks allows PHYTEC to develop a customer-specific SBC within a short time. We are able to deliver production-ready custom Single Board Computers within a few weeks at very low costs. The already developed SBCs, such as the phyCORE-STM32MP1 carrier board, each represent a combination of different customer wishes. This means all necessary interfaces are already available on the standard versions, allowing PHYTEC SBCs to be integrated into a large number of applications without modification.

For any necessary detail adjustment, extension connectors are available which allow a wide variety of functions to be added.

phyBOARD-Sargas Features

The phyBOARD -Sargas STM32MP1 supports the following features:

  • Developed in accordance with PHYTEC's SBCplus concept (SBCplus Concept)
  • Populated with PHYTEC’s phyCORE-STM32MP1 SOM
  • Dimensions of 160 mm × 100 mm
  • Boot from eMMC, SD Card, NAND, NOR, over USB OTG (DFU mode), or over UART
  • 9-28 VDC power supply or USB-C 5V Supply
  • One RJ45 jack for 10/100/1000 Mbps Ethernet
  • One USB 2.0 host interface brought out to an upright USB Standard-A connector. 
  • One USB OTG interface available at a USB Micro-AB connector
  • One USB Debug interface (UART-USB FTDI converter)
  • One Secure Digital / MultiMedia Memory Card interface brought out to a Micro-SD connector
  • One phyCAM-P interface (PHYTEC parallel camera interface)
  • One MIPI DSI interface (compatible with Raspberry PI MIPI DSI pinout connector)
  • One LCD RGB 18-bit interface (to connect PHYTEC PEB-AV module)
  • One micro MEMS specific connector interface (to connect PHYTEC MEMS Array board)
  • One CAN FD transceiver (data rates up to 5 Mbit/s in the CAN FD fast phase)
  • One RS-232 or RS-485 transceiver supporting USART1 including handshake signals with data rates of up to 1 Mbps (2×5 pin header 2.54 mm)
  • One CryptoAuthentication Device
  • Reset button
  • ON/OFF/Wakeup button
  • Two user buttons
  • One multicolor LED
  • Audio Codec (Mono Speaker output, Stereo Headset and Line in/out)
  • One JTAG interface
  • Goldcap Backup supply for RTC
  • Expansion connectors for different interfaces:
    • Raspberry Pi HAT 
    • Arduino Shield
    • Motor Control
    • Expansion (PHYTEC specific)
    • Audio/Video (PHYTEC specific)

Block Diagram


phyBOARD-Sargas STM32MP1 Block Diagram

phyBOARD-Sargas STM32MP1 Components

Note

For easy reference, Pin 1 for each component has been highlighted.

phyBOARD-Sargas Component Placement Diagram

phyBOARD-Sargas Components

phyBOARD-Sargas Components

phyBOARD-Sargas Component Overview

The phyBOARD-Sargas STM32MP1 features many different interfaces and is equipped with the components listed in the table Connectors and Pin Headers. For a more detailed description of each component, refer to the appropriate section listed in the table below. The image phyBOARD-Sargas Componentshighlights the location of each component for easy identification.

Connectors and Pin Headers

The table below lists all available connectors on the phyBOARD-Sargas.

Reference Designator

Description

Section

X1phyCORE-Connector (Samtec 2 x 60 pins, 0.5 mm pitch)phyCORE-STM32MP1 SOM Connector
X2USB host connector (USB 2.0 Standard-A)USB
X3Arduino Shields Connector (socket connector, 2.54 mm pitch)Arduino Shields Connector
X4phyCAM-P camera connector (33-pin Hirose FFC-connector, 0.5 mm pitch)Camera
X5Mono Speaker output (2-pole Molex SPOX, 2.5 mm pitch)Audio Connectivity

X5VIN

USB-C 5V Standard Supply voltage input5V USB-C Supply Voltage Input
X6External Backlight Power (1×2 pin header, 2.54 mm pitch)External Backlight Power
X7Raspberry Pi HAT Connector (2×20 pin header, 2.54 mm pitch)Raspberry Pi HAT
X8JTAG (2×10 pin header, 2.54 mm pitch)JTAG
X99V-28V DC Supply voltage input (Phoenix Socket)
9 V to 28 V Supply Voltage
DCIN19V-28V DC Supply voltage input (DC10 Power Socket)
X12USB On-The-Go connector (USB Micro-AB)USB
X13Debug USB (USB Micro-AB)USB Debug
X14microSDHC card slotSecure Digital Memory/ MultiMedia Card
X19Connector for external Backup Battery (1×2 pin header, 
2.54 mm pitch)
VBAT
X20Microphone Array Board Connector (2x10 pin header, 1.27 mm pitch)Microphone Array Connector
X24Audio/ Video 2 (2×8 dual entry socket, 2 mm pitch)
Audio/Visual Connectors
X25Audio/ Video 1 (2×20 dual entry socket, 2 mm pitch)
X26Stereo Line Output (3,5mm Stereo Audio Jack)

Audio Connectivity
X27Stereo Line Input (3,5mm Stereo Audio Jack)
X28Headset (3,5mm Stereo Audio Jack)
X33Expansion Connector (2×30 socket, 2mm pitch)Expansion Connector
X35RS485 / RS232  (2x5 pin header, 2.54 mm pitch)RS232 / RS485 Connector
X36CAN FDCAN2 (2x5 pin header, 2.54 mm pitch)CAN FD
X38Motor Control Connector (2×17 pin header, 2.54 mm pitch)Motor Control Connector
X41MIPI-DSI Connector (20 position FPC, 1 mm pitch)MIPI-DSI
X47Ethernet Connector (10/100/1000 Base-T RJ45 with Integrated magnetic and LED)Ethernet

phyBOARD-Sargas Connectors and Pin Header

Warning

Ensure that all module connections do not exceed their expressed maximum voltage or current. Maximum signal input values are indicated in the corresponding controller User's Manual/Data Sheets. As damage from improper connections varies according to use and application, it is the user‘s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals.

LEDs

The phyBOARD-Sargas is populated with oneprogrammable RGBLED.  See Multicolor (RGB) LED (D11) for more information.

LED

Color

Description

Section

D11RGBUser-programmable RGB LEDMulticolor (RGB) LED

 phyBOARD-Sargas LED Descriptions

Switches

The phyBOARD-Sargas is populated with several switches. The table below shows their functions.

SwitchDescriptionSection
S1System ResetSystem Reset
S2System ON/OFF/Wake-upSystem Wake-up
S4User 1User Programmable Buttons
S5User 2
S7Boot SelectionBoot Switch

phyBOARD-Sargas Switch Descriptions

Jumpers

phyBOARD-Sargas Jumper Locations

phyBOARD-Sargas Jumper Locations

The phyBOARD-Sargas comes pre-configured with several jumpers (JP). The jumpers enable the flexible configuration of a limited number of features for development purposes. The table below shows the function of each jumper.

ReferencePositionDescriptionSection
JP1closed120 Ohm termination resistor installed on the CAN bus
CAN FD
openno termination resistor

JP2

closedU3 output (5V/3A) connected to VCC5V_IN



5V USB-C Supply Voltage Input

openU3 output (5V/3A)  not used

JP3

closedU4 output (3.3V/3A) connected to VCC3V3_IN
openU4 output (3.3V/3A)  not used
JP41+2 X_USART1_RX/PZ6 connected to RS232 transceiver (U14)RS232 / RS485 Connector

2+3 X_USART1_RX/PZ6 connected to RS485 transceiver (U18)
JP51+2 X_USART1_TX/PZ7 connected to RS232 transceiver (U14)RS232 / RS485 Connector

2+3 X_USART1_TX/PZ7 connected to RS485 transceiver (U18)
JP61+2 VCC_BL connected to VINExternal Backlight Power Connectivity
2+3 VCC_BL connected to X_VBL (opt. ext. BCKL power on X6)
JP16closed

 X_USART3_RX/PB12 & X_USART3_TX/PB10 connected to X3 and X33

Debugging Connectivity
-----
Arduino Shields Connectivity
-----

Expansion Connector

open

X_USART3_RX/PB12 & X_USART3_TX/PB10 connected to 2nd Debug FTDI (U7) port, if USB cable plug on X13, else connected on X3 and X33

JP181+23V3 from U4 L7986 (Carrier Board)


Power

2+3

3V3 from VDD_BUCK4 (SOM)

JP251+2X_FDCAN2_TX/PB13 connected to X33

CAN FD
-----
Expansion Connector

2+3X_FDCAN2_TX/PB13 connected to CAN FD transceiver (U15)
JP261+2X_FDCAN2_RX/PB5 connected to X33CAN FD
-----
Expansion Connector
2+3X_FDCAN2_RX/PB5 connected to CAN FD transceiver (U15)
JP271+2X_I2C1_SDA/PF15 connected to X3Arduino Shields Connectivity
-----
I2C5/I2C6 Interface
2+3X_USART1_RTS/PA12 connected to X3
JP281+2X_I2C1_SCL/PF14 connected to X3Arduino Shields Connectivity
-----
I2C5/I2C6 Interface
2+3X_USART1_CTS/PA11 connected to X3

JP29

closedLevel Shifter (U2) enabled (needed when using phyCAM-P)Camera Connectivity
openLevel Shifter (U2) disabled
JP30
closedX_USART1_CTS/PA11 connected to RS232 transceiver (U14)RS232 / RS485 Connector
openX_USART1_CTS/PA11 not connected to RS232 transceiver

JP31

closedX_USART1_RTS/PA12 connected to RS232 (U14) & RS485 transceiver (U18)RS232 / RS485 Connector
openX_USART1_RTS/PA12 not connected to RS232 (U14) & RS485 transceiver (U18)

phyBOARD-Sargas Jumper Descriptions

Warning

Due to the small footprint of the solder jumpers (J), PHYTEC does not recommend manual jumper modifications. This may also render the warranty invalid. Only the removable jumper (JP) is described in this section. For information on the solder jumpers, see Soldering Jumpers. Contact our sales team if you need jumper configurations different from the default configuration.

phyBOARD-Sargas Component Details

This section provides a more detailed look at the phyBOARD-Sargas components. Each subsection details a particular connector/interface and associated jumpers for configuring that interface.

Tip

When possible, we also provide any useful information regarding design consideration for components. This can be used if you plan to design your own carrier board.

phyCORE-STM32MP1 SOM Connector (X1)

phyCORE Connection (X1)

phyCORE Connection (X1)

Power (X9, DCIN, X5VIN, X19)


Warning

Do not change modules or jumper settings while the phyBOARD-Sargas is supplied with power!

Powering Scheme

Powering Scheme

The phyBOARD-Sargas can be supplied with power through 3 different ways: on X9, DCIN, or X5VIN (5V USB-C Supply). The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE mounted on the phyBOARD-Sargas, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board.

9 V to 28 V Supply Voltage Inputs (X9, DCIN)

Warning

Please note the polarity of the power component X9 and DCIN jack. Ensure that your power adapter is correctly set up to use the polarity as shown below.

phyCORE-STM32MP15x carrier board Polarity

The board can be supplied by standard 12VDC or 24VDC adapter either on X9 or DCIN connector. A 24VDC adapter with a minimum supply of 1A is recommended. X9 is a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector. DCIN is a barrel jack connector (DC Power socket).

Interface Pin #
Signal
Signal Type Signal Level

Description

1X_VINPWR_I9-28VphyBOARD Power Supply
2GND_IN--Ground

X9 and DCIN Pin Assignment

Note

The phyBOARD-Sargas is equipped with two step-down switching regulator (L7986) when using 9-28V as power input:

  • U3: 5V/3A max to supply the phyCORE-STM32MP1 (VCC5V_IN) and the 5V phyBOARD-Sargas components (VCC5V)
  • U4: 3.3V/3A max to supply all the 3.3V phyBOARD-Sargas components (VCC3V3)

Tip

For power consumption consideration, instead of using the phyBOARD 3.3V supply from U4, it is possible to use 3.3V from VDD_BUCK4 coming from the SOM. In this case, JP18 must be changed to JP18=2+3.

5 V USB-C Supply Voltage Input (X5VIN)

The board can also be supplied by standard 5 V USB-C cable on X5VIN (female USB-C connector), instead of using 9 V-28 V supply on X9 or DCIN connectors. On this standard USB-C connector, only the power signals are connected. Data signals are not connected.

Warning

To power the board using the USB-C connector, the following jumper settings must be set:

  • JP18 = 2+3: VCC3V3 is supplied from VDD_BUCK4 (SOM)
  • Remove jumpers on JP2 and JP3 so to disconnect the unused 5V/3V3 Regulators of the phyBOARD (U3+U4)

VBAT (X19)

To back up the RTC on the module, a secondary voltage source of 1.8 V to 3.6 V (typ. 3.0 V) can be attached to the phyCORE-STM32MP1 at pin X1D57. This voltage source supplies the backup voltage domain VBAT of the STM32MP1, as well as the module's external RTC when the primary system power (VCC5V_IN) is removed.

The phyBOARD-Sargas is equipped with a rechargeable backup battery at C199. If the backup battery is not installed at C199, connector X19 can serve as a connector for an external backup source. The pinout of the 1x2-pin header connector (2.54 mm pitch) is the following.

Interface Pin #SignalSignal TypeSignal LevelDescription
1VBATPWR_I

1.8 V to 3.6 V (typ. 3.0 V)

external backup voltage
2GND--Ground

X19 Pin Assignment

Ethernet (X47)

Ethernet Connector (X47)

Ethernet Connector (X47)

The phyBOARD-Sargas is equipped with an RJ45 connector supporting a 10/100/1000Base-T network connection. The LEDs for LINK (green) and SPEED (yellow) indication are integrated into the connector. The Ethernet transceiver supports Auto MDI-X, eliminating the need for a direct connect LAN or cross-over path cable. They detect the TX and RX pins of the connected device and automatically configure the PHY TX and RX pins accordingly.

Ethernet Design Consideration

The data lanes should be routed with a differential impedance of 100 Ohm. The center taps of each pair's transformer have to be connected to GND through a 100nF capacitor. The X_ETH_LED signals are open-drain outputs of the SOM without resistors, so they should be connected to the cathodes of the LEDs through a resistor.

USB (X2, X12)

USB Connectors (X2 and X12)

USB Connectors (X2 and X12)

The phyBOARD-Sargas is equipped with two USB 2.0 interfaces:

  1. One USB Host on X2 (USB Type A)
  2. One USB OTG on X12 (USB micro-AB). USB OTG devices are capable of initiating a session, controlling the connection, and exchanging host and peripheral roles between each other. 

USB Design Consideration

The data lanes should be routed with a differential impedance of 90 Ohm.

Secure Digital Memory/ MultiMedia Card (X14)

microSDHC card slot (X14)

The phyBOARD-Sargas provides a standard microSDHC card slot at X14 for use microSD-Cards. It features card detection, a lock mechanism, and a smooth extraction function by pushing the card in and out. DIP switch S7 provides a toggle between SD card Boot and other Boot modes (refer to Boot Switch for further information).

SD / MM Card Design Considerations

  • Series resistors might be required to adapt the drive strength of the card and the SOM output. The trace length between CLK, CMD, and DATA lanes should be matched. 
  • 10k pull-ups are also necessary on the command line and the data lines.
  • The SDMMC signals for the SD card should be routed with a 50 Ohm impedance.

phyCAM-P Camera Connector (X4)

phyCAM-P Camera Connector (X4)

phyCAM-P Camera Connector (X4)

The phyBOARD-Sargas provides one parallel interface for camera connectivity at connector X4 (33-pin Hirose FFC-connector, 0.5 mm pitch).

The parallel version of the phyCAM interface offers an extremely simple and cost-effective way to integrate the camera into a system. The data and control signals are transmitted in parallel via a 33-pin FFC cable. This reduces the interface effort to a minimum and still enables compatibility of the camera types. Reserved pins allow access to special functions such as trigger input or light control. Image data can be transferred with up to 10-bit grayscale resolution or color depth.

phyCAM-P is particularly suitable for the device-internal installation of cameras. The cable length can be up to 30 cm.

General information and design guidelines about phyCAM-P can be found on our specific website page: https://www.phytec.eu/products/embedded-imaging/phycam-embedded-camera-modules/

Note

A Level Shifter (U2) is populated on the phyBOARD to adapt the DCMI signal levels between the phyCAM-P and the phyCORE. By default, this Level Shifter is not enabled. To enable it, JP29 must be populated. 

Note

The table below describes the camera signals when using the phyCAM-P BSP feature. By default, this feature is not enabled (not supported by BSP yet). Currently, every X_DCMI signal is configured as GPIO by default.

Interface Pin #

Signal Name

phyCORE Signal Name (before/after Level Shifters)Signal TypeSignal Level

Description

Jumper setting
1VCC_CAM-PWR_O3.3V/2.8V/1.8V

Power Supply[8]

-
2VCC_CAM_PG-AnalogVCC_CAMVCC_CAM power good signal-
3CAM_VSET-Analogcf. phyCAM datasheet

Power Voltage Set[8]

-
4CAM_CTRL2-I/OVCC_CAMControl Signal 2 left opened or to connected to Ground or VCC_CAMJ4 open
5CAM_MCLK-OVCC_CAM

27Mhz Camera Master Clock coming from oscillator OZ1 (+ level shifter U6)

J3 2+3
X_MCO2/PG2OVCC_CAM27Mhz Camera Master Clock coming from X_MCO2/PG2 (+ level shifter U6)J3 1+2
6GND---Ground-
7CAM_PCLKX_DCMI_PIXCLK/PA6IVCC_CAMCamera Pixel Clock-
8GND---Ground-
9CAM_DD0X_DCMI_DATA0/PH9IVCC_CAMCamera Signal 0-
10CAM_DD1X_DCMI_DATA1/PC7IVCC_CAMCamera Signal 1-
11GND---Ground-
12CAM_DD2X_DCMI_DATA2/PE0IVCC_CAMCamera Signal 0-
13CAM_DD3X_DCMI_DATA3/PE1IVCC_CAMCamera Signal 0-
14GND---Ground-
15CAM_DD4X_DCMI_DATA4/PH14IVCC_CAMCamera Signal 0-
16CAM_DD5X_DCMI_DATA5/PI4IVCC_CAMCamera Signal 0-
17GND---Ground-
18CAM_DD6X_DCMI_DATA6/PE5IVCC_CAMCamera Signal 0-
19CAM_DD7X_DCMI_DATA7/PI7IVCC_CAMCamera Signal 0-
20GND---Ground-
21CAM_DD8X_DCMI_DATA8/PI1IVCC_CAMCamera Signal 0-
22CAM_DD9X_DCMI_DATA9/PH7IVCC_CAMCamera Signal 0-
23GND---Ground-
24CAM_LVX_DCMI_HSYNC/PH8IVCC_CAMCamera HSYNC Signal-
25CAM_FVX_DCMI_VSYNC/PB7IVCC_CAMCamera VSYNC Signal
26GND---Ground-
27CAM_CTRL1-
VCC_CAMControl Signal 1 connected to Ground or to VCC_CAMJ5 1+2
28CAM_I2C_SCLX_I2C1_SCL/PF14OVCC_CAMI2C1 clock Signal (with I2C buffer U13)-
29CAM_I2C_SDAX_I2C1_SDA/PF15I/OVCC_CAMI2C1 data Signal (with I2C buffer U13)-
30GND---Ground-
31VCC_CAM_PG--VCC_CAMVCC_CAM power good signal
32VCC_CAM-PWR_O3.3V/2.8V/1.8VPower Supply-
33VCC_CAM-PWR_O3.3V/2.8V/1.8VPower Supply-
34, 35Not Connected-----

X4 Pin Assignment

8.

The supply voltage VCAM can be different for various camera modules (3.3V/2.8V/1.8V). Please refer to the detailed descriptions of specific phyCAMs. The phyBOARD-Sargas is equipped with an adaptive power supply (U5). Reading the resistance value of pin 31, the phyCAM-P detect configures the phyBOARD voltage regulator with the CAM_VSET pin.


phyCAM-P camera Design Consideration

The DCMI signals should be routed with a 50 Ohm impedance.

CAN FD (X36)


CAN FDCAN1 Connector (X36)

CAN FD Connector (X36)

The phyBOARD-Sargas is equipped with a CAN FD transceiver at U15 connected to the STM32MP1 FDCAN2 interface. The CAN bus is available at X36 (2x5 pin header; 2.54mm pitch). A 120 Ohm resistor (R141) is present on the CAN bus when the JP1 jumper is populated. This resistor is not present when JP1 is removed. 

The CAN with Flexible Data-Rate (CAN FD) is an updated extension of the original CAN protocol. This enables extra data bytes and flexible bit rates. In general, the CAN FD offers 3 benefits to regular CAN:

  1. Increased Data Length
    CAN FD supports up to 64 data bytes per data frame vs. 8 data bytes for regular CAN.
  2. Increased Speed
    CAN FD supports dual bit rates: normal 1Mbit/s bit rate of a regular CAN and data bit rates up to 5Mbit/s, depending on network and transceiver types. TJA1051T/3 transceiver (U15) on the phyBOARD-Sargas supports data bit rates up to 5Mbit/s
  3. Improved Reliability
    CAN FD uses an improved cyclic redundancy check (CRC), lowering the risks of undetected errors.

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

Jumper setting
1Not Connected---
2GND--Ground
3X_CANLCAN_I/O LowCAN standard

Negative CAN lane

JP25/JP26 2+3
4X_CANHCAN_I/O HighCAN standardPositive CAN laneJP25/JP26 2+3
5GND--Ground
6, 7, 8, 9, 10Not Connected---

X36 Pin Assignment

An adapter cable (pin header to DB9 male connector) can be plugged on X36 to facilitate the use of the CAN FD interface. The following figure shows the signal mapping of the DB9 male connector:

DB9 male

DB9 male pin #CAN signal
6GND
2X_CANL
7X_CANH
3GND

CAN Design Consideration

The CAN bus lanes (X_CANL/X_CANH) should be routed with a differential impedance of 120 Ohm.

Audio / Visual Connectivity

MIPI-DSI (X41)

 MIPI-DSI Connector (X41)

MIPI-DSI Connector (X41)

20 position FPC, 1 mm pitch to connect a MIPI DSI display. The connector pinout is compatible with the Raspberry Pi MIPI DSI display connector.

Compatible MIPI DSI displays: 

  • STMicroelectronics MB1407 DSI display (480x800 pixels)
  • Raspberry Pi Foundation 7'' Touchscreen Display (800x480 pixels)

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1GND--Ground
2Not Connected---
3X_MIPI_DSI_DATA1NDSI_O1.2VMIPI DSI Data 1 Negative Lane
4Not Connected---
5X_MIPI_DSI_DATA1PDSI_O1.2VMIPI DSI Data 1 Positive Lane
6Not Connected---
7GND--Ground
8Not Connected---
9X_MIPI_DSI_CLKNDSI_O1.2VMIPI DSI Clock Negative Lane
10Not Connected---
11X_MIPI_DSI_CLKPDSI_O1.2VMIPI DSI Clock Positive Lane
12Not Connected---
13GND--Ground
14Not Connected---
15X_MIPI_DSI_DATA0NDSI_O1.2VMIPI DSI Data 0 Negative Lane
16Not Connected---
17X_MIPI_DSI_DATA0PDSI_O1.2VMIPI DSI Data 0 Positive Lane
18Not Connected---
19GND--Ground
20Not Connected---
21X_I2C1_SCL/PF14O3.3VI2C1 clock Signal 
22Not Connected---
23X_I2C1_SDA/PF15I/O3.3VI2C1 data Signal
24Not Connected---
25GND--Ground
26Not Connected---
27VCC3V3PWR_O3.3V3.3 V phyBOARD Supply
28Not Connected---
29VCC3V3PWR_O3.3V3.3 V phyBOARD Supply
30Not Connected---
31GND--Ground
32Not Connected---
33X_AV_INT/PI8I3.3V
34Not Connected---
35X_MIPI_DSIHOST_TE/PD13I/O3.3V
36Not Connected---
37X_LCD_BL_PWM/PI0O3.3V
38Not Connected---
39LCD_RESETI/O3.3V
40Not Connected---

X41 Pin Assignment

MIPI DSI Design Consideration

The MIPI DSI Data and Clock lanes should be routed with a differential impedance of 100 Ohm.

Audio/Visual Connectors (X24 and X25)

Audio/Visual Connector (X24 and X25)

The audio/video (A/V) connectors (X24 and X25) provides an easy way to add typical A/V functions to the phyBOARD-Sargas. Standard interfaces such as parallel display, SAI (or SPI/I2S), and I2C as well as different supply voltages are available at the two A/V female dual entry connectors. A special feature of these connectors is their connectivity from either the top or bottom of the board.

Tip

PHYTEC delivers expansion boards like the HDMI interface (PEB-AV-01) or LCD screen module (PEB-AV-02) that can be plugged on those two connectors. PEB-AV-02 module is used to connect a capacitive/resistive touchscreen 7'' display. For resistive touchscreen, the phyBOARD is equipped with a STMPE811 resistive touchscreen driver at U20 (I2C address 0x44 or 0x41).


Interface Pin #

Signal Name

SOM signal Name (when different)

Signal TypeSignal Level

Description

Jumper setting

1

X_AUDIO_CK

X_SAI2_SCK_B/PH2

O3.3VSAI2 transmit bit clock

J17 2+1

X_SPI16_SCK/PZ0

O3.3V

SPI1 (or SPI6) Serial Clock Output[9]

J17 2+3

2X_AUDIO_SYNCX_SAI2_FS_B/PC0O3.3VSAI2 transmit frame SyncJ18 2+1
X_SPI16_NSS/PZ3O

SPI1 or SPI6 Slave Select[10]

J18 2+3
3X_AUDIO_RXDX_SAI2_SD_A/PI6I3.3VSAI2 receive dataJ19 2+1
X_SPI16_MISO/PZ1I

SPI1 or SPI6 Master Input Slave Output[11]

J19 2+3
4X_AUDIO_TXDX_AUDIO_TXDO3.3VSAI2 transmit dataJ20 2+1
X_SPI16_MOSI/PZ2O

SPI1 or SPI6 Master output Slave input[12]

J20 2+3
5X_AV_INT/PI8X_PI8I3.3VA/V Interrupt-
6X_LCD_PWCTRL/PA4X_DACOUT1/PA4O3.3VLCD power control-
7GND---Ground-
8X_LCD_RST/PD9X_PD9

I/O

3.3VGPIO used for LCD Reset-

X_nRESET-Reset3.3VSystem Reset-
9TS_X+-I/O/ANA_I3.3VResistive Touch Input X+ of U20 (refer to STMPE811 datasheet for details)-
10TS_X--I/O/ANA_I3.3V
Resistive Touch Input X- of U20 (refer to STMPE811 datasheet for details)-
11TS_Y+-I/O/ANA_I3.3VResistive Touch Input Y+ of U20 (refer to STMPE811 datasheet for details)-
12TS_Y--I/O/ANA_I3.3VResistive Touch Input Y- of U20 (refer to STMPE811 datasheet for details)-
13VCC3V3-PWR_O3.3V3.3 V phyBOARD Supply-
14GND---Ground-
15X_I2C1_SCL/PF14-O3.3VI2C1 clock Signal -
16X_I2C1_SDA/PF15-I/O3.3VI2C1 data Signal -

X24 Pin Assignment

9.

X_SPI16_SCK/PZ0 can be configured as I2S1_CK (I2S1 Serial Clock line) with  BSP device tree modifications.

10.

X_SPI16_NSS/PZ3 can be configured as I2S1_WS (I2S1 Word Select line) with BSP pin muxing modification.

11.

X_SPI16_MISO/PZ1 can be configured as I2S1_SDI (I2S1 Serial Data line) with  BSP pin muxing modification.

12.

X_SPI16_MOSI/PZ2 can be configured as I2S1_SDO (I2S1 Serial Data line) with BSP pin muxing modification.

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1, 2, 3GND--Ground
4X_LCD_R2/PC10O3.3VLCD data R2
5X_LCD_R3/PB0O3.3VLCD data R3
6GND--Ground
7X_LCD_R4/PH10O3.3VLCD data R4
8X_LCD_R5/PH11O3.3VLCD data R5
9X_LCD_R6/PH12O3.3VLCD data R6
10X_LCD_R7/PE15O3.3VLCD data R7
11, 12, 13GND--Ground
14X_LCD_G2/PH13O3.3VLCD data G2
15X_LCD_G3/PE11O3.3VLCD data G3
16GND--Ground
17X_LCD_G4/PH15O3.3VLCD data G4
18X_LCD_G5/PH4O3.3VLCD data G5
19X_LCD_G6/PI11O3.3VLCD data G6
20X_LCD_G7/PI2O3.3VLCD data G7
21, 22, 23GND--Ground
24X_LCD_B2/PG10O3.3VLCD data B2
25X_LCD_B3/PG11O3.3VLCD data B3
26GND--Ground
27X_LCD_B4/PE12O3.3VLCD data B4
28X_LCD_B5/PI5O3.3VLCD data B5
29X_LCD_B6/PB8O3.3VLCD data B6
30X_LCD_B7/PD8O3.3VLCD data B7
31GND--Ground
32X_LCD_CLK/PG7O3.3VLCD pixel clock
33X_LCD_DE/PE13O3.3VLCD data Enable
34X_LCD_HSYNC/PI10O3.3VLCD Horizontal synchronization
35X_LCD_VSYNC/PI9O3.3VLCD Vertical synchronization
36, 37GND--Ground
38

X_LCD_BL_PWM/PI0

(named X_PI0 on SOM)

O3.3VPWM output for LCD backlight
39VCC_BLPWR_O-Optional Backlight power supply output
40VCC5VPWR_O5V5 V phyBOARD Supply

X25 Pin Assignment

LCD Design Consideration

The LCD signals should be routed with a 50 Ohm impedance.

External Backlight Power Connector (X6)


Optional External Backlight Power Connector (X6)

Optional External Backlight Power Connector (X6)

When using a custom display, a specific voltage might be needed for the backlight power supply (VCC_BL). This connector allows an external power supply to be attached for this purpose.

By default, VCC_BL is connected to the phyBOARD-Sargas power supply (VIN) by jumper JP6=2+1

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1X_VBLany voltagePWR_IOptional External Power Supply for LCD Backlight when JP6 = 2+3
2GND--Ground

X6 Pin Assignment

Audio Connectivity (X5, X26, X27, X28)


Audio Connectors (X5, X26, X27, X28)

Audio Connectors (X5, X26, X27, X28)

The audio interface provides a method of exploring and using STM32MP1x's audio capabilities. The phyBOARD-Sargas is populated with a TLV320AIC3007 audio codec (U1). The audio codec is connected to the STM32MP1's SAI interface to support :

  • Stereo line output/input at 3,5mm Stereo Audio Jacks X26/X27
  • HeadSet at 3,5mm Stereo Audio Jack X28 (stereo Headphone with mono microphone)
  • A direct mono speaker output (Mono Class-D 1W BTL 8Ω Speaker Driver) available at Molex connector X5.

The audio codec can be configured via I2C1 at address 0x18.

It is possible to disable the Audio Codec with Jumper J39. Closing Jumper J39 at 1+2 connects the reset input of the audio codec to GND which holds the Audio Codec in a reset state.

Jumper J2 can be used to configure the headset jack detection:

  • J2 1+2: detection using dc-coupled Stereo Headphone output connection
  • J2 2+3: detection using a Capless Headphone output connection

For additional information regarding special interface specifications, refer to the TLV320AIC3007 audio codec reference manual.

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1SPOPANA_OAnalog

Speaker Output Positive Lane
(U1 LINE1LP)

2SPOMANA_OAnalog

Speaker Output Negative Lane
(U1 LINE1RP)

X5 Pin Assignment

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1GND--Ground
2Not Connected---
3LINE_OUT_RANA_OAnalogAudio Line Output right channel
4LINE_OUT_LANA_OAnalogAudio Line Output right channel

X26 Pin Assignment

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1GND--Ground
2Not Connected---
3LINE_IN_RANA_IAnalogAudio Line In right channel
4LINE_IN_LANA_IAnalogAudio Line In left channel

X27 Pin Assignment

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1GND--Ground
2MIC_INANA_IAnalogMicrophone Input
3HEAD_PHONE_RANA_OAnalogHeadphone Output right
4HEAD_PHONE_LANA_OAnalogHeadphone Output left

X28 Pin Assignment

Audio Codec Design Consideration

Analog Ground (AGND) used for the Audio Codec should be connected to the Ground (GND) through a PCB Star Point (J9 + J10 on phyBOARD-Sargas).

Microphone Array Connector (X20)

Microphone Array Connector (X20)

Microphone Array Connector (X20)

This specific connector connects a PHYTEC custom board equipped with 7 I²S/TDM Output Digital Microphone Array and 12 RGB LEDs. This board was developed for recognition with echo and noise suppression and adaptive Beamforming. This allows for the acoustic detection of the person speaking and the greatest possible suppression of ambient noise. Thus it is also suitable for use in loud environments. 

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1VCC5VPWR_O5V5 V phyBOARD Supply
2VCC3V3PWR_O3.3V3.3 V phyBOARD Supply
3Not Connected---
4GND--Ground
5Not Connected---
6X_I2C1_SCL/PF14O3.3VI2C1 clock Signal
7GND--Ground
8X_I2C1_SDA/PF15I/O3.3VI2C1 data Signal
9X_SAI2_SCK_B/PH2O3.3VSAI2 transmit bit clock
10GND--Ground
11X_SAI2_FS_B/PC0O3.3VSAI2 transmit frame Sync
12X_SAI2_SD_A/PI6I3.3VSAI2 receive data
13X_SAI2_SD_B/PF11O3.3VSAI2 transmit data
14, 15, 16, 17Not Connected---
18GND--Ground
19X_nRESETReset3.3VSystem reset
20Not Connected---

X20 Pin Assignment

Debugging Connectors (X8, X13)

Debugging Connectivity (X8, X13)

Debugging Connectivity (X8, X13)

JTAG Connector (X8)

The phyBOARD-Sargas JTAG interface is accessible at pin header connector X8. It also supports Serial Wire Debug (SWD). 

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

1VCC3V3PWR_O3.3V3.3 V phyBOARD Supply
2VCC3V3PWR_O3.3V3.3 V phyBOARD Supply
3X_JTAG_nTRSTI3.3VJTAG Test Reset
4GND--Ground
5X_JTAG_TDII3.3VJTAG Test Data In
6GND--Ground
7X_JTAG_TMS/SWDIO

I/O

3.3VJTAG Test Mode Select / SWD Single bi-directional data pin
8GND--Ground
9X_JTAG_TCK/SWCLKI3.3VJTAG Test Clock
10GND--Ground
11JTAG_RTCKO3.3VJTAG Return Test Clock 
12GND--Ground
13X_JTAG_TDO/TRACESWOO3.3VJTAG Test Data Out / SWD Output trace port
14GND--Ground
15X_nRESETReset3.3VSystem Reset
16, 17, 18, 19, 20GND--Ground

X8 Pin Assignment

USB Debug Connector (X13)

  • The main debug interface is UART4. It is connected to a UART-to-USB Converter (U7) via a Multiplexer (U23). When a USB cable is plugged in at X13 (USB Micro-AB), the UART4 will be available at the connector. Otherwise, it is routed to the expansion connector (X33). The actual routing is shown by the blue LED D7. Further UART information can be found in the section Expansion Connector.
  • A second UART (USART3) is also available on the USB Debug only when jumper JP16 is removed. USART3 is connected to a UART-to-USB Converter (U7) via a Multiplexer (U22).  When a USB cable is plugged in at X13 and JP16 removed, the USART3 will be available at the connector. Otherwise, it is routed to the expansion connector (X33). 
USB Design Consideration

The data lanes should be routed with a differential impedance of 90 Ohm.

Raspberry Pi HAT Connector (X7)

Raspberry Pi HAT Connector (X7)

Raspberry Pi HAT Connector (X7)

2×20 pin header, 2.54 mm pitch compatible with the official Raspberry Pi HAT connector pinout. The advantages of this connector are:

  • Raspberry Pi HAT boards (official or from the community) can be plugged on the phyBOARD-Sargas and driven by the phyCORE-STM32MP1
  • Existing Raspberry Pi application code can be reused to run on Cortex A7 (Linux).

Interface Pin #

Signal Name

SOM Signal Name
(when different)

Signal TypeSignal Level

Description

Jumper / 0Ω Res setting

1VCC3V3-PWR_O3.3V3.3 V phyBOARD Supply-
2VCC5V-PWR_O5V5 V phyBOARD Supply-
3X_I2C1_SDA/PF15-I/O3.3VI2C1 data Signal -
4VCC5V-PWR_O5V5 V phyBOARD Supply-
5X_I2C1_SCL/PF14-O3.3VI2C1 clock Signal -
6GND---Ground-
7X_DBTRGO/PA13-I/O3.3V

GPIO or External trigger output from CTI

-

8X_USART1_TX/PZ7-O3.3VUSART1 Transmit Data-
9GND---Ground
10X_USART1_RX/PZ6-I3.3VUSART1 Receive Data-
11X_USART1_RTS/PA12X_FDCAN1_TX/PA12O3.3V

USART1 Request To Send[13][14]

-
12

RPI_PCM_CLK/PWM0
(X_SAI2_SCK_B/PH2)

-O3.3VSAI2 transmit bit clockJ21 2+1

RPI_PCM_CLK/PWM0
(TIM1_CH2/PE11)

X_LCD_G3/PE11

O3.3VTIM1 positive channel 2

J21 2+3 & R240 mounted

13X_SDMMC3_D3/PD7-I/O3.3VSD/SDIO data line 3-
14GND---Ground-
15X_SDMMC3_CK/PG15-O3.3VSD/SDIO clock
16X_SDMMC3_CMD/PF1-I/O3.3VSD/SDIO bidirectional command/response signal-
17VCC3V3-PWR_O3.3V3.3 V phyBOARD Supply-
18X_SDMMC3_D0/PF0-I/O3.3VSD/SDIO data line 0-
19X_SPI16_MOSI/PZ2-O3.3VSPI1 (or SPI6) Master output Slave input-
20GND---Ground-
21X_SPI16_MISO/PZ1-I3.3VSPI1 (or SPI6) Master Input Slave output-
22X_SDMMC3_D1/PF4-I/O3.3VSD/SDIO data line 1-
23X_SPI16_SCK/PZ0-O3.3VSPI1 (or SPI6) Serial Clock Output-
24X_SPI16_NSS/PZ3-O3.3VSPI1 (or SPI6) Slave Select-
25GND---Ground-
26X_CEC/PA15X_SPI1_NSS/PA15I/O3.3VGPIO or HDMI-CEC controller signal-
27X_I2C1_SDA/PF15-I/O3.3VI2C1 data Signal -
28X_I2C1_SCL/PF14-O3.3VI2C1 clock Signal -
29X_MCO2/PG2-O3.3VMicrocontroller Clock Output 2-
30GND---Ground-
31X_TIM15_CH1N/PE4X_SDMMC1_CKIN/PE4O3.3VTIM15 negative channel 1-
32

RPI_GPIO_PWM0
(X_PH5)

X_I2C2_SDA/PH5I/O3.3VGPIOJ22 2+1

RPI_GPIO_PWM0
(TIM1_CH2/PE11)

X_LCD_G3/PE11O
TIM1 positive channel 2

J22 2+3 R240 mounted

33

RPI_GPIO_PWM1
(X_PF2)

X_SDMMC1_D0DIR/PF2O3.3VGPIO

J35 2+1

RPI_GPIO_PWM1
(X_DACOUT2_TIM8_CH1N/PA5)

X_DACOUT2/PA5O3.3VDAC output or TIM8 negative channel 1J35 2+3
34GND---Ground-
35X_SAI2_FS_B/PC0-O3.3VSAI2 transmit frame Sync-
36X_USART1_CTS/PA11X_FDCAN1_RX/PA11I3.3V

USART1 Clear To Send[13][14]

-
37X_SDMMC3_D2/PF5-I/O3.3VSD/SDIO data line 2-
38X_SAI2_SD_B/PF11-O3.3VSAI2 transmit data-
39GND---Ground-
40X_SAI2_SD_A/PI6-I3.3VSAI2 receive data-

X7 Pin Assignment

13.

X_USART1_RTS/PA12 and  X_USART1_CTS/PA11 can also be used as a second phyBOARD I2C bus interface (I2C5_SDA/I2C6_SDA and I2C5_SCL/I2C6_SCL). Cf. See I2C5/I2C6 Interface.

14.

X_USART1_RTS/PA12 and  X_USART1_CTS/PA11 can also be pin muxed (in BSP) as FDCAN1_TX/FDCAN1_RX signals (second CAN FD interface without transceiver).

Arduino Shields Connector (X3)

Arduino Connector (X3)

Arduino Shields Connector (X3)

The Arduino shields connector is composed of 32 sockets (four single row connectors, 2.54mm pitch). The pinout is compatible with the Arduino Uno Rev3 Shield connector:

  • Socket 1x8: power supply and Reset signal
  • Socket 1x6 (pins A0 to A5): analog signals 
  • Socket 1x10 (pins D8 to D15): I/O signals (GPIO, I2C/CAN, SPI, PWM, or DFSDM)
  • Socket 1x8 (pins D0 to D7):  I/O signals (GPIO, UART, PWM or DFSDM)

The advantages of these connectors are :

  • Most of STM32 NUCLEO Eval boards or Arduino community Eval boards can be plugged on the phyBOARD-Sargas
  • Existing Firmware can run on Cortex M4

By default, only one of the I2C signals is used on the phyBOARD (I2C1). But in case one other I2C bus is needed (must be controlled by Cortex-M4 for example), Jumpers JP27 and JP28 are provided to use I2C5 or (I2C6) bus from the phyCORE instead of I2C1 (only for the Arduino shield connector).

Note

The Signal Type shown in the table below contains the signals configured in the Arduino/MotorControl device tree expansion files (BSP) which are not activated by default. By default, except USARTs, I2C1, and SPI16, all the other signals are GPIOs.

Interface Pin #

Arduino Pin ID

Signal Name

SOM Signal Name (when different)Signal TypeSignal Level

Description

Jumper / 0Ω Res setting

1D0X_USART3_RX_ARD_EXP/PB12X_USART3_RX/PB12I3.3V

X_USART3_RX/PB12 is connected to this Interface Pin if JP16 populated. 

If JP16 is not populated,  X_USART3_RX/PB12 is connected when there is no VCC_FTDI_3V3 supply (USB Debug cable not plugged on X13)

JP16 1+2

or

JP16 open+ no VCC_FTDI_3V3 supply

2D1X_USART3_TX_ARD_EXP/PB10X_USART3_TX/PB10O3.3V

X_USART3_TX/PB10 signal is connected to this Interface Pin if JP16 populated. 

If JP16 is not populated,  X_USART3_TX/PB10 is connected when there is no VCC_FTDI_3V3 supply (USB Debug cable not plugged on X13)

JP16 1+2

or

JP16 open+ no VCC_FTDI_3V3 supply

3D2X_DFSDM1_DATIN3/PF13-I/O

3.3V

GPIOor DFSDM1 Input from Channel 3-
4D3TIM4_CH2/PB7X_DCMI_VSYNC/PB7O
TIM4 positive channel 2R241 mounted
5D4X_DFSDM1_DATIN1/PC3
I/O

3.3V

GPIOor DFSDM1 Input from Channel 1-
6D5TIM15_CH1/PE5X_DCMI_DATA6/PE5O3.3VTIM15 positive channel 1R242 mounted
7D6

ARD_D6_PWM

(TIM12_CH2/PH9)

X_DCMI_DATA0/PH9I/O3.3VGPIOor TIM12 positive channel 2 

J36 2+1

& R244 mounted

ARD_D6_PWM
(X_DFSDM1_CKOUT/PD10))

-I/O3.3VGPIOor DFSDM1 Clock OutputJ36 2+3
8D7X_DFSDM1_DATIN0/PG0-I/O3.3VGPIOor DFSDM1 Input from Channel 0-
9D8X_TIM8_BKIN2/PG3X_DFSDM1_CKIN1/PG3I/O3.3VGPIO or TIM8 Break Input 2-
10D9X_TIM1_CH4/PE14X_SDMMC1_D123DIR/PE14O3.3VTIM1 positive channel 4-
11D10X_PG8X_USART3_RTS/PG8I/O3.3VGPIOJ37 2+1

X_SPI16_NSS/PZ3

-O3.3VSPI1 (or SPI6) Slave SelectJ37 2+3
12D11X_TIM15_CH1N/PE4X_SDMMC1_CKIN/PE4O3.3VTIM15 negative channel 1J38 2+1
X_SPI16_MOSI/PZ2-O3.3VSPI1 (or SPI6) Master Output Slave InputJ38 2+3
13D12X_SPI16_MISO/PZ1-I3.3VSPI1 (or SPI6) Master Input Slave Output-
14D13X_SPI16_SCK/PZ0-O3.3VSPI1 (or SPI6) Serial Clock Output-
15GNDGND---Ground-
16AREFNot Connected-----
17D14X_I2C1_SDA/PF15-I/O3.3VI2C1 data Signal JP27/JP28 2+1
X_USART1_RTS/PA12X_FDCAN1_TX/PA12O3.3V

USART1 Request To Send[13][14]

JP27/JP28 2+3
18D15X_I2C1_SCL/PF14-O3.3VI2C1 clock Signal JP27/JP28 2+1
X_USART1_CTS/PA11X_FDCAN1_RX/PA11I3.3V

USART1 ClearTo Send[13][14]

JP27/JP28 2+3
19A5X_ADC1_INN2/PF12-ANA_I0-VREFADC1 Input INN2 or INP6-
20A4ADC1_INP13_INN12/PC3X_DFSDM1_DATIN1/PC3ANA_I0-VREFADC1 Input INP13 or INN12R238 mounted
21A3ADC2_INP2/PF13X_DFSDM1_DATIN3/PF13ANA_I0-VREFADC2 Input INP2R234 mounted
22A2X_PVD_IN/ADC1_INP15/PA3-ANA_I0-VREFADC1 Input INP1 or Power programmable Voltage Detector Input or 5-
23A1X_ADC1_INP1-ANA_I0-VREFADC1 Input INP1-
24A0X_ADC1_INN1-ANA_I0-VREFADC1 Input INN1-
25VINNot Connected-----
26, 27GNDGND---Ground-
285VVCC5V-PWR_O5V5 V phyBOARD Supply-
293.3VVCC3V3-PWR_O3.3V3.3 V phyBOARD Supply-
30RESETX_nRESET-Reset3.3VSystem ResetSystem Reset-
31IOREFVCC3V3-PWR_O3.3V3.3 V phyBOARD Supply-
32RESERVEDNot Connected-----

X3 Pin Assignment

13.

X_USART1_RTS/PA12 and  X_USART1_CTS/PA11 can also be used as a second phyBOARD I2C bus interface (I2C5_SDA/I2C6_SDA and I2C5_SCL/I2C6_SCL). Cf. See I2C5/I2C6 Interface.

14.

X_USART1_RTS/PA12 and  X_USART1_CTS/PA11 can also be pin muxed (in BSP) as FDCAN1_TX/FDCAN1_RX signals (second CAN FD interface without transceiver).

Motor Control Connector (X38)

Motor Control Connector (X38)

Motor Control Connector (X38)

2×17 pin header, 2.54 mm pitch. Compatible with STM32 motor control power eval boards STEVAL‐x. It is also possible to connect X-NUCLEO-IHMx STM32 motor control eval boards using the X-NUCLEO-IHM09M1 adaptor.

Note

The Signal Type shown in the table below contains the signals configured in the Arduino/MotorControl device treeexpansion files (BSP) which are not activated by default. By default, except for USART and LCD signals, all the other signals are GPIOs.

Interface Pin #

Signal Name

SOM Signal Name
(when different)

Signal TypeSignal Level

Description 


Jumper

/ 0Ω Res setting

Motor Control function
1X_TIM8_BKIN2/PG3X_DFSDM1_CKIN1/PG3I/O3.3V

GPIOor TIM8 Break Input 2

-EmergencySTOP
2GND---Ground--
3TIM8_CH1/PI5X_LCD_B5/PI5O3.3VTIM8 positive channel 1R228 mounted

U HighPhase Control

(PWM output)

4GND---Ground--
5X_DACOUT2_TIM8_CH1N/PA5X_DACOUT2/PA5O3.3VTIM8 negative channel 1

U Low Phase Control

(PWM output)

6GND---Ground--
7TIM8_CH2/PC7X_DCMI_DATA1/PC7O3.3VTIM8 positive channel 2R230 mounted

V High Phase Control

(PWM output)

8GND---Ground--
9TIM8_CH2N/PB0X_LCD_R3/PB0O3.3VTIM8 negative channel 2R231 mounted

V Low Phase Control

(PWM output)

10GND---Ground--
11TIM8_CH3/PI7X_DCMI_DATA7/PI7O3.3VTIM8 positive channel 3R239 mounted

W High Phase Control

(PWM output)

12GND---Ground--
13TIM8_CH3N/PH15X_LCD_G4/PH15O3.3VTIM8 negative channel 3R232 mounted

W Low Phase Control

(PWM output)

14X_PVD_IN/ADC1_INP15/PA3-ANA_I0-VREFADC1 input INP15-Bus Voltage sensing
15X_ADC1_INN2/PF12-ANA_I0-VREFADC1 input INN2 or INP6-Current phase A
16GND---Ground--
17X_ADC1_INN1-ANA_I0-VREFADC1 input INN1-Current phase B
18GND---Ground--
19X_ADC1_INP1-ANA_I0-VREFADC1 input INP1-Current phase C
20GND---Ground--
21X_LCD_PWCTRL/PA4X_DACOUT1/PA4I/O3.3VGPIO-

bypass Relay NTC resistor

22GND---Ground--
23TIM3_CH1/PA6X_DCMI_PIXCLK/PA6O3.3VTIM3 positive channel 3R270 mounted

Dissipative Brake

(PWM output)

24GND---Ground--
25VCC5V-PWR_O5V5 V phyBOARD Supply--
26ADC1_INP13_INN12/PC3X_DFSDM1_DATIN1/PC3ANA_I0-VREF-R238 mountedHeat sink (temperature monitor)
27TIM1_CH2/PE11X_LCD_G3/PE11I3.3VTIM1 positive channel 2R240 mounted

Power Factor Correction (PFC) Synchronisation (timer input capture)

X_USART1_RTS/PA12X_FDCAN1_TX/PA12I3.3VTIM1_ETRR275 mounted

Timer 1 external Trigger input (optional)

28VCC3V3-PWR_O3.3V3.3 V phyBOARD Supply--
29X_TIM1_CH4/PE14X_SDMMC1_D123DIR/PE14O3.3VTIM1 positive channel 4-

Power Factor Correction (PFC)

(PWM output)

30GND---Ground--
31TIM5_CH1/PH10X_LCD_R4/PH10O3.3VTIM5 positive channel 1R245 mounted

Encoder / Hall / BEMF - phase A

(Quadrature encoder input)

32GND---Ground--
33TIM5_CH3/PH12X_LCD_R6/PH12O3.3VTIM5 positive channel 3R249 mounted

Encoder / Hall / BEMF - phase B

(Quadrature encoder input)

34TIM5_CH4/PI0X_PI0O3.3VTIM5 positive channel 4R246 mounted

Encoder / Hall / BEMF - phase C

(Quadrature encoder input)

X38 Pin Assignment

RS232 / RS485 Connector (X35)


RS232 / RS485 Connector (X35)

The phyBOARD-Sargas is equipped with an RS232 transceiver (U14) and RS485 transceiver(at U18). Both are connected to the phyBOARD-Sargas USART1 interface so jumpers must be set correctly to select which interface to use (RS232 or RS485).

The RS232 transceiver (MAX3232ESE) operates at data rates up to 250 kbit/s. The RS485 transceiver (SN65HVD12D) operates up to 1Mbit/s. 

Interface Pin #

Signal Name

Signal TypeSignal Level

Description

Jumper setting
1, 2, 10Not Connected---
3X_RS232_RXRS232_IRS232 standardRS232 Receive DataJP4 1+2
4X_RS232_RTSRS232RS232 standardRS232 Request to Send signalJP31 closed
5X_RS232_TXRS232_ORS232 standardRS232 Transmit DataJP5 1+2
6X_RS232_CTSRS232RS232 standardRS232 Request to Clear signalJP30 closed
7X_RS485_ARS485_I/ORS485 standardRS485 A signal JP4/JP5 2+3
8X_RS485_BRS485_I/ORS485 standardRS485 B signal JP4/JP5 2+3
9GND--Ground

X35 Pin Assignment

An adapter cable (pin header to DB9 male connector) is plugged by default on X35 on the phyBOARD-Sargas STM32MP1 Kit to facilitate the use of the RS232/RS485 interface. The following figure shows the signal mapping of the DB9 male connector:

DB9 male

DB9 male pin #RS232/RS485 signal
2X_RS232_RX
7X_RS232_RTS
3X_RS232_TX
8X_RS232_CTS
4X_RS485_A
9X_RS485_B
5GND

RS485 Design Considerations

The RS485 bus lanes (X_RS485_A/X_RS485_B) should be routed with a differential impedance of 120 Ohm.

Expansion Connector (X33)

Expansion Connector (X33)

Expansion Connector (X33)

The expansion connector X30 provides an easy way to add other functions and features to the phyBOARD-Sargas. Standard interfaces such as SPI, USB OTG, SDMMC, U(S)ARTs, or I2C are available at the expansion connector. Additionally, other power supplies or signals from the phyCORE-STM32MP1 are available on it. The expansion connector is intended to be used with a PHYTEC PEB-x expansion board or custom expansion boards.

Interface Pin #

Signal Name

SOM Signal Name
(when different)

Signal Type

Signal Level

Description

Jumper setting
1VCC3V3-PWR_O3.3V3.3 V phyBOARD Supply-
2VCC5V-PWR_O5V5 V phyBOARD Supply-
3VCC1V8-PWR_O1.8V1.8 V phyBOARD Supply-
4GND---Ground-
5X_SPI16_NSS/PZ3-O3.3VSPI1 or SPI6 Slave Select-
6X_SPI16_MOSI/PZ2-O3.3VSPI1 or SPI6 Master output Slave input-
7X_SPI16_MISO/PZ1-I3.3VSPI1 or SPI6 Master Input Slave output-
8X_SPI16_SCK/PZ0-O3.3VSPI1 or SPI6 Serial Clock Output-
9GND---Ground-
10X_UART4_RX_EXP/PB2X_UART4_RX/PB2I3.3VUART4 Receive Data X_UART4_RX/PB2  is connected to this pin when there is no VCC_FTDI_3V3 supply (USB Debug cable not plugged on X13)no VCC_FTDI_3V3 supply
11X_I2C1_SDA/PF15-I/O3.3VI2C1 data Signal-
12X_UART4_TX_EXP/PB9X_UART4_TX/PB9O3.3VUART4 Transmit Data X_UART4_TX/PB9  is connected to this pin when there is no VCC_FTDI_3V3 supply (USB Debug cable not plugged on X13)no VCC_FTDI_3V3 supply
13X_I2C1_SCL/PF14-O3.3VI2C1 clock Signal-
14GND---Ground-
15X_SAI2_MCLK_B/PH3---SAI2 Master Clock-
16X_SAI2_SD_B/PF11-O3.3VSAI2 transmit data-
17X_SAI2_SCK_B/PH2-O3.3VSAI2 transmit bit clock-
18X_SAI2_FS_B/PC0-O3.3VSAI2 transmit frame Sync-
19GND---Ground-
20X_SAI2_SD_A/PI6-I3.3VSAI2 receive data-
21X_USB_DP2_EXPX_USB_OTG_D2PUSB_I/O3.3VUSB 2.0 Positive LaneJ23/J24 2+3
22X_USB_DM2_EXPX_USB_OTG_D2MUSB_I/O3.3VUSB 2.0 Negative LaneJ23/J24 2+3
23X_nRESET-Reset3.3VSystem Reset-
24GND---Ground-
25X_SDMMC3_CMD/PF1-I/O3.3VSD/SDIO bidirectional command/response signal-
26X_SDMMC3_D0/PF0-I/O3.3VSD/SDIO data line 0-
27X_SDMMC3_CK/PG15-O3.3VSD/SDIO clock-
28X_SDMMC3_D1/PF4-I/O3.3VSD/SDIO data line 1-
29GND---Ground-
30X_SDMMC3_D2/PF5-I/O3.3VSD/SDIO data line 2-
31X_USART3_RX_ARD_EXP/PB12X_USART3_RX/PB12I3.3VUSART3 Receive Signal

JP16 1+2
or
JP16 open+ no VCC_FTDI_3V3 supply

32X_SDMMC3_D3/PD7-I/O3.3VSD/SDIO data line 3-
33X_USART3_TX_ARD_EXP/PB10X_USART3_TX/PB10O3.3VUSART3 Transmit Signal

JP16 1+2
or
JP16 open+ no VCC_FTDI_3V3 supply

34GND---Ground-
35VREF-PWR_I/O

ADC VREF pin

refer to SM32MP1 datasheet for signal level

-
36X_PWR_ON-O3.3VPWR_ON STM32MP1 output pin (connected to PWRCTRL PMIC input pin) -
37VBUS_SW-PWR_O5VVBUS USB HOST Voltage Supply from PMIC-
38X_RTC_EVI-I3.3VphyCORE external RTC Event input-
39X_RTC_CLKOUT-O3.3VphyCORE external RTC clock output-
40X_nRTC_INT-O3.3VphyCORE external RTC interrupt output-
41GND---Ground-
42X_DBTRGO/PA13-I/O3.3V

GPIOor External trigger output from CTI

-
43X_DBTRGI/PA14-I/O3.3VGPIOor External trigger input to CTI-
44X_WAKEUP3/PC13-I/O3.3VPMIC wakeup pin input / STM32MP1 PC13 pin -
45X_nPMIC_INT/PA0-O3.3VPMIC interrupt output-
46GND---Ground-
47X_DFSDM1_CKOUT/PD10-O3.3VDFSDM1 Clock output-
48X_PG8-I/O3.3VGPIO-
49X_FDCAN2_TX_EXP/PB13X_USART3_CTS/PB13O3.3VFDCAN2 transmit dataJP25/JP26 1+2
50X_FDCAN2_RX_EXP/PB5X_SPI1_MOSI/PB5I3.3VFDCAN2 receive dataJP25/JP26 1+2
51GND---Ground-
52X_nPONKEY-I3.3VPONKEYn PMIC pin-
53X_USB_OTG_ID/PA10-I/O3.3VID Pin of USB OTG Port-
54X_USB_OTG_VBUS-PWR_I5VUSB OTG VBUS input -
55VBUS_OTG-PWR_O5VUSB OTG Supply Voltage Supply from PMIC-
56GND---Ground-
57VDD-PWR_O3.3VVDD power supply from PMIC-
58VDD_BUCK4-PWR_O3.3VVDD_BUCK4 power supply from PMIC-
59GND---Ground-
60VDD_LDO1-PWR_O1.7 - 3.3VVDD_LDO1 power supply from PMIC-

X33 Pin Assignment

phyBOARD-Sargas LED and Switches

phyBOARD-Sargas LED and Switch Locations

phyBOARD-Sargas LED and Switch Locations

Multicolor (RGB) LED (D11)

The phyBOARD-Sargas provides one multicolor (RGB) LED (D11) for user application. The LED is controlled with a LED dimmer PCA9533/01 (U10) and supply by VCC5V.

The LED dimmer can be accessed via I2C1 at address 0x62 and dynamically controls the LED with 3 PMW signals.

The table below shows the signals from LED dimmer (U10) that control the RGB colors:

U10 pin #

U10 Pin name

Signal name

Description

1LED0RGB_LED_REDPWM controlling Red Color
2LED1RGB_LED_GREENPWM controlling Green Color
3LED2RGB_LED_BLUEPWM controlling Blue Color

Multicolor LED Configuration

Boot Switch (S7)

The phyBOARD-Sargas has six defined boot sources that can be selected with DIP switch S7 (see Boot Mode Selection for more information).

The figures below show a visual representation of each S7 boot mode switch settings (the switch-position is shown in white):

NORSD CardeMMCNANDUART/USB

Boot Mode Design Considerations

Bootpin voltages have to be valid when X_nRESET is released.

System Reset (S1)

The phyBOARD-Sargas is equipped with a System Reset switch at S1 (push button).

Pressing this switch will toggle the X_nRESET pin (X1 Pin D51) of the phyCORE-STM32MP1, to Low state, causing the module to reset with a complete power cycle.

System ON/OFF/Wake-up (S2)

The phyBOARD-Sargas is equipped with an ON/OFF/Wake-up switch at S2 (push button).

Pressing this switch will toggle the X_nPONKEY pin (X1 Pin D54) of the phyCORE-STM32MP1, to low state. On the phyCORE, this signal is directly connected to the PMIC PONKEYn input pin.

  • A long keypress enables powering OFF the system.
  • A single keypress enables powering ON the system or waking up from any Low Power mode.

Note

This behavior depends on the BSP configuration. More information can be found in the STM32MP1 and STPMIC1A datasheets.

User Programmable Switches (S4, S5)

The phyBOARD-Sargas is equipped with two User Programmable Switches S4, and S5  (push buttons).

Those switches allow any Software application to used it as an event source :

  • Pressing S4 switch will toggle to X_DBTRGO/PA13 Low state (on the phyCORE-STM32MP1, it will light up LED red D2).
  • Pressing S5 switch will toggle to X_DBTRGI/PA14 Low state (on the phyCORE-STM32MP1, it will light up LED green D1).

Additional System Level Hardware Information

Soldering Jumpers and 0 Ohm Resistors

Numerous soldering jumpers and 0 Ohm resistors allow the phyBOARD-Sargas to be configured according to various application needs.

Soldering Jumpers

ReferencePositionDescriptionSection
J21+2 Audio Jack/Headset detection: dc couplingAudio Connectivity
2+3Audio Jack/Headset detection: capless application
J31+2CAM_MCLK from X_MCO2/PG2 pin
Camera
2+3CAM_MCLK from 27MHz oscillator (OZ1)
J41+2 CAM_CTRL2 to GND

Camera

2+3CAM_CTRL2 to VCC_CAM
not mountedCAM_CTRL2 not connected
J51+2CAM_CTRL1 to GND
Camera
2+3CAM_CTRL1 to VCC_CAM
J71+2 X_nRESET to X24
Audio/Visual Connectors
2+3X_LCD_RST/PD9 to X24
J81+2I2C address of STMPE811 (U20) = 0x41
Audio Connectivity
2+3I2C address of STMPE811 (U20) = 0x44

J9

closedGND connected to AGND via a star pointAudio Connectivity

J10

closedGND connected to AGND via a star pointAudio Connectivity
J171+2X_SAI2_SCK_B/PH2 connected to X24
Audio/Visual Connectors
2+3X_SPI16_SCK/PZ0 connected to X24
J181+2X_SAI2_FS_B/PC0 connected to X24
Audio/Visual Connectors
2+3X_SPI16_NSS/PZ3 connected to X24
J191+2X_SAI2_SD_A/PI6 connected to X24
Audio/Visual Connectors
2+3X_SPI16_MISO/PZ1 connected to X24
J201+2X_SAI2_SD_B/PF11 connected to X24
Audio/Visual Connectors
2+3X_SPI16_MOSI/PZ2 connected to X24
J211+2X_SAI2_SCK_B/PH2 connected to X7
Raspberry Pi HAT
2+3TIM1_CH2/PE11 (X_LCD_G3/PE11) connected to X7
J221+2X_PH5 connected to X7
Raspberry Pi HAT
2+3TIM1_CH2/PE11 (X_LCD_G3/PE11) connected to X7
J231+2X_USB_OTG_D2M connected to X12USB
-----
Expansion Connector
2+3X_USB_OTG_D2M connected to X33
J24

1+2X_USB_OTG_D2P connected to X12USB
-----
Expansion Connector
2+3X_USB_OTG_D2P connected to X33
J29

1+2TPS62150 Step-Down Converter (U5) disabled
Camera
2+3TPS62150 Step-Down Converter (U5) enabled

J35
1+2X_PF2 connected to X7
Raspberry Pi HAT
2+3X_DACOUT2_TIM8_CH1N/PA5 connected to X7

J36
1+2TIM12_CH2/PH9 (X_DCMI_DATA0/PH9) connected to X3

Arduino Shields Connector

2+3X_DFSDM1_CKOUT/PD10 connected to X3
J37

1+2X_PG8 connected to X3Arduino Shields Connector
2+3X_SPI16_NSS/PZ3 connected to X3

J38
1+2X_TIM15_CH1N/PE4 connected to X3Arduino Shields Connector
2+3X_SPI16_MOSI/PZ2 connected to X3
J391+2Audio Codec (U1) nRESET pin connected to Ground (U1 disabled)
Audio Connectivity
2+3Audio Codec (U1) nRESET pin connected to X_nRESET (U1 enabled)

0 Ohm Resistors

Those resistors have no functional impact and should be always mounted.

Most of the phyBOARD-Sargas TIMERs signals are Alternate Function of X_LCD_x or X_DCMI_x signals (configured by Software Pin muxing in the BSP). For better schematic visibility and to avoid any signal length routing issue when using LCD or DCMI function, 0 Ohm resistors are mounted by default between X_LCD or X_DCMI and TIMx_CHy signals. Additionally, two X_DFSDM signals are used as ADC on the phyBOARD, so the same logic has been done for those two signals.

ReferencePopulatedDescriptionSection
R228mountedTIM8_CH1/PI5 connected to PI5 MPU pin (= X_LCD_B5/PI5)Motor Control Connector
not mountedTIM8_CH1/PI5 Not connected to PI5 MPU pin
R230mountedTIM8_CH2/PC7 connected to PC7 MPU pin (= X_DCMI_DATA1/PC7)Motor Control Connector
not mountedTIM8_CH2/PC7 Not connected to PC7 MPU pin
R231mountedTIM8_CH2N/PB0 connected to PB0 MPU pin (= X_LCD_R3/PB0)Motor Control Connector
not mountedTIM8_CH2N/PB0 Not connected to PB0 MPU pin
R232mountedTIM8_CH3N/PH15 connected to PH15 MPU pin (= X_LCD_G4/PH15)Motor Control Connector
not mountedTIM8_CH3N/PH15 Not connected to PH15 MPU pin 
R234mountedADC2_INP2/PF13 connected to PF13 MPU pin (= X_DFSDM1_DATIN3/PF13)Arduino Shields Connector
not mountedADC2_INP2/PF13 Not connected to PF13 MPU pin
R238mountedADC1_INP13_INN12/PC3 connected to PC3 MPU pin (= X_DFSDM1_DATIN1/PC3)

Arduino Shields Connector
-----
Motor Control Connector

not mountedADC1_INP13_INN12/PC3 Not connected to PC3 MPU pin
R239mountedTIM8_CH3/PI7 connected to PI7 MPU pin (= X_DCMI_DATA7/PI7)Motor Control Connector
not mountedTIM8_CH3/PI7 Not connected to PI7 MPU pin
R240mountedTIM1_CH2/PE11 connected to PE11 MPU pin (= X_LCD_G3/PE11)Raspberry Pi HAT
-----
Motor Control Connector
not mountedTIM1_CH2/PE11 Not connected to PE11 MPU pin
R241mountedTIM4_CH2/PB7 connected to PB7 MPU pin (= X_DCMI_VSYNC/PB7)Arduino Shields Connector
not mountedTIM4_CH2/PB7 Not connected to PB7 MPU pin
R242mountedTIM15_CH1/PE5 connected to PE5 MPU pin (= X_DCMI_DATA6/PE5)Arduino Shields Connector
not mountedTIM15_CH1/PE5 Not connected to PE5 MPU pin
R244mountedTIM12_CH2/PH9 connected to PH9 MPU pin (= X_DCMI_DATA0/PH9)Arduino Shields Connector
not mountedTIM12_CH2/PH9 Not connected to PH9 MPU pin
R245mountedTIM5_CH1/PH10 connected to PH10 MPU pin (= X_LCD_R4/PH10)Motor Control Connector
not mountedTIM5_CH1/PH10 Not connected to PH10 MPU pin
R246mountedTIM5_CH4/PI0 connected to PI0 MPU pin (= X_LCD_BL_PWM/PI0)Motor Control Connector
not mountedTIM5_CH4/PI0 Not connected to PI0 MPU pin
R249mountedTIM5_CH3/PH12 connected to PH12 MPU pin (= X_LCD_R6/PH12)Motor Control Connector
not mountedTIM5_CH3/PH12 Not connected to PH12 MPU pin
R270mountedTIM3_CH1/PA6 connected to PA6 MPU pin (= X_DCMI_PIXCLK/PA6)Motor Control Connector
not mountedTIM3_CH1/PA6 Not connected to PA6 MPU pin

Warning

Due to the small footprint of the jumpers / 0 Ohm resistors, we do not recommend manual jumper/resistor modifications. This may render the warranty invalid. Please contact our sales team if you need one of the configurations described below.

I2C Connectivity

I2C4 Interface

The I2C4 interface is intended to be used for the SOM only. But the interface is available on the SOM connector:

  • pin X1.D21 = X_I2C4_SCL/PZ4 and pin X1.D22 = X_I2C4_SDA/PZ5

This bus is also used for security purposes. This is why on the phyBOARD, the Crypto AuthentificationATECC508A device (U24) is connected to this I2C4 bus at address 0x60. Otherwise, this bus is not available phyBOARD-Sargas expansion connectors.

I2C1 Interface

The I2C1 interface is intended to be used for the phyBOARD only (not used on the SOM). The table below provides a list of the expansions connectors and pins with I2C1 connectivity:

Connector

Connector Pin #

Signal name

Jumper setting
X206

X_I2C1_SCL/PF14


8X_I2C1_SDA/PF15
X2415

X_I2C1_SCL/PF14



16X_I2C1_SDA/PF15
X317

X_I2C1_SDA/PF15

JP27/JP28 1+2
18X_I2C1_SCL/PF14JP28/JP28 1+2
X73

X_I2C1_SDA/PF15


X_I2C1_SCL/PF14
27X_I2C1_SDA/PF15
28X_I2C1_SCL/PF14
X3311

X_I2C1_SDA/PF15


13X_I2C1_SCL/PF14
X4121, 22X_I2C1_SCL/PF14
23, 24X_I2C1_SDA/PF15

I2C5/I2C6 Interface (possible additional I2C interface)

I2C5 (or I2C6) is a possible additional I2C interface that is available on expansion connectors (X3 or X7), in case X_USART1_CTS/PA11 and X_USART1_RTS/PA12 signals are not used for USART1 flow control. In this case, the pin muxing (BSP) must be changed to configure those signals as an I2C bus.

The table below provides a list of the expansions connectors and pins with I2C5/I2C6 connectivity:

Connector

Connector Pin #

Signal name

Jumper Setting
X317

X_USART1_RTS/PA12 (I2C56_SDA)

JP27/JP28 2+3
18X_USART1_CTS/PA11 (I2C56_SCL)JP28/JP28 2+3
X711

X_USART1_RTS/PA12 (I2C56_SDA)


36X_USART1_CTS/PA11 (I2C56_SCL)

If needed, 2K pull-ups can be mounted on the I2C5/I2C6 bus: X_USART1_RTS/PA12 (SDA) with resistor R273 and X_USART1_CTS/PA11 (SCL) with resistor R274.

I2C4 and I2C1 Connectivity

To avoid any conflicts when connecting external I2C devices to the phyBOARD-Sargas, the addresses of the on-board I2C devices must be considered.

The table below lists the addresses already in use and shows only the default address. The I²C addresses are hexadecimal in an 8-bit representation. In Linux, a 7-bit representation may be used. In this case, the address value must be shifted one digit to the right. The specification refers to the write address (bit 0 = 0), the read address is increased by 1 according to bit 1 = 1.

Board

Prod. No.

Device

Address used (7 MSB)

I2C4

phyCORE

PCM-068


RTC (RV-3028-C7)0x52
EEPROM (M24C32)0x50
PMIC (STPMIC1)0x33 and 0x58 
phyBOARDPCM-939CryptoAuthentication Device (ATECC508A)0x60
I2C1
phyBOARD

PCM-939



RGB LED (PCA9533/01)0x62
Audio Codec (TLV320AIC3007)0x18
Resistive Touch driver (STMPE811)

0x44 by default (J8=2+3)
(or 0x41 with J8=1+2)

AV-Adapter HDMIPEB-AV-01HDMI Core (TDA19988)0x70
CEC Core (TDA19988)0x34
AV-Adapter Display (with 7'' EDT Display)KPEB-AV-02Touchscreen driver (EDT ft5x06)0x38

I2C Addresses in Use

Warning

Additional I2C devices can be added on the I2C1 bus through the different expansion connectors (with PHYTEC expansion boards or custom boards). In this case, all the I2C device addresses must be unique to avoid conflict.

Revision History

Changes in this manual

Version #

Changes in this manual



15.06.2020



L-875e-A0

Preliminary Manual
Describes the phyCORE‑STM32MP1
SOM Version: 1534.1
Describes the phyBOARD-Sargas
PCB Version: 1517.2