Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (™ or ®) and copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents and trademarks are similarly not expressly indicated in this manual.

The information in this document has been carefully checked and is considered to be entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result.

Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so.

@ Copyright 2020 PHYTEC Messtechnik GmbH, D-55129 Mainz. 

Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH.

Conventions, Abbreviations, and Acronyms

This hardware manual describes the PCL-069 System on Module, referred to as phyCORE^®-i.MX 8M Mini, and the PB-02820-xxxxx.Ax, referred to as phyBOARD^®-Polis. The manual specifies the phyCORE-i.MX 8M Mini and phyBOARD-Polis' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M Mini microcontrollers can be found in thei.MX 8M Mini Microcontroller Data Sheet/Reference Manual.

Conventions

The conventions used in this manual are as follows:

• Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low, or are driving low.
• A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
• The hex-numbers given for addresses of I²C devices always represent the 7 MSB of the address byte. The correct value of the LSB which depends on the desired command (read (1), or write (0)) must be added to get the complete address byte. E.g.  given address in this manual 0x41 => complete address byte = 0x83 to read from the device and 0x82 to write to the device
• Tables that describe jumper settings show the default position in bold,bluetext.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of a signal.

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate any unfamiliar terms used in this document.

Abbreviations and Acronyms Used in this Manual

Preface

As a member of PHYTEC's phyCORE^® product family, the phyCORE‑i.MX 8M Mini is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers, various types of memory (RAM, NAND flash, eMMC), and many other features. This, in turn, offers increased kinds of functions and configurations. PHYTEC supports a variety of 8/16/32/64 bit controllers in two ways:

1. As the basis for Rapid Development Kits which serve as a reference and evaluation platform.
2. As insert-ready, fully functional phyCORE^® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "reinvent" microcontroller circuitry. Furthermore, much of the value of the phyCORE^® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative full system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Ordering Information

The part numbering of the phyCORE has the following structure:

Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-mini-nano/
or
https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 8M Mini

PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Product Change Management and Information Regarding Parts Populated on the SOM / SBC

With the purchase of a PHYTEC SOM / SBC you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.

Our general philosophy here is: We never discontinue a product as long as there is a demand for it.

Therefore, we have established a set of methods to fulfill our philosophy:

Avoidance strategies:

• Avoid changes by evaluating the longevity of parts during the design-in phase.
• Ensure the availability of equivalent second source parts.
• Stay in close contact with part vendors to be aware of roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

• Ensure long term availability by stocking parts through last time buy management according to product forecasts.
• Offer long term frame contracts to customers.

Change management in case of functional changes:

• Avoid impacts on product functionality by choosing equivalent replacement parts.
• Avoid impacts on product functionality by compensating changes through hardware redesign or backward-compatible software maintenance.
• Provide early change notifications concerning functional, relevant changes to our products.

We refrain from providing detailed part specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

• Quickstart Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a BSP, the device tree, and accessing peripherals.
• Hardware Manual:  A detailed description of the System on Module and accompanying carrier board. 
• Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; an introduction, installing and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
• BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
• Development Environment Guide:  This guide shows how to work with the Virtual Machine (VM) Host PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running demo projects for these programs on a phyCORE product as well. Information on how to build a Linux host PC yourself is also a part of this guide.
• Pin Muxing Table:  phyCORE SOMs have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case by case basis. Most of the documentation can be found in the applicable download page of our products.

phyCORE‑i.MX 8M Mini Introduction

The phyCORE‑i.MX 8M Mini belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of the PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a sub-miniature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all EMI (Electro-Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 37 % of all connector pinson the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high noise environments.

phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 8M Mini is a sub-miniature (37 mm x 40 mm) soldered System on Module populated with the NXP® Semiconductor i.MX 8M Mini microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to a 1,27mm pitch BGA Ball. Each signal ball has an associated GND pin which ensures the GND reference for each signal. The ball packages are placed in lines. There is enough space between lines to ensure the possibility of easy routing out of the package. Signal balls for high-speed signals like HDMI are placed on the outer lines, making it easy to route to the top layer of the carrier board. The SOM is designed to support carrier boards with as little as 6 layers to reduce PCB costs. For proper EMC characteristics, it is necessary to place the processor caps directly under the SOM. This required a hole in the carrier board.

The descriptions in this manual are based on the NXP® Semiconductor i.MX 8M Mini. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 8M Mini.

phyCORE‑i.MX 8M Mini Features 

The phyCORE‑i.MX 8M Mini offers the following features:

• Insert-ready, sub-miniature (37 mm x 40 mm) System on Module (SOM) sub-assembly in low EMI design, achieved through advanced SMD technology
• Mounted using BGA Technology
• Populated with the NXP® Semiconductor i.MX 8M Mini microcontroller (BGA486 packaging)
• 1.6 GHz core clock frequency (up to 1.8 GHz)
• Boot from different memory devices (eMMC standard)
• Single supply voltage of +3.3 V with onboard power management
• All controller required supplies are generated onboard
• Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins

• 2 GB (up to 4 GB^[1]) LPDDR4 RAM 

• 4 GB (up to 32 GB^[1]) onboard eMMC
• 4 kB^[1] I²C EEPROM
• Two High-Speed USB 2.0 OTG interfaces

• One 10/100/1000 MBit Ethernet interface (if Ethernet transceiver is mounted)^[2]

• One RGMII interface at TTL level (if Ethernet transceiver is not mounted)^[2]
• Three I²C interfaces
• Two SPI interfaces
• One PCIe interface
• Four UART interfaces
• Four PWM outputs
• One LVDS interface (if MIPI-DSI to LVDS converter is mounted)^[2]
• One MIPI DSI interface (if MIPI-DSI to LVDS converter is not mounted)^[2]
• One MIPI CSI camera interface
• One 4-Bit SD card interface
• One 8-Bit SDIO interface
• SAI audio interface
• Internal RTC
• Available for different temperature grades (Product Temperature Grades)

phyCORE-i.MX8M Mini Block Diagram

phyCORE-i.MX 8M Mini Block Diagram

phyCORE-i.MX 8M Mini Component Placement

phyCORE-i.MX 8M Mini Component Placement (Top)

phyCORE-i.MX 8M Mini Component Placement (Bottom)

phyCORE-i.MX 8M Mini Minimal Operating Requirements

Pin Description

All controller signals extend to BGA Signal Balls (1.27 mm) This allows the phyCORE‑i.MX 8M Mini to be soldered into any target application like a "big chip".

PHYTEC provides a complete pinout table for the phyCORE-i.MX 8M Mini Connector X1. This table contains a complete signal path for the phyCORE‑i.MX 8M Mini and the carrier board phyBOARD-Polis, including signal names, pin muxing paths, and descriptions specific to each pin. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found with the pinout table.

ftp://ftp.phytec.de/pub/Products/phyBOARD-Polis-iMX8M_Mini/TechData/phyCORE-i.MX8M_MINI_Pin_Muxing_Table.A0.xlsx

Power

The phyCORE‑i.MX 8M Mini operates off of a single power supply voltage. The following sections discuss the primary power pins on the phyCORE-i.MX 8M Mini Connector X1 in detail.

Primary System Power (VDD_3V3)

The phyCORE‑i.MX 8M Mini operates with a single primary voltage supply. Onboard switching and low dropout regulators generate the 2.5 V, 1.8 V, 1.2 V, 1.1 V, 0.9 V, and 0.8 V voltage rails required by the i.MX 8M Mini CPU and onboard components from the input voltage VDD_3V3.

For proper operation, the phyCORE‑i.MX 8M Mini must be supplied with a voltage source of 3.3 V +4.5 %-4 % with 2 A load at the VDD pins on the phyCORE-i.MX 8M Mini Connector X1.

In order to perform a full power cycle of the phyCORE-i.MX 8M Mini, including the SNVS domain of the PMIC and the CPU, the voltage input rail VDD_3V3 has to remain below 0,3 V for at least 600 ms.

     VDD_3V3:     X1  →   A75, A76, A77, A78

Connect all VDD_3V3 input pins to your power supply and, at the very least, the matching number of GND pins.

     Corresponding GND:     X1  →  B36, B37, B38, B39, B40, B41

Please refer to the section Pin Description for information on additional GND pins located at the phyCORE-i.MX 8M Mini Connector X1.

Power Management IC (PMIC)(U3)

The phyCORE-i.MX 8M Mini provides an onboard Power Management IC (PMIC) at position U3 to generate different voltages required by the microcontroller and the onboard components. The Powering Scheme figure presents a graphical depiction of the powering scheme. The PMIC supports many functions like on-chip RTC and different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 8M Mini via the onboard I²C bus (I2C1) (I²C Interface). The I²C address of the PMIC is 0x08.

Power Domains

phyCORE-i.MX 8M Mini Powering Scheme

External voltages:

• VDD_3V3:     SOM input supply voltage
• VDD_BAT:     Backup supply (connected to VBAT)

Internally generated voltages:

External Logic Supply Voltage

The voltage level of the phyCORE’s logic circuitry is VDD_3V3_S (3.3 V) which is derived from the SOM main input voltage, VDD_3V3. In order to follow the mandatory power-up and power-down sequencing for the i.MX 8M Mini, external devices have to be supplied by the I/O supply voltage VDD_3V3_S which is brought out at pin E14 of the phyCORE-Connector. The use of VDD_3V3_S ensures that external components are only supplied when the supply voltages of the i.MX 8M Mini are stable.

Backup Power (VBAT)

To back up the i.MX 8M Mini's low power domain (NVCC_SNVS) and its RTC, a secondary 3.3 V voltage source can be attached to the phyCORE-i.MX 8M Mini at pin A79.

Reset

Pin C43 on the phyCORE-Connector is designated as an open-drain reset input with a pull-up resistor, that triggers a hard reset of the module. The external reset signal is connected to the enable signal of the voltage supervisor U41, which triggers a watchdog event in the PMIC resulting in a hard reset of the module. For debouncing purposes, the U41 delays the signal by 8,804 ms.

For PCB version 1518.0, 1518.1a and 1518.2 additional precautions have to be taken regarding the undervoltage detection of the phyCORE-i.MX 8M Mini. X_nPOR_IN must be held on a logical low level, as long as VDD_3V3 is below 3.135 V. If this is not considered in the design of a baseboard, there is a small chance, the SoM could enter an unspecified mode of operation. PCB version 1518.3 and higher will not require this feature any longer, yet it is good engineering practice, to monitor all voltage rails at all times.

The PMIC reset output signal POR_B is made available at the phyCORE-Connector through a buffer as the open drain signal X_nPOR_OUT_OD. X_nPOR_OUT_OD is not connected to a pull-up resistor on the module. This leaves the user the freedom to choose the voltage domain used on the target hardware.

In case of a hard reset, regardless if it was triggered internally or externally, the PMIC holds the POR_B signal low until the module voltages are at stabilized levels. The POR_B signal is released approximately 11 ms after the last module voltage is correctly generated.

In order to perform a full power cycle of the phyCORE-i.MX 8M Mini, including the SNVS domain of the PMIC and the CPU, the voltage input rail VDD_3V3 has to remain below 0,3 V for at least 600 ms.

phyCORE-Connector Reset Pins

System Boot Configuration

Most features of the i.MX 8M Mini microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

• Boot mode selection
• Boot device selection
• Boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 8M Mini after POR release. The ROM code detects the boot mode by using the boot mode pins (BOOT_MODE[1:0]), while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO pins (BOOT_CFGx[14:12]).

Boot Mode Selection

The i.MX 8M Mini microcontroller boot mode is determined by the configuration of two boot mode inputs BOOT_MODE[1:0] during the reset cycle of the operational system. These inputs are brought out at the phyCORE‑Connector pins X_BOOT_MODE[1:0] (X1D1, X1C1). Possible settings of pins X_BOOT_MODE0 (C15) and X_ BOOT_MODE1 (C16) and the resulting boot configuration of the i.MX 8M Mini:

phyCORE-i.MX 8M Mini Boot Modes

The BOOT_MODE[1:0] lines have 10 kΩ pull-up and pull-down resistors populated on the module. Leaving the two pins unconnected sets the controller to internal boot (Boot Mode 2). For serial boot (Boot Mode 1), the ROM code polls the communication interface selected, initiates the download of the code into the internal RAM, and triggers its execution from there. Please refer to the i.MX 8M Mini Reference Manual for more information.

In Boot Mode 0 and 2, the ROM code finds the bootstrap in permanent memories, such as eMMC or SD cards, and executes it. The boot device selection and the required interface configuration are accomplished with the help of the eFUSEs and/or the corresponding GPIO input. 

Boot Device Selection and Configuration

In normal operation (Boot Mode 0 or 2), the boot ROM uses the BOOT_MODE state and eFUSEs to determine the boot device.

During development, it is advisable to set the Boot Source to “Internal Boot” (Boot Mode 2) so that choosing and configuring the boot device using GPIO pin inputs is available. The input pins are sampled at boot and, if the BT_FUSE_SEL fuse is not blown, override the values of the corresponding eFUSEs BOOT_CFGx[14:0].

The phyCORE-Connector Boot Configuration Pins table lists the eFUSEs BOOT_CFGx[14:0] and the corresponding input pins. On the phyCORE‑i.MX 8M Mini, the GPIOs have 10 kΩ pull-up and pull-down resistors preinstalled to configure eFUSEs BOOT_CFGx[14:0] in accordance with the module features.

The specific boot configuration settings, which are set by the onboard configuration resistors, can be changed by modifying the resistors on the module or by connecting a configuration resistor (e.g. 10 kΩ) to the configuration signal. Please consider that any change of the default boot configuration can also influence other boot modes, which might result in faulty boot behavior.

Please refer to the i.MX 8M Mini Reference Manual for further information about the eFUSEs and the impact of the settings at the boot configuration pins.

phyCORE-Connector Boot Configuration Pins

System Memory

The phyCORE‑i.MX 8M Mini provides four types of onboard memory:

• One bank LPDDR4 RAM: 2 GB LPDDR4 RAM (up to 4 GB)^[3]

• eMMC: 8 GB (up to 32 GB)
• Quad SPI-NOR: 32 MB (up to 256 MB)^[3]
• I²C-EEPROM: 4 kB^[3]

The following sections detail each memory type used on the phyCORE‑i.MX 8M Mini.

LPDDR4-RAM (U2)

The RAM memory of the phyCORE‑i.MX 8M Mini is comprised of one 32 bit wide bank with two 16-bit wide LPDDR4-RAM chips in one integrated circuit. The chips are connected to the DDR interface called the DDR Controller (DDRC) of the i.MX 8M Mini microcontroller.

Typically, the LPDDR4-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 8M Mini controller. Refer to the i.MX 8M Mini Reference Manual for accessing and configuring these registers.

QUAD SPI-NOR (U7)

The Quad NOR flash memory at U7 is connected to the Flexible Serial Peripheral Interface A (FlexSPI A). The connected flash device uses the provided Chip Select 0 signal (QSPIA_SS0). The NOR flash device is powered by the 1.8 V supply voltage VDD_1V8. No further voltages are required to program the device.

As of the printing of this manual, these NOR flash devices generally have a life expectancy of at least 100,000 erase cycles per sector and a data retention rate of typically 20 years. Any parts that are footprint (TBGA-24 5x5) and functionally compatible may be used with the phyCORE-i.MX 8M Mini.

For more information about the NOR Flash, please refer to the i.MX 8M Mini Reference Manual.

eMMC Flash Memory (U21)

The managed NAND (eMMC) flash device is powered by the supply voltages VDD_1V8 (1.8 V) and VDD_3V3_S (3.3 V). No further voltages are required for programming the device. The eMMC memory is connected to the SDIO3 interface of the i.MX 8M Mini. Any parts that are footprint (BGA153) and functionally compatible may be used with the phyCORE-i.MX 8M Mini.

For more information about the eMMC, please refer to the i.MX 8M Mini Reference Manual.

I²C EEPROM (U13)

The phyCORE‑i.MX 8M Mini is populated with a 4 kB I²C^[4]EEPROM at U13. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I²C port 1 of the i.MX 8M Mini. The control registers for I²C port 1 are mapped between addresses 0x021A 8000 and 0x021A BFFF. Please see the i.MX 8M Mini Reference Manual for detailed information on the registers.

The three lower address bits are fixed to zero which means that the EEPROM can be accessed at I²C address 0x51.

EEPROM Write Control

The Write Control (WC) signal of the EEPROM is permanently fixed to GND over resistor R106, so the EEPROM is not always write-protected.

Serial Interfaces

The phyCORE‑i.MX 8M Mini provides numerous dedicated serial interfaces, some of which are equipped with a transceiver to allow direct connection to external devices:

• Two SDIO interfaces (4 and 8-Bit)
• Four High-speed UART interfaces.
• Two High-Speed USB OTG interfaces extended directly from the i.MX 8M Mini USB 2.0 PHY
• One 10/100/1000 Mbit Ethernet interface
• Four independent I²C interfaces
• Two Serial Peripheral Interfaces (SPI), extending from the first and second SPI modules (eCSPI1 and eCSPI2) of the i.MX 8M Mini. A third interface can be implemented through the use of GPIOs. See i.MX 8M Mini Reference Manual muxing options.
• Four Serial Audio Interfaces (SAI), originating from the i.MX 8M Mini I²S module.
• One PCI Express Gen. 2, extending directly from the i.MX 8M Mini PCIe PHY
• One MIPI CSI-2 interface with 4 data lanes and 1 clock lane

The following sections detail each of these serial interfaces.

SDIO Interfaces

The SDIO interfaces are part of the ultra Secured Digital Host Controller and can be used to connect external SD cards, eMMC, or any other device requiring an SDIO interface (examples include WiFI, I/O expansion). The phyCORE‑i.MX 8M Mini features two SDIO interfaces (4 and 8-Bit). On the phyCORE‑i.MX 8M Mini, the interface signals extend from the controller's first and second Ultra Secured Digital Host Controller (uSDHC1/uSDHC2) to the phyCORE-Connector.

The tables below show the locations of the various interface signals on the phyCORE-Connector. The Ultra Secured Digital Host Controller is fully compatible with SD/SDIO 3.0 (200MHz SDR signaling for up to 100 MB/s) and MMC 5.1 (HS400 DDR for up to 400 MB/s). uSDHC1 and uSDHC3 both provide 8-Bit interfaces, and uSDHC2 provides a 4-Bit interface. Refer to the i.MX 8M Mini Reference Manual for more information.

SDIO1 Interface Signal Locations

SDIO2 Interface Signal Locations

uSDHC2 provides dedicated card-detect and write-protect signals. USDHC1 card-detect and write-protect functions may be implemented by using GPIOs of the i.MX 8M Mini. Refer to the i.MX 8M Mini Reference Manual. For more information about SD cards, please refer to the manufacturer's user manual.

Universal Asynchronous Interface

The phyCORE‑i.MX 8M Mini provides four high speed universal asynchronous interfaces. Hardware flow control (RTS and CTS signals) may be implemented through the use of additional GPIO signals. See muxing options in i.MX 8M Mini Reference Manual for more information. Location of the signals on the phyCORE-Connector:

UART Signal Locations

USB OTG Interfaces

The phyCORE‑i.MX 8M Mini provides two high-speed USB OTG interfaces, which use the i.MX 8M Mini’s embedded High-Speed USB 2.0 PHY.

For the use of various USB functionalities, only an external USB Standard-A (for USB host), USB Standard-B (for USB devices), or USB Mini-AB (for USB OTG) connector is needed. The applicable interface signals (DN, DP, ID, and VBUS) are located on the phyCORE‑Connector X1. The locations of the USB OTG interface signals on the phyCORE-Connector X1 can be found in the tables below.

If overcurrent and power-enable signals are needed for the USB host interface, the functionality can be easily implemented through the use of GPIOs.

USB1 OTG Signal Locations

USB2 OTG Signal Locations

Ethernet Interface

Connection of the phyCORE‑i.MX 8M Mini to the World Wide Web or a local area network (LAN) is possible using the onboard GbE PHY at U4. It is connected to the RGMII interface of the i.MX 8M Mini. The PHY operates with a data transmission speed of 10, 100, or 1000 Mbit/s. Alternatively, the RGMII interface which is available on the phyCORE‑Connector can be used to connect an external PHY. In this case, the onboard GbE PHY (U4) must not be populated (see RGMII Interface).

Ethernet PHY (U4)

With an Ethernet PHY mounted at U4, the phyCORE‑i.MX 8M Mini has been designed for use in 10/100/1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE-i.MX 8M Mini Connector X1.

Ethernet Signal Locations

The onboard GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct-connect LAN or a cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface of the i.MX 8M Mini. Please refer to the i.MX 8M Mini Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (ETH0_A±, ETH0_B±, ETH0_C±, ETH0_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals.

Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.

Ethernet PHY Reset

The Ethernet PHY at U4 can be reset with software. The reset input of the Ethernet PHY is connected to the Power-On Reset (POR) signal of the module and to the GPIO RESET_ETHPHY of the i.MX 8M Mini.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 8M Mini is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

RGMII Interface

In order to use an external Ethernet PHY instead of the onboard GbE PHY at U8, the RGMII interface (ENET) of the i.MX 8M Mini is brought out at phyCORE-i.MX 8M Mini Connector X1.

RGMII Interface Signal Locations

SPI Interfaces

The Serial Peripheral Interface (SPI) interface is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI interfaces on the phyCORE‑i.MX 8M Mini Connector X1.

Each SPI interface provides one chip-select signal. The enhanced Configurable SPI (eCSPI) of the i.MX 8M Mini has three separate modules (eCSPI1, eCSPI2, and eCSPI3) which support data rates of up to 20 Mbit/s. The interface signals of the first and second modules (eCSPI1, eCSPI2) are made available on the phyCORE-Connector. The third SPI module can be made available through the i.MX 8M Mini pin muxing options. Refer to the i.MX 8M Mini Reference Manual for more detailed information. All modules are master/slave configurable. The following tables list the SPI signals on the phyCORE-i.MX 8M Mini Connector X1:

SPI1 Interface Signal Locations

SPI2 Interface Signal Locations

I²C Interface

The Inter-Integrated Circuit (I²C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 8M Mini contains four identical, independent Multimaster fast-mode I²C modules. The interface of three modules is available at the phyCORE-Connector. The first I²C module (I2C1) connects to the onboard EEPROM at U13 (I²C EEPROM), the PMIC at U3 (Power Management IC), the Real-Time Clock at U12, and the MIPI to LVDS converter at U5 LVDS (FlatLink). The MIPI to LVDS converter connects to the I2C1 interface through the level shifter U22. The voltage domain in this part of the bus is 1,8 V.

The following tables list the I²C ports on the phyCORE-Connector, separated by interface:

I2C2 Interface Signal Locations

I2C3 Interface Signal Locations

I2C4 Interface Signal Locations

Onboard I2C Bus

The first I²C module (I2C1) connects to the onboard EEPROM at U13 and the PMIC at U3. The following table shows the addresses of all I2C1 devices on the phyCORE-i.MX 8M Mini:

I2C1 Onboard Bus Addresses

Synchronous Audio Interface (SAI)

The phyCORE-i.MX 8M Mini features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces: SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-i.MX 8M Mini Connector X1. All signals are part of the VDD_3V3_S voltage domain.

SAI1 provides 8-bit transmit and 8-bit receive functionality with receive, transmit, and master clock output. Frame synchronization is available for receive and transmit operations. The tables below show the signal locations for each SAI interface.

SAI1 Signal Locations

SAI2 provides 1-bit transmit and 1-bit receive functionality with receive, transmit, and master clock output. Frame synchronization is available for receive and transmit operations.

SAI2 Signal Locations

SAI3 provides 1-bit transmit and 1-bit receive functionality with receive, transmit, and master clock output. Frame synchronization is available for receive and transmit operations.

SAI3 Signal Locations

SAI5 provides 4-bit receive functionality with receive and master clock output. Frame synchronization is available for receive operations.

SAI5 Signal Locations

PCI Express Interface

The 1-lane PCI Express interface of the phyCORE‑i.MX 8M Mini provides PCIe Gen. 2.0 functionality which supports 5 Gbit/s operation. Furthermore, the interface is fully backward compatible with the 2.5 Gbit/s Gen. 1.1 specification. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented via the use of GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Polis) for a circuit example.

Position of the PCIe signals on the phyCORE‑Connector X1:

PCIe Interface Signal Locations

General Purpose I/Os

The following table lists all pins not used by any of the other interfaces described explicitly in this manual and which, therefore, can be used as GPIO without harming other features of the phyCORE‑i.MX 8M Mini. In addition, most pins directly routed to the phyCORE-i.MX M Mini Connector X1 can be configured as GPIO due to the multiplexing functionality of the i.MX 8M Mini.

For more details on the possible GPIO settings, see the i.MX 8M Mini Reference Manual.

GPIO Pin Locations

JTAG Interface

The phyCORE‑i.MX 8M Mini is equipped with a JTAG interface for downloading program code into the external flash, internal controller RAM, or for any debugging programs that are executed. Location of the JTAG pins on the phyCORE-i.MX 8M Mini Connector X1:

JTAG Interface Signal Locations

Display Interfaces

In the industrial market, LVDS is the default display with the best long-time availability. MIPI is normally used for the consumer market. For this reason, PHYTEC has added a MIPI to LVDS converter as part of the SOM design. This allows a normal LVDS display to be used in industrial applications. Alternatively, phyCORE-i.MX 8M MINI can be ordered without the converter so that a MIPI display can be used.

LVDS (Flatlink)

The LVDS interface of the phyCORE-i.MX 8M Mini, using an optional MIPI to LVDS converter, is converted from the i.MX 8M Mini’s MIPI-DSI2 interface. The converter supports resolutions of up to 1920x1200 (WUXGA) at 60 frames per second with 24 bpp and reduced blanking. It is also suitable for resolutions of 1366x768 with 60 frames per second and 1280x800 at 60 frames per second, both 18 and 24 bpp. The LVDS interface is available only when U5 is mounted. Please refer to the Texas Instruments SN65DSI83 datasheet for more information.

Location of the LVDS signals on the phyCORE-i.MX 8M Mini Connector:

LVDS Interface Signal Locations

MIPI-Display Serial Interface 2 (MIPI-DSI2)

The i.MX 8M Mini’s MIPI-DSI2 interface provides resolutions of up to 1920x1080 at 60 frames per second. It uses four data channels and one clock channel. The MIPI-DSI2 interface is only available if the MIPI to LVDS converter U5 is not mounted. The interface provides a maximum bit rate of 1,5 Gbit/s.

MIPI DSI-2 Interface Signal Locations

MIPI CSI-2 Camera Interface

The phyCORE-i.MX 8M Mini features a MIPI CSI-2 camera interface. It is routed directly to the phyCORE-i.MX 8M Mini Connector X1. The interface provides a maximum bit rate of 1,5 Gbit/s. It uses four data channels and one clock channel. All signals, including control signals and an I²C interface, to use the camera interfaces, according to PHYTEC's phyCAM‑S standard, are available at the phyCORE‑i.MX 8M Mini Connector.

The i.MX 8M Mini microcontroller is equipped with one MIPI camera interface. The following table shows the location of all MIPI CSI-2 interface signals on the phyCORE-Connector X1:

Camera Interface MIPI CSI-2 Signal Locations

CPU Core Frequency Scaling

The i.MX 8M Mini on the phyBOARD‑Polis is able to scale the clock frequency and the voltage. This is used to save power when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as Dynamic Voltage and Frequency Scaling (DVFS).

The i.MX 8M Mini BSP supports the DVFS feature. The Linux kernel provides a DVFS framework that allows each CPU core to have a minimum/maximum frequency as well as the applicable voltage and a governor that regulates these values depending on the system load. Depending on the i.MX 8M Mini variant used, several different frequencies are supported. Further details on how to configure this governor can be found in the phyCORE-i.MX 8M BSP Manual.

Technical Specifications

The module’s profile is a maximum of 10 mm thick, with a maximal component height of 3.0 mm on the bottom (connector) side of the PCB and approximately 5.0 mm on the top (microcontroller) side. The board itself is approximately 1.4 mm thick.

phyCORE-i.MX 8M Mini Footprint

Additional Specifications:

Technical Specifications

These specifications describe the standard configuration of the phyCORE‑i.MX 8M Mini as of the printing of this manual.

phyCORE-i.MX 8M Mini Power Consumption

In order to illustrate the power consumption of the phyCORE-i.MX 8M Mini in various realistic load scenarios, multiple measurements were conducted. It is important to note, that these measurements are a sole depiction of the specific stresses, asserted to the SOM through the specified software applications. The given results may be utilized to dimension a power supply for the phyCORE-i.MX 8M Mini on custom hardware. Especially custom software may yield different results in power consumption compared to the values posted in the table below. It is vital that power consumption of the phyCORE-i.MX 8M Mini is evaluated when it is intended to be used with custom software.

The power consumption of the phyCORE-i.MX 8M Mini was measured at the 3.3 V SOM input voltage rail. The results below do not account for a possible current draw through the switched 3.3 V voltage rail VDD_3V3_S. The SOM is capable of drawing the measured current continuously. In case the ambient temperature varies greatly from the underlying test conditions for this measurement, a difference in power consumption may be observed.

In the applicable datasheet, the manufacturer of the i.MX 8M Mini CPU defines maximum current ratings for each voltage rail, which are designated as a guideline during the dimensioning of the on-module power supply and the resulting voltage rails. The mentioned absolute current ratings were considered in the design process of the phyCORE-i.MX 8M Mini's power infrastructure, yet do not represent realistic use cases for the SOM.

Product Temperature Grades

The feasible operating temperature of the SOM highly depends on the use case of your software application. Modern high-performance microcontrollers and other active parts, such as the ones described within this manual, are usually rated by qualifications based on tolerable junction or case temperatures. Therefore, making a general statement about minimum or maximum ambient temperature ratings for the described SOM is not possible.

However, the above-mentioned parts are available in different temperature qualification levels by the producers. We offer our SOMs in different configurations, making use of those temperature qualifications. To indicate which level of temperature qualification is used for active and passive parts of a SOM configuration, we have categorized our SOMs into three temperature grades.

The Product Temperature Grades table describes these grades in detail. These grades describe a set of components that, in combination, add up to a useful set of product options with different temperature grades. This enables us to make use of cost optimizations depending on the required temperature range.

In order to determine the right temperature grade and whether the minimum or maximum qualification levels are met within an application, the following conditions must be defined by considering the use case:

• Determined the processing load for the given software use case
• Maximum temperature ranges of components (Product Temperature Grades)
• Power consumption resulting from a baseload and the calculating power required (in consideration of peak loads as well as time periods for system cooldown)
• Surrounding temperatures and existing airflow in case the system is mounted into a housing
• Heat resistance of the heat dissipation paths within the system along with the considered usage of a heat spreader or a heat sink to optimize heat dissipation

Product Temperature Grades

phyCORE-i.MX 8M Mini FTGA Mounting

The phyCORE i.MX 8M Mini uses Fused Tin Grid Array (FTGA) to mount to a carrier board (for example, phyBOARD-Polis). FTGA provides several advantages:

• An easy-to-produce design
• Permanent and robust mechanical connection to the carrier application
• Relaxed fit in regards to onboard circuitry
• Easy to design in any application
• Low profile
• Cost-efficient

For more information about FTGA soldering, please refer to the PHYTEC FTGA Soldering Guide (LAN-095e.A1 i.MX 8M Mini Fused Tin Grid Array (FTGA) Soldering Information).

Hints for Integrating and Handling the phyCORE‑i.MX 8M Mini

Integrating the phyCORE-i.MX 8M Mini

Apart from this hardware manual, more information is available to facilitate the integration of the phyCORE‑i.MX 8M Mini into customer applications.

1. The design of the phyBOARD‑Polis can be used as a reference for any customer application.
2. Many answers to common questions can be found at: https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-mini-nano/or https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/
3. The link “Carrier Board” within the category Dimensional Drawing leads to the layout data as shown in phyCORE-i.MX 8M Mini Footprint. It is available in different file formats. The use of this data allows the user to integrate the phyCORE-i.MX 8M Mini SOM as a single component of your design.
4. Different support packages are available for support in all stages of embedded development. Please visit http://www.phytec.de/de/support/support-pakete.html or https://www.phytec.eu/support/support-packages/ or contact our sales team for more details.
5. Many answers to common questions can be found at:
   https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-mini-nano/
   or
   https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-mini-nano/

Integrating the phyCORE into a Target Application

Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. As a minimum, all GND pin neighboring signals which are being used in the application circuitry should be connected to GND.

Handling the phyCORE-i.MX 8M Mini

phyCORE Module Modifications

The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board as well as surrounding components and sockets remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework stations, or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

phyCORE-i.MX 8M Mini on the phyBOARD-Polis

Hardware Overview

The phyBOARD‑Polis for phyCORE-i.MX 8M Mini is a low-cost, feature-rich software development platform supporting the NXP Semiconductors i.MX 8M Mini microcontroller. Due to numerous standard interfaces, the phyBOARD‑Polis can serve as the bedrock for any application. At the core of the phyBOARD‑Polis is the PCL-069/phyCORE-i.MX 8M Mini System On Module (SOM) containing the processor, DRAM, eMMC, power regulation, supervision, transceivers, and other core functions required to support the i.MX 8M Mini processor. Surrounding the SOM is the PB-02820-xxxxx.Ax/phyBOARD‑Polis carrier board, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals.

The PCL-069 System On Module connects to the phyBOARD‑Polis carrier board using a Ball Grid Array (BGA). The PCL-069 SOM is soldered directly onto the phyBOARD‑Polis using PHYTEC's Direct Solder Connect technology. This solution offers an ultra-low-cost Single Board Computer for the i.MX 8M Mini processor, while maintaining most of the advantages of the SOM concept. 

phyBOARD-Polis Concept

phyCORE carrier boards are designed and tested to be used in:

• series products
• evaluating, testing, and prototyping PHYTEC System on Modules in laboratory environments prior to their use in customer designed applications.

PHYTEC phyCORE carrier boards are fully equipped with all mechanical and electrical components necessary for a fast, secure start-up. Subsequent communication to and programming of applicable PHYTEC System on Modules (SOM) is made easy.

This modular development platform concept includes the following components:

• The phyCORE-i.MX 8M Mini module populated with the i.MX 8M Mini microprocessor and all applicable SOM circuitry such as LPDDR 4 SDRAM, managed NAND, Ethernet transceiver, WiFi, and PMIC to name a few.
• The phyBOARD-Polis carrier board offers all essential components and connectors for a start-up including: a power supply for 24 V input voltage, interface connectors such as USB micro-AB, USB A, and Ethernet RJ-45 which enable the use of the SOM’s interfaces with standard cables.

The carrier board can also serve as a reference design for the development of custom target hardware in which the phyCORE SOM is deployed. Carrier board schematics are available under a Non-Disclosure Agreement (NDA). Reuse of carrier board circuitry enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

SBCplus Concept

The SBCplus concept was developed to meet the many, small differences in customer requirements with little development effort. This greatly reduces the time-to-market. The core of the SBCplus concept is the SBC design library (a kind of construction set) that consists of a large number of function blocks (so-called "building blocks") which are continuously being refined and updated.

Recombining these function blocks allows PHYTEC to develop a customer-specific SBC within a short time. We are able to deliver production-ready custom Single Board Computers within a few weeks at very low costs. The already developed SBCs, such as the phyBOARD-Polis, each represent a combination of different customer wishes. This means all necessary interfaces are already available on the standard versions, allowing PHYTEC SBCs to be integrated into a large number of applications without modification.

For any necessary detail adjustment, extension connectors are available which allow a wide variety of functions to be added.

phyBOARD-Polis Features

The phyBOARD‑Polis i.MX 8M Mini supports the following features:

• Developed in accordance with PHYTEC's new SBCplus concept (SBCplus Concept)
• Populated with PHYTEC’s phyCORE-i.MX 8M Mini SOM (via BGA mounting)
• Dimensions 100 mm × 100 mm
• Boot from eMMC or SD Card
• Max. 1.6 GHz core clock frequency and up to four cores
• Wide input of voltage ranges (12 V – 24 V through external power module)
• 2GB RAM
• 8GB eMMC
• 4kB EEPROM
• One RJ45 jack for 10/100/1000 Mbps Ethernet

• One USB 2.0 host interface brought out to a USB Standard-A connector^[5]

• One USB OTG interface available at a USB Micro-AB connector
• One Secure Digital / Multi-Media Memory Card interface brought out to a Micro-SD connector
• One LVDS interface brought out via an A/V connector
• One MIPI-DSI2 brought out via an A/V connector (if MIPI to LVDS converter is not mounted)
• One MIPI CSI-2 camera interface via the phyCAM-M connector
• One PCIe interface brought out to a Mini PCI Express connector
• RS-232 / RS-485 transceiver supporting UART4 including handshake signals with data rates of up to 1 Mbps (2×5 pin header 2.54 mm)
• Reset Button
• ON/OFF Button
• WiFi via the SD1 SDIO interface
• One multicolor LED
• SAI Audio brought out via A/V connector
• Voice array connector
• JTAG via evaluation adapter
• Expansion connector for different interfaces:
  • I²C
  • SPI
  • UART
  • USB
  • SPDIF
• TPM via SPI or I²C

phyBOARD-Polis Block Diagram

phyBOARD-Polis Block Diagram

phyBOARD-Polis Component Placement

phyBOARD-Polis Components (Top)

phyBOARD-Polis Components (Bottom)

phyBOARD-Polis Component Overview

The phyBOARD‑Polis features many different interfaces and is equipped with the components listed in table Connectors and Pin Headers. For a more detailed description of each component, refer to the appropriate section listed in the table below. phyBOARD-Polis Components (Top) and phyBOARD-Polis Components (Bottom) highlight the location of each component for easy identification. 

Connectors and Pin Headers

This is a list of all available connectors on the phyBOARD-Polis. 

phyBOARD-Polis Pin Headers and Connectors

LEDs

The phyBOARD-Polis is populated with one LED, which is user-programmable. phyBOARD-Polis Components (Top) shows the location of the LED.

phyBOARD-Polis LED Description

Switches

The phyBOARD-Polis is populated with 3 switches. The tables below show their function:

phyBOARD-Polis S2/S3 Descriptions

Additionally, S1 is a 5-port dip switch bar populated for several functions:

• Boot Selection (see Multi-port Switch)
• SD card or WIFI Selection
• UART3 destination (A/V or FTDI) (see USB Debug)

Jumpers

The phyBOARD-Polis comes pre-configured with several solder jumpers (J). The jumpers enable the flexible configuration of a limited number of features for development purposes.

phyBOARD-Polis SBC Component Details

This section provides a more detailed look at the phyBOARD‑Polis components. Each subsection details a particular connector/interface for configuring that interface.

phyCORE-Connection (X3)

phyCORE Connector (X3)

Power Supply (X33)

Power Supply Connector (X33)

The phyBOARD-Polis is available with one power supply connector, a 2-pole Combicon Phoenix connector suitable for a single supply voltage (X33).

The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE mounted on the phyBOARD-Polis, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board.  The power input is protected against overcurrent with a fuse (F1). A suppressor diode (D36) protects against polarity reversal. The pin assignment of the power input connector X33:

X33 Pin Assignment

Power Design Considerations

It is recommended to route high current rails, like the SOM supply voltage, as planes to keep series resistance at a minimum. The same thing should be applied to ground paths. For more information, see phyCORE-i.MX 8M MINI Power Consumption.

UART Connectivity (X8 and X9)

UART Connector (X9)

The phyCORE-i.MX 8M Mini features 4 UART interfaces. On the phyBOARD-Polis, TTL level UART2 is available at the A/V connector (X18) and TTL level UART4 is available at the expansion connector (X8). The availability of UART3 at the expansion connector depends on the state of the debug USB port and the configuration of switch S1 (Multi-port Switch) If a USB device is connected to the debug USB port (USB Debug), UART3 will only be available for the FTDI U66. The following is a detailed description of UART states and conditions:

• UART1:
  • U84 gives the option to use the UART1 default muxing option or the alternative muxing option SAI2_RXC and SAI2_RXFS for UART1 functionality. S1 (Multi-port Switch, pad 3) controls the configuration of U84.
  • U83 makes UART1 (default or alternative assignment) available for the FTDI U66 or the conversion to RS232/RS485. If a USB device is plugged into the debug USB port (USB Debug), U83 will route UART1 to U66. U83 output is twisted.
  • U85 gives the option to use the UART1 RS232/RS485 signal either for conversion to RS232 or RS485 via U78 or U77. S1 (pad 5) controls the configuration of U84. SAI2_RXD0 and SAI2_TXFS are used for handshake functionality.
• UART2: Available at connector X18
• UART3: U82 gives the option to route UART3 to U87 as debug UART or to route UART3 to the expansion connector X8. In case a USB device is plugged into the debug USB port (USB Debug), U83 will route UART1 to U87. 
• UART4: Available at expansion connector X8 and voice array connector X38

Further information on the switch S1 can be found in Multi-port Switch. Further information on the expansion connector X8 can be found in the section Expansion Connector. The following table shows the signal mapping of the RS-232 and RS-485 level signals at connector X9:

X9 Pin Assignment

UART Design Consideration

When designing a custom carrier board, remember the TTL level is 3.3 V. Route signals as single-ended 50 Ohm lines.

Ethernet Connectivity (X1)

Ethernet Connector (X1)

The phyBOARD‑Polis is equipped with an RJ45 connector supporting a 10/100/1000Base-T network connection. The LEDs for LINK (green) and ACTIVITY (yellow) indication are integrated into the connector. The Ethernet transceiver supports Auto MDI-X, eliminating the need for a direct connect LAN or cross-over cable. They detect the TX and RX pins of the connected device and automatically configure the PHY TX and RX pins accordingly.

The following table shows the pin assignment of the Ethernet0 connector X1:

X1 Pin Assignment

Ethernet Design Consideration

The data lanes should be routed with a differential impedance of 100 Ohm and kept as short as possible. The center taps of each pair's transformer have to be connected to GND through a 100nF capacitor. The LED pins are open-drain outputs of the SOM without a resistor, so they should be connected to the cathodes of the LEDs through a suitable resistor.

USB OTG and 2.0 Connectivity (X2 and X5)

USB OTG and 2.0 Connectors (X2 and X5)

The phyBOARD-Polis provides one USB 2.0 and one USB OTG interface. 

USB1 is accessible at the USB Micro-AB connector X2 and is configured as USB OTG. USB OTG devices are capable of initiating a session, controlling the connection, and exchanging host and peripheral roles between each other. This interface is compliant with USB revision 2.0. USB2 is accessible at the Standard-A connector X5 and is configured as a USB host.

The following tables show the pin assignments of the USB OTG and USB 2.0 interface:

USB OTG - X2 Pin Assignment

USB 2.0 - X5 Pin Assignment

USB Design Consideration

The data lanes should be routed with a differential impedance of 90 Ohm and kept as short as possible.

USB Debug (X30)

USB Debug Connector (X30)

The phyBOARD-Polis offers a USB debug interface, that is accessible via the USB micro-AB connector X30. When a USB device is plugged into X30, UART3 will automatically be routed to the UART to USB converter U87. The following table shows the pin configuration of the debug USB micro-AB connector X30:

X30 Pin Assignment

Debug Design considerations

The UART data signals to the UART to USB converter should be routed as singled ended signals with an impedance of 50 Ohm and kept as short as possible. The USB data lanes should be routed with a differential impedance of 90 Ohm and kept as short as possible.

Secure Digital Memory / MultiMedia Card (X4)

SD Card / MM Card Connector (X4)

The phyBOARD‑Polis provides a standard microSDHC card slot at X4 for use with SD/MMC interface cards. It allows for a fast, easy connection to peripheral devices like SD and MMC cards. Power to the SD interface is supplied by inserting the appropriate card into the SD/MMC connector. It also features card detection, a lock mechanism, and a smooth extraction function by pushing the card in and out.

DIP switch S1 provides a toggle between default and SD card boot. In order to boot from SD card, S1 (pads 1-12) must be switched ON (refer to Multi-port Switch for further information).

X4 Pin Assignment

SD / MM Card Design Considerations

Series resistors in data and clock signals should be placed as close as possible to the signal source. For I/O signals this means two resistors in one electric net are recommended. The voltage of the SD2 signal lanes is NVCC_SD2 and can switch between 1.8 V and 3.3 V. The supply voltage of the SD card remains 3.3 V and should not be connected to NCVV_SD2. All signals should be routed as 50 Ohm singled ended lines.

PCIe Connectivity (X6)

PCIe Connector (X6)

The 1-lane PCI express interface of the phyBOARD‑Polis provides PCIe Gen. 2.0 functionality, which supports 5 Gbit/s operations. The interface is fully backwards compatible with the Gen. 1.1, 2.5 Gbit/s specification. Various control signals are implemented with GPIOs. The pin assignment of the Mini PCI Express connector is shown in the following table:

X6 Pin Assignment

PCIe Design Considerations

100nF AC-Coupling capacitors are placed close to output pins of the i.MX 8M Mini on the PCL-069 in series to the TX-Lanes. No further TX coupling capacitors are needed. The differential impedance should be 85 Ohm.

Camera Connections

phyCAM-M MIPI CSI-2 Camera Connector (X10)

 phyCAM-M MIPI CSI-2 Camera Connector (X10)

The phyCORE-i.MX 8M Mini on the phyBOARD-Polis offers one interface to connect to digital cameras with the MIPI CSI-2 interface. The signals of the Camera Serial Interface (CSI) are available as a multi-lane LVDS camera interface together with an I²C interface to allow for a direct connection of appropriate camera modules. On the phyBOARD-Polis, the CMOS Camera Interface is brought out as a phyCAM-M camera interface at connector X10. Information on the phyCAM-M standard and other possibilities can be found in the phyCAM manual:  https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-748e_10.pdf.

Pin assignment of the phyCAM-M MIPI CSI-2 connector X10:

X10 Pin Assignment

CAN FD (X7)

CAN FD (X7)

The CAN with Flexible Data-Rate (CAN FD) is an updated extension of the original CAN protocol. This enables extra data bytes and flexible bit rates. In general, the CAN FD offers 3 benefits to regular CAN:

1. Increased Data Length
   CAN FD supports up to 64 data bytes per data frame vs. 8 data bytes for regular CAN.
2. Increased Speed
   CAN FD supports dual bit rates: normal 1Mbit/S bit rate of a regular CAN and data bit rates up to 5Mbit/s, depending on network and transceiver types.
3. Improved Reliability
   CAN FD uses an improved cyclic redundancy check (CRC), lowering the risks of undetected errors.

Pin assignment of the CAN FD Connector X7:

X7 Pin Assignment

Audio/Video Connectors (X16 and X18)

Audio/Video Connectors (X16 and X18)

The Audio/Video (A/V) connectors X16 and X18 provide an easy way to add typical A/V functions and features to the phyBOARD‑Polis. Standard interfaces such as parallel display, I²S, and I²C as well as different supply voltages are available at the two 2 mm pitch dual inline sockets. 

The A/V connector is intended for use with phyBOARD Expansion Boards^[6]and to add specific audio/video connectivity with custom expansion boards. A/V connector X16 makes all data and clock signals for display connectivity available. X18 provides signals for audio and touch screen connectivity as well as an I²C bus and additional control signals.

Pin assignments for A/V connectors X16 and X18:

X16 A/V Connector Pin Assignment

X18 A/V Connector Pin Assignment

A/V Design Consideration

All signals should be routed as short as possible and as 50 Ohm single-ended lines.

Voice Array Connector (X38)

Voice Array Connector (X38)

The phyBOARD-Polis offers a 2x9 socket as a voice array connector with UART, I2C, and I2S functionality. The following table shows the pin assignment of the voice array connector X38:

X38 Pin Assignment

Voice Array Design Considerations

All signals should be routed as short as possible and as 50 Ohm single-ended lines.

Expansion Connector (X8)

Expansion Connector (X8)

The expansion connector X8 provides an easy way to add other functions and features to the phyBOARD‑Polis. Standard interfaces such as USB, SPDIF, JTAG, UART, SPI, and I²C as well as different supply voltages and some GPIOs are available at the female expansion connector. The expansion connector is intended for use with phyBOARD Expansion Boards and to add specific functions with custom expansion boards. Information on the expansion boards available for the expansion connector can be found in the Application Guide for phyBOARD Expansion Boards (L-793e).

Pin assignment of the expansion connector X8: