Information on this Manual

This hardware manual describes the PCL-079 (FPSC) System on Module, referred to as phyCORE®-i.MX 95, and the PCM-937-L, referred to as Libra Development Board. This manual also specifies the phyCORE-i.MX 95 and Libra Development Board's design and function. Precise specifications for the NXP® Semiconductor i.MX 95 microcontrollers can be found in the i.MX 95 Microcontroller Data Sheet/Reference Manual.

There will be several changes and additions to this manual. New versions will be released in the future with no notice. Please make sure that you are using the latest version of this manual when working with your product.

Future Proof Solder Core

The PCL-079 System on Module, referred to as phyCORE®-i.MX 95 FPSC, is designed according FPSC Gamma Feature Set Specifications (LAN-118e.A0).

Design Considerations

The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and is known to work. The schematics have been re-formatted to fit better in this hardware manual.

Many hardware examples and suggestions are given in the following pages. Designing the phyCORE System on Module onto a Carrier Board is generally straightforward. However, before committing to a particular active component selection when designing a carrier board, it is wise to check out the software driver support for those components. A particular device may be supported in, for example, Linux but not in Windows Embedded Compact 7. Your overall project may go smoother if you pick components that are already supported in your target OS. The premade selections for our reference designs, for example our Single Board Computers, are typically focused on using components that are well supported under Linux.

Specific details may need to be considered when designing a customer-specific carrier board. For design information on carrier board components, please check the Design Considerations in each component section of phyCORE-i.MX 95 on the Libra Development Board. Be aware that not all components need to be considered when designing your own carrier board.

Preface

As a member of PHYTEC's product family, the phyCORE® SoM can be populated with different controllers, various types of memory (RAM, NAND flash, eMMC), and many other features. This, in turn, offers increased types of functions and configurations. PHYTEC supports a variety of 8/16/32/64-bit controllers in two ways:

1. As the basis for Rapid Development Kits which serve as a reference and evaluation platform
2. As insert-ready, fully functional phyCORE® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "reinvent" microcontroller circuitry. Furthermore, much of the value of the phyCORE® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative, full-system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®

PHYTEC System on Modules are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Product Change Management and Information Regarding Parts Populated on the SoM

With the purchase of a PHYTEC SoM / SBC, you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our Product Change Management (PCM) team of developers is continuously processing all incoming Product Change Notifications (PCNs) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.

Our general philosophy here is: We will never discontinue a product as long as there is a demand for it.

To fulfill this, we have established a set of methods to fulfill our philosophy:

Avoidance strategies:

• Avoid changes by evaluating the longevity of parts during the design-in phase.
• Ensure the availability of equivalent second source parts.
• Stay in close contact with part vendors to keep up with roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

• Ensure long-term availability by stocking parts through last-time buy management according to product forecasts.
• Offer long-term frame contracts to customers.

Change management in cases of functional changes:

• Avoid impacts on product functionality by choosing equivalent replacement parts.
• Avoid impacts on product functionality by compensating for changes through hardware redesign or backward-compatible software maintenance.
• Provide early change notifications concerning functional, relevant changes to our products.

We refrain from providing detailed part-specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

• Quickstart Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a Board Support Package (BSP), the device tree, and accessing peripherals.
• Hardware Manual:  A detailed description of the System on Module (SoM) and accompanying carrier board. 
• Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; introducing, installing, and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
• BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
• Development Environment Guide:  This guide shows how to work with the Virtual Machine (VM) Host PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running demo projects for these programs on a phyCORE product as well. Information on how to build a Linux host PC yourself is also a part of this guide.
• Pin Muxing Table:  phyCORE SoMs have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case-by-case basis. Most of the documentation can be found on the applicable download page of our products.

These manuals and more can be found in the download section of phyCORE-i.MX 95 Product page.

Conversions, Abbreviations, and Acronyms

Conventions

The conventions used in this manual are as follows:

• Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low or are driving low.
• A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
• The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the address byte. The correct value of the LSB, which depends on the desired command (read (1), or write (0)), must be added to get the complete address byte. For example, if the given address in this manual is 0x41 =>, the complete address byte = 0x83 to read from the device and 0x82 to write to the device
• Tables that describe all settings show the default position in bold, blue text.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of signal.

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document.

phyCORE-i.MX 95 FPSC Introduction

The phyCORE‑i.MX 95 belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of the PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all EMI (Electromagnetic interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 20 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high-noise environments.

phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 95 is a subminiature (48 mm x 45 mm) insert-ready System on Module populated with the NXP® Semiconductor i.MX 95 microcontroller. Its universal design enables it to be inserted into a wide range of embedded applications. All controller signals and ports extend from the controller to surface mount technology (FPSC FTGA 1.27 mm grid) connectors aligning four sides of the board, allowing it to be soldered into any target application like a "big chip".

The descriptions in this manual are based on the NXP® Semiconductor i.MX 95. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 95.

phyCORE-i.MX 95 FPSC Features

The phyCORE‑i.MX 95 FPSC offers the following features:

• Insert-ready, sub-miniature (48 mm x 45 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology
• Mounted using FTGA Direct Solder Connector (FPSC FTGA)
• Populated with the NXP® Semiconductor i.MX 95 microcontroller (19mmx19mm BGA716 packaging)
• Up to 6 ARM-A55 cores (clock frequency up to 2.0 GHz)
• Machine Learning Neuronal Processing eIQ Neutron NPU mit 2 TOP/s
• 1x Cortex M7 core (800 MHz)
• 1x Cortex M33 core (333 Mhz)
• Arm Mali-G310 Graphic Processing Unit (GPU), 3D GPU supporting 64 GFLOPs FP32, OpenGL® ES 3.2, Vulkan® 1.3, OpenCL 3.0, 4Kp60 H.265 and H.264 encode and decode
• Image Signal Processor (up to 500 MP/s)
• Boot from different memory devices (eMMC Flash standard)
• Single supply voltage of +5 V with on-board power management
• IO voltage between 1.8 V (default) and 3.3 V (factory assembly option)
• All controller-required supplies are generated on-board using sophisticated on-board Power Management
• Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins

• up to 16 GB^[1] LPDDR5 RAM (MTS6400)

• up to 128 GB^[1] on-board eMMC
• 4kB^[1]I²C User-EEPROM and 4kB I²C Factory-EEPROM
• 1x USB 3.0/2.0 Type C with PHY, 1x USB 2.0 with PHY

• 2x 1Gbit Ethernet interfaces with TSN support (either one of them with Ethernet transceiver on the phyCORE-i.MX 95 enabling a direct connection to an existing Ethernet network; the second as RGMII Signals at logic-level at the signal pins instead)

• 1x 10G Ethernet interface with TSN support (USXGMII)
• up to 8x I²C interfaces / 2x I³C interfaces
  
• up to 8x SPI interfaces
• 2x PCIe Gen 3.0 (1-lane)
• up to 8x UART interfaces
• up to 5x CAN-FD interfaces
• up to 6x Timer/PWM outputs
• 1x MIPI CSI-2/DSI-2 camera/display interface
• 1x MIPI CSI-2 camera interfaces
• 1x LVDS Tx interface 2 channels x4
• 1x 8-bit uSDHC for eMMC
• 1x 4-bit SD-Card interface
• 1x 4-bit SDIO interface
  
• up to 5x SAI audio interfaces
• 1x SPDIF interface
• Extreme Low Power RTC Module
• 4x temperature sensors to monitor the board's temperature profile
• All processor interfaces available at the SOM Connector
• Available for different temperature grades (see Product Temperature Grades)

phyCORE-i.MX 95 FPSC Block Diagram

phyCORE-i.MX 95 FPSC Component Placement

phyCORE-i.MX 95 FPSC Minimum Operating Requirements

Before the phyCORE-i.MX 95 FPSC can be used, please make sure the host system meets the minimum operating requirements. These include:

• The stable and clean input power supply of 5.0 V with low ESR bulk capacitors (e.g. 2x 47µ/16V MLCC) paired with some HF blocking capacitors (e.g. 100nF MLCC) connected to the input pins as near as possible (phyCORE-i.MX 95 Power Consumption)
• Supply voltage for externally connected peripherals should be controlled by signal X_nPWR_READY to avoid reverse currents (External Logic IO Supply Voltage)
• If external peripherals need a longer reset delay, hold reset signal X_POR_B as long low as needed (Reset)
• Desired boot configuration - default configuration is "Boot from on-board eMMC" (System Boot Configuration)
• To back up the on-board I2C-RTC, connect a buffer voltage source to input pin X_RTC_VBACKUP (Backup Power (X_RTC_VBACKUP), RTC)

Pin Description

All controller signals extend to FPSC footprint. These contacts line four sides of the module (referred to as FPSC footprint). This enables phyCORE-i.MX 95 to be plugged into any target application like a "big chip".

PHYTEC provides a complete pinout table for the phyCORE-i.MX 95 Connector (X1). This table contains a complete signal path for the phyCORE‑i.MX 95 and the Libra Development Board, including signal names, pin muxing paths, and descriptions specific to each pin. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found with the phyCORE-i.MX 95 Pinout Table.

Jumpers

The phyCORE-i.MX 95 FPSC (PCL-079) is jumperless. There are, however, a few jumpers on the Libra Development Board. Information on these jumpers can be found inJumpers.

Power

The phyCORE‑i.MX 95 FPSC operates off of a single power supply voltage. The following section discusses the primary power pins on the phyCORE i.MX 95 FPSC Connector X1 in detail.

Primary System Power (VIN_5V)

The phyCORE‑i.MX 95 FPSC is powered by a primary voltage supply with a nominal value of +5.0 V. On-board switching regulators generate the voltage supplies required by the i.MX 95 MCU and on-board components from the primary 5.0 V supplied to the SOM.

For proper operation, the phyCORE‑i.MX 95 FPSC must be supplied with a voltage source of 4.75 ... 5.25 V with a maximum power consumption of a 4 A load at the VIN_5V pins on the phyCORE.

                VIN_5V:                        X1 → AA1, AA2, AB1, AC1, AC2, AB3, AA4, AC3 

Connect all +5.0 V VIN_5V input pins to your power supply and all GND contacts of the module.

                Corresponding GND:           X1 → all GND contacts of the module

Please refer to section Pin Description for information on additional GND Pins located at the phyCORE i.MX 95 Connector X1.

For information on various power consumption scenarios that PHYTEC has run, go to phyCORE-i.MX 95 FPSC Power Consumption.

Power Management IC (PMIC) (U4/U5/U6)

The phyCORE-i.MX 95 FPSC provides an on-board Power Management IC (PMIC) at position U4 and two slave regulatiors U5/U6 (VDD_ARM/VDD_SOC) to generate different voltages required by the microcontroller and the on-board components. The PMIC supports many functions like different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 95 via the on-board I²C bus (I2C2). The I²C address of the PMIC U4 is 0x08. The slave regulator U5 has I²C bus address 0x2A and U6 0x29.

Power Domains

External voltages to supply the board:

• VIN_5V 5.0 V main supply voltage (4.75 .. 5.25 V / max. 4A)
  
• X_RTC_VBACKUP backup supply voltage for the on-board I2C-Bus RTC U14 (RV-3028-C7)

External Logic IO Supply Voltage

The voltage level of the phyCORE’s logic interface circuitry is VDD_1V8 (1.8 V).

To follow the power-up and power-down sequencing mandatory for the i.MX 95, external devices connected to the phyCORE interface circuitry have to be supplied by an external power supply which is controlled by the output signal X_nPWR_READY (OD driver) which is brought out at pin X1-AB7. X_nPWR_READY should control the external supply voltage which is used to supply the external interface circuitry connected to the phyCORE's interfaces. X_nPWR_READY switches to GND to start the external voltage supply or to switch over a power switch. If the on-board interface voltage (VDD_IO) switches off, X_nPWR_READY is released to high impedance. To raise the signal, an external pull-up resistor (eg. 4k7) is needed. It can be connected to voltage levels up to 10V (used Transistor DMN1260UFA has abs. max. 12V) depending on the external power supply control signal requirement. Use of X_nPWR_READY ensures that external components are only supplied when the supply voltages of the i.MX 95 is stable and avoids undefined return currents while the system is powered down.

Backup Power (X_RTC_VBACKUP)

To back up the on-board I2C-Bus RTC U14 (RV-3028-C7), an external voltage source must be added at Pin X1-AC7 (X_RTC_VBACKUP). The RTC has an extremely low backup current consumption of only 40nA (@3 V).

Manual Power Switch (X_OnOff)

The signal X_OnOff (Pin X1-AC4) is used to manual switch the power of the SOM. X_OnOff signal can be left unconnected if not used. It has a weak on-board pull-up resistor against 1.8 V (VDD_VAON) and is held high as long as VIN_5V is present. To drive the signal to GND, use an open collector driver or push button. For more information about ONOFF refer to the NXP Semiconductor i.MX 95 Reference Manual.

Reset

The X_WDOG_ANY signal (Pin X1-AD6) on the phyCORE-Connector is designated as a "cold reset" input. Driving X_WDOG_ANY to low (has 10k pull-up to default 1.8V supplied by NVCC_AON) will restart the system performing a complete power recycle. X_WDOG_ANY has a 12µs debouncing circuit. This input can be used for a mechanical reset switch button. X_POR_B Signal (Pin X1-AB5) can be used to prevent bootup of the i.MX 95. This can be used as a startup as described in the section Power Management IC. 

System Boot Configuration

Most features of the i.MX 95 microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

• Boot mode selection
• Boot device selection
• Boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 95 after POR. The ROM code detects the boot mode by using the boot mode pins (BOOT_MODE[3:0]), while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO input pins (X_BOOT_MODE[3:0]).

Boot Mode Selection

The boot mode of the i.MX 95 microcontroller is determined by the configuration of four boot mode inputs BOOT_MODE[3:0] during the reset cycle of the operational system. These inputs are brought out at the phyCORE processor pins X_BOOT_MODE[3:0] ((X1-AA7, X1-AA6, X1-AA5, X1-AA4). phyCORE-i.MX 95 Boot Modes shows the possible settings of pins X_BOOT_MODE[3:0] and the resulting boot configuration of the i.MX 95.

The X_BOOT_MODE[3,2,0] lines have 100 kΩ pull-down resistors populated (and unpopulated pull-up resistors) while X_BOOT_MODE[1] has a 4,7 kΩ pull-up resistor on the module in parallel to the internal pull-down resistors of the i.MX 95. Leaving the four pins unconnected sets the controller to boot mode 2, boot from on-board eMMC U7 memory device. The boot configuration settings can be changed by changing the populated resistors configuration on the module or by connecting configuration resistors (e.g. 4,7 kΩ pull-up) to the X_BOOT_MODE configuration signals. The pull-up resistors must be supplied by the right voltage level of (default NVCC_AON=1.8 V, see section External Logic IO Supply Voltage).

The BOOT_MODE is initialized by sampling the BOOT_MODE inputs on the rising edge of the POR_B. After these inputs are sampled, their subsequent state does not affect the contents of the BOOT_MODE internal register. X_BOOT_MODE module input signals are connected only during reset phase to the processor inputs. For runtime the X_UART and X_SAI1 signals are routed through the MUX U3.

System Memory

The phyCORE‑i.MX 95 FPSC provides three types of on-board memory:

^*Factory EEPROM should not be used by the application. It contains module specific information to identify the module during factory handling and testing.

LPDDR5-RAM (U2)

The RAM memory interface of the phyCORE‑i.MX 95 FPSC supports one 32-bit LPDDR5-RAM chip (U2). The memory interface supports MTS6400 transfer speed.

Typically, the LPDDR5-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 95 controller. Refer to the NXP Semiconductor i.MX 95 Reference Manual to access and configure these registers.

eMMC Flash Memory (U7)

The main flash memory of the i.MX 95 is eMMC and is populated at U7. The eMMC Flash memory is connected to the SD1 interface of the i.MX 95.

For more information about the eMMC Flash interface, please refer to the NXP Semiconductor i.MX 95 Reference Manual.

I²C Factory EEPROM (U8)

The phyCORE‑i.MX 95 FPSC is populated with a non-volatile 4 kB I²C EEPROM at U8. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I²C port 1 on the i.MX 95. Please see the NXP Semiconductor i.MX 95 Reference Manual for detailed information on the I²C port 1.

The three lower address bits are fixed to 0x1 which means that the EEPROM can be accessed at I²C address 0x51. The EEPROM has a second address on 0x59, which is called Identification Page, and is reserved for internal PHYTEC uses only.

The device is write proteced per default. Write protection can be deactivated by driving the signal X_EEPROM1_WC (X1-DE21) to GND. The signal has a 10k pull-up resistor to VDD_IO (default 1.8 V).

I²C User EEPROM (U9)

The phyCORE‑i.MX 95 FPSC is populated with a non-volatile 4 kB I²C EEPROM at U9. This memory is free of use. This device is accessed through I²C port 1 on the i.MX 95. Please see the NXP Semiconductor i.MX 95 Reference Manual for detailed information on the I²C port 1.

The three lower address bits are fixed to 0x1 which means that the EEPROM can be accessed at I²C address 0x50. The EEPROM has a second address on 0x58, which is called Identification Page.

The device is not write proctected per default. Write protection can be established by driving the signal X_EEPROM2_WC (X1-DF20) to VDD_IO (default 1.8 V). The signal has a 10k pull-down resistor.

Serial Interfaces

The phyCORE‑i.MX 95 FPSC provides numerous dedicated serial interfaces, some of which are equipped with a transceiver to enable direct connection to external devices:

1. 1x 4-bit SDIO interface (SD2) with controlled IO voltage for µSD card.
   
2. 1x 4-bit SDIO interface (SD3)
   
3. 3x high-speed UARTs
4. 2x CAN-FD interfaces
5. 1x USB 3.0/2.0 Dual-Role interfaces with PHY
6. 1x USB 2.0 Dual-Role interfaces with PHY
7. 2x 1Gbit Ethernet interfaces with TSN support (ENET2 with Ethernet transceiver on the phyCORE-i.MX 95 FPSC enabling a direct connection to an existing Ethernet network; ENET1 as RGMII Signals at logic-level at the signal pins instead)
8. 5x I²C interfaces
9. 2x Serial Peripheral Interfaces (SPI)
10. 1x SAI audio interface
11. 2x PCI Express with x1 interface
12. 1x MIPI CSI-2 camera interfaces
13. 1x MIPI CSI-2/DSI-2 display interface

Details for each of these serial interfaces and any applicable jumper configurations are below.

SDIO Interface

The SDIO interface can be used to connect external SD cards, eMMC, or any other device requiring an SDIO interface (i.e WiFI, I/O expansion, etc.) The phyCORE bus features one SDIO interface. On the phyCORE‑i.MX 95 FPSC, the interface signals extend from the secon and third Ultra Secured Digital (SD2 and SD3) Host controller to the phyCORE-Connector. 

The tables below show the location of the different interface signals on the phyCORE-Connector. The MMC/SD/SDIO Host Controller is fully compatible with the SD Memory Card Specification 3.0. The interface SD2 supports SD cards with 3.3 V and 1.8 V I/O signals.

SDIO SD2 (4-bit)

SDIO SD2 is a 4-bit wide interface with controlled I/O voltage to support high-speed modes that require 1.8 V I/O voltage. During runtime, the I/O voltage can be switched from 3.3 V (default) to 1.8 V by the processor which controls the PMIC integrated voltage regulator. X_VDDSW_SD2 will be used exclusively to supply an external SD or MicroSD memory card. X_VDDSW_SD2 is monitored by the PMIC for overcurrent and short circuits. For more details, please refer to the PMIC data sheet provided by NXP.

SDIO SD3 (4-bit)

SDIO SD3 is an 4-bit wide interface. The I/O voltage is default 1.8 V (refer to External Logic IO Supply Voltage).

Universal Asynchronous Interfaces (UARTs)

The phyCORE‑i.MX 95 FPSC provides four high-speed universal asynchronous interfaces. The following table shows the location of the signals on the phyCORE-Connector.

CAN Interfaces

The CAN-FD interfaces of the phyCORE‑i.MX 95 FPSC is connected to the FLEXCAN modules (FLEXCAN1/FLEXCAN2) of the i.MX 95 which is a full implementation of the CAN FD protocol specification version 2.0B. It supports a flexible message payload, ranging from 0, 8, 12, 16, 20, 24, 32, 48, and 64 bytes. It supports also standard and extended message frames and programmable bit rates of 2, 5, and 8 Mb/s.

The following table shows the position of the signals on the phyCORE‑Connector.

USB Interfaces

The phyCORE‑i.MX 95 provides one USB 3.0/2.0 and one USB 2.0 dual role interfaces. The USB 3.0 supports super-speed (5Bbit/s) with two sets of Superspeed SerDes lanes with automatic identifaction by type-C assist system. USB 2.0 supports high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) operation. The applicable interface signals can be found on the phyCORE‑Connector X1. If overcurrent and power enable signals are needed for the USB host interface, the functionality can be easily implemented with GPIOs.

Ethernet Interfaces ENET1 and ENET2

The phyCORE‑i.MX 95 FPSC provides two Ethernet Interfaces ENET1 and ENET2 with TSN support. Connection of the phyCORE‑i.MX 95 FPSC to the world wide web or a local area network (LAN) is possible using the on-board GbE PHY at U13. It is connected to the RGMII interface of ENET2. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. Additionally, the RGMII interface of ENET1, which is available on the phyCORE‑Connector, can be used to connect an external PHY. (ENET1 RGMII Interface).

ENET2 Ethernet PHY (U13)

With an Ethernet PHY mounted at U13, the phyCORE‑i.MX 95 FPSC has been designed for use in 10Base-T, 100Base-T, and 1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE‑Connector X1.In Linux environment, ENET2 interface is called eth0 as it is the port with on-board PHY.

Ethernet Signal Locations of ENET2

The on-board GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct-connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface ENET1 of the i.MX 95. Please refer to the NXP Semiconductor i.MX 95 Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (ETH_A±, ETH_B±, ETH_C±, ETH_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals. 

Reset of the Ethernet Controller

The reset input of the Ethernet PHY at U13 is connected to the system reset POR_B.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 95 FPSC is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

ENET1 RGMII Interface

In order to use an external Ethernet PHY, the RGMII interface (ENET1) of the i.MX 95 is brought out at phyCORE‑Connector X1. ENET1 supports TSN network operation. For that use case, an external TSN-ready ethernet switch device is used.In a Linux environment, ENET1 interface is called eth1 as it is the port with external PHY.

10G Ethernet

The phyCORE i.MX 95 provides 10G Ethernet MAC (TSN) with USXGMII Interface to connect an external PHY. Wtih a external connected PHY like AQR113, the interface supports 10/100M and 1G/2G5/5G and 10G Ethernet.

Take care about signal routing to connect the USXGMII SerDes Lanes to an external PHY. PCB-Traces must be route accurate impdance controlled with differential impedance of 85 Ohm (±10%). For AC coupling capacitors connect high quality X7R 100nF capacitors to the RX signals on the basboard side to connect the TX outputs of the PHY device. It is recommended to strictly limit the amout of vias and to use at maximum two vias for each trace with no stubs.

SPI Interface

The Serial Peripheral Interface (SPI) is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI on the phyCORE‑Connector X1. The SPI provides one chip select signal for each interface. The Low Power SPI (LPSPI) of the i.MX 95 has eight separate modules (LPSPI1 to LPSPI8) which support clock rates of up to 60 MHz. The interface signals of three modules (LPSPI3 ,LPSPI4, LPSPI7) are made available on the phyCORE-Connector. These modules are master/slave configurable. The following table lists the SPI signals on the phyCORE-Connector.

I²C / I³C Interface

The Inter-Integrated Circuit (I²C / I³C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 95 contains eight identical and independent Multimaster fast-mode I²C modules and two I³C modules. The interface of 5 modules is available on the phyCORE-Connector X1. I2C2 is reserved for controlling on the SOM and I2C1 supports I³C protocol.

The following table lists the I²C / I³C ports on the phyCORE-Connector:

Audio Interface

 The i.MX 95 supports multiple audio interfaces. One of them is available per default as listed below:

I²S Audio Interface (SAI)

The phyCORE-i.MX 95 FPSC features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97 and TDM. The interface is divided into four sub-interfaces SAI1, SAI2, SAI3, and SAI5. SAI5 is are routed directly to the phyCORE-Connector X1 per default. 

The tables below show the signal locations of the SAI5 interface.

SAI1 Interface

PCI Express Interfaces

The phyCORE‑i.MX 95 FPSC supports two one 1-lane PCI Express interfaces with PCIe Gen. 3.0 functionality which supports up to 8 GT/s operations. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented with GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. Libra Development Board) for a circuit example.

The position of the PCIe signals on the phyCORE‑Connector X1 is shown below:

General Purpose I/Os

All pins not used by any of the other interfaces specifically described in this manual and can be used as GPIO without harming other features of the phyCORE‑i.MX 95 FPSC. These pins are shown below:

Besides these pins, most of the i.MX 95 signals which are connected directly to the module connector can be configured to act as GPIOs, due to the multiplexing functionality of most controller pins. Normally, pins with signal type I/O are able to work as a GPIO.

Debug Interface

The phyCORE‑i.MX 95 FPSC is equipped with a JTAG interface to download program code into the external flash, internal controller RAM, or any debugging programs being executed. The location of the JTAG pins on the phyCORE-Connector X1 are below:

UART Debug

The default debug UART Interfaces is FPSC UART3 (i.MX 95 LPUART7) for Cortex-A55 Cores and FPSC UART2 (i.MX 95 LPUART5) for Cortex-M7 Core. FPSC UART3 is accessible on connector X1 pins AB15 (RXD) and AC14 (TXD) and FPSC UART2 on pins DA6 (RXD) and DA7 (TXD).

For more information also refer to Universal Asynchronous Interfaces (UARTs).

Display Interfaces

Low Voltage Differential Signal Display Interface (LVDS)

The phyCORE-i.MX 95 FPSC offers one LVDS display interface which supports two output channels.

The locations of the LVDS signals are shown below:

Camera Connections

The phyCORE-i.MX 95 FPSC offers 2 MIPI-CSI interfaces to connect digital cameras. The two MIPI/CSI‑2 camera interfaces of the i.MX 95 extends to the phyCORE‑Connector X1 with 4 data lanes and one clock lane.

The locations of the MIPI-CSI signals are shown below:

ADC Inputs

The phyCORE i.MX 95 FPSC provides an 16 channel 12-Bit SAR ADC with 8 single ended inputs. The second 8 channel are muxed interally in the CPU.

FPSC Reserved Target specific Proprietary Signals

The following signals are not defined according to FPSC Specification Featureset 24A.0 (LAN-118e.Ax). These signals are processor-specific and should only be used in application if no direct compatibility between different SOMs is required.

RTC

The phyCORE i.MX 95 has an on-board, externally mounted RTC. The RV-3028-C7 is the newest generation of RTC from Micro Crystal with an extremely low backup current of typically 40nA at 25 degrees. PHYTEC uses the most optimal implementation in each phyCORE design to give the most optimal usage for all customers.

The RTC is accessible over I2C1 on Address 0x52. In a normal operation state, the RTC power is supplied from the SOM voltage VDD_3V3. If the SOM is not powered and RTC backup is needed, the VBACKUP Pin of the RTC can be supplied over the X_RTC_VBACKUP pin X1-AC7.

The RTC provides an interrupt output signal (X_RTC_INT) which is fed to the module connector X1-AC5. This signal is an open drain (OD). The on-board pull-up resistor is, by default, not mounted. To use the X_RTC_INT signal, add an external pull-up resistor (e.g. 10k) to an appropriate I/O voltage level (e.g. X_RTC_VBACKUP).

Furthermore, the RTC is able to supply a programmable clock output signal (push-pull) RTC_CLKOUT. Frequencies of 1/32/64/1024/8192 Hz and 32.768 Hz (default) are programmable. The RTC_CLKOUT signal is fed to the module connector at X1-AC6. For a detailed description of the programming capabilities of the RTC, refer to the Micro Crystal RV-3028-C7 App-Manual.

The RTC supports an external event input signal (X_RTC_EVI at X1-DD20), which can be used e.g. interrupt genration or timestamp function. A 100k pull-down resistor is connected to this signal. For a detailed description of the programming capabilities of the RTC, refer to the Micro Crystal RV-3028-C7 App-Manual.

Temperature Sensors

The phyCORE-i.MX 95 FPSC supports two internally sensored thermal zones in the i.MX 95 CPU as well as 4 externally sensored thermal zones for monitoring board-level temperatures. The presence of the sensors depends on the delivery variant of the module.

The external temperature sensors are located at the following positions.

The TMP102 temperature sensor devices used are connected to I2C1 bus. TMP102 measures temperatures from -40 °C to +125 °C. For a more detailed description of TMP102, refer to the Texas Instruments TMP102 Datasheet.

CPU Core Frequency Scaling

The phyCORE-i.MX 95 FPSC is able to scale the clock frequency and voltage. This is used to save power and reduce heat dissipation when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as 'Dynamic Voltage and Frequency Scaling' (DVFS).

The phyCORE-i.MX 95 FPSC BSP supports the DVFS feature. The Linux kernel provides a DVFS framework that allows each CPU core to have a min/max frequency as well as the applicable voltage and a governor that governs these values depending on the system load. Depending on the i.MX 95 variant used, several different frequencies are supported. Further details on how to configure this governor can be found in the phyCORE-i.MX 95 BSP Manual.

Technical Specifications

Additional specifications:

These specifications describe the standard configuration of the phyCORE‑i.MX 95 FPSC as of the printing of this manual.

phyCORE-i.MX 95 FPSC Power Consumption

The values listed in the table below are a guideline to determine the required dimensions of the power supply circuitry on a carrier board. They do not take application-specific load situations into account. These values have been generated by looking at the maximum power consumption measured using different load scenarios and adding a voltage source of 5.0 V.  These values are based on internal PHYTEC testing. Customers need to consider their application power requirements to ensure they do not generate a load greater than the values listed here. 

For power measurement, a SOM (PCL-078) with 8 GB RAM, 32GB eMMC, ETH0, and an PIMX9596AVZXNAB was used together with PDx.x.x. 

Additionally, there are some values that cannot be tested. Situations such as suspending to RAM, suspend freeze, and standby mode must be tested on a case-by-case basis to ensure the application's power consumption stays within the guideline stated above.

Product Temperature Grades

The feasible operating temperature of the SOM highly depends on the use case of your software application. Modern high-performance microcontrollers and other active parts such as the ones described within this manual are usually rated by qualifications based on tolerable junction or case temperatures. Therefore, making a general statement about minimum or maximum ambient temperature ratings for the described SOM is not possible.

However, the above-mentioned parts are available at different temperature qualification levels by the producers. We offer our SOMs in different configurations, making use of those temperature qualifications. To indicate which level of temperature qualification is used for active and passive parts of a SOM configuration, we have categorized our SOMs into three temperature grades.

The table below describes these grades in detail. This table describes a set of components that, in combination, add up to a useful set of product options with different temperature grades. This enables us to make use of cost optimizations depending on the required temperature range.

In order to determine the right temperature grade and whether the minimum or maximum qualification levels are met within an application, the following conditions must be defined by considering the use case:

• Determined the processing load for the given software use case
• Maximum temperature ranges of components (table below)
• Power consumption resulting from a baseload and the calculating power required (in consideration of peak loads as well as time periods for system cooldown)
• Surrounding temperatures and existing airflow in case the system is mounted into a housing
• Heat resistance of the heat dissipation paths within the system along with the considered usage of a heat spreader or a heat sink to optimize heat dissipation

FPSC Footprint on the phyCORE-i.MX 8M Plus FPSC

For information on the footprint, mating baseboard footprint, numbering schema, etc. please refer to the corresponding FPSC Gamma Feature Set Specifications (LAN-118e.A0)

Pin numbering schema:

https://www.phytec.de/cdocuments/?doc=owEwO#FPSCGammaFeatureSetSpecificationsLAN118e-A0-PinNumbering

Mating FPSC Baseboard Footprint;

https://www.phytec.de/cdocuments/?doc=owEwO#FPSCGammaFeatureSetSpecificationsLAN118e-A0-Baseboard

Interface Signal Trace Length Table

PHYTEC recommends a control delay and trace length of the high-speed interface signals. Signal delay and trace length of the high-speed interface signals routed on the for of the phyCORE‑i.MX 95 FPSC are listed in the following table. Take these values into consideration for the calculation of the overall delay and trace length budgets.

Hints for Integrating and Handling the phyCORE‑i.MX 95 FPSC

Integrating the phyCORE-i.MX 95 FPSC

Besides this hardware manual, more information is available to facilitate the integration of the phyCORE‑i.MX 95 FPSC into customer applications.

1. The design of the Libra Development Board can be used as a reference for any customer application.
2. Many answers to common questions can be found at: https://www.phytec.de/produkte/system-on-modules/phycore-imx-95-fpsc/#downloads/
3. The link “Carrier Board” within the category Dimensional Drawing leads to the layout data phyCORE-i.MX 95 FPSC Footprint. It is available in different file formats. The use of this data allows the user to integrate the phyCORE-i.MX 95 FPSC SOM as a single component into their design.
4. Different support packages are available for support in all stages of embedded development. Please visit https://www.phytec.de/support/support-pakete/ or https://www.phytec.eu/support/support-packages/ or contact our sales team for more details.

Handling the phyCORE-i.MX 95 FPSC

phyCORE Module Modifications

The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station, or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Integrating the phyCORE into a Target Application

Successful integration in user target circuitry greatly depends on adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. At a minimum, all GND pin neighboring signals which are being used in the application circuitry should be connected to GND.

Ordering Information

The part numbering of the phyCORE PCM-070 has the following structure:

Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
https://www.phytec.de/produkte/system-on-modules/phycore-imx-95-fpsc/
or
https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-95-fpsc/

phyCORE-i.MX 95 FPSC on the Libra Development Board

Hardware Overview

The Libra Development Board for phyCORE-i.MX 95 FPSC is a low-cost, feature-rich software development platform supporting the NXP Semiconductors i.MX 95 microcontroller. Due to numerous standard interfaces, the Libra Development Board i.MX 95 can serve as the bedrock for any application. At the core of the Libra Development Board is the PCL-079/phyCORE-i.MX 95 FPSC System On Module (SOM) containing the processor, LPDDR5 RAM, eMMC Flash, power regulation, supervision, transceivers, and other core functions required to support the i.MX 95 processor. Surrounding the SOM is the PCM-937-L/Libra Development Board carrier board, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals.

Libra Development Board Concept

PHYTEC phyCORE carrier boards are fully equipped with all mechanical and electrical components necessary for a fast, secure start-up. Subsequent communication to and programming of applicable PHYTEC System on Modules (SOM) is made easy. phyCORE carrier boards are designed for evaluation, testing, and prototyping of PHYTEC System on Modules in laboratory environments prior to their use in customer-designed applications.

This modular development platform concept includes the following components:

• The phyCORE-i.MX 95 FPSC Module populated with the i.MX 95 microcontroller and all applicable SOM circuitry such as LPDDR5 SDRAM, eMMC-Flash, Ethernet-PHY, PMIC, etc.
• The Libra Development Board Carrier Board offers all essential components and connectors for a start-up including a power supply for 24 V input voltage and interface connectors such as HDMI, USB, and Ethernet, which enable the use of the SOM’s interfaces with a standard cable.

The carrier board can also serve as a reference design for developing custom target hardware in which the phyCORE SOM can be deployed. Carrier board schematics are available under a Non-Disclosure Agreement (NDA). The reuse of carrier board circuitry enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

SBCplus Concept

The SBCplus concept was developed to meet the many, small differences in customer requirements with little development effort. This greatly reduces the time-to-market. The core of the SBCplus concept is the SBC design library (a kind of construction set) that consists of a large number of function blocks (so-called "building blocks") that are continuously being refined and updated.

Recombining these function blocks allows PHYTEC to develop a customer-specific SBC within a short time. We are able to deliver production-ready custom Single Board Computers within a few weeks at very low costs. The already developed SBCs, such as the Libra Development Board, each represent a combination of different customer wishes. This means all necessary interfaces are already available on the standard versions, allowing PHYTEC SBCs to be integrated into a large number of applications without modification.

For any necessary detail adjustment, extension connectors are available which enable a wide variety of functions to be added.

Libra Development Board Features

The Libra Development Board supports the following features:

[1]

• Developed under PHYTEC's FPSC concept
• Populated with PHYTEC’s phyCORE FPSC SoM (see phyCORE SoM Feature List)
• Dimensions of 230 mm × 140 mm
• Boot from eMMC, SD Card, or over USB with the Serial Downloader
• 24 V input voltage
• USB-C input power
• 32 MByte NOR (at Kit Version)
• 4 kByte EEPROM
• 2x RJ45 jack for 10/100/1000 Mbps Ethernet
• 1x RJ45 jack for 10/100/1000/2500/5000/10000 Mbps Ethernet

• 1x USB-Host interface made available through a USB 3.0 4-port HUB at:

  • USB 3.0 Type-A connector (Actual USB speed depends on mounted SoM)

  • Mini PCI express connector (USB 2.0)

  • Audio/Video connector (USB 2.0)

  • Expansion Connector (USB 2.0)^[2]

• 1x USB-C 3.2 interface connected to phyCORE FPSC SoM
• 1x Secure Digital / MultiMedia Memory Card interface brought out to a Micro SD-Card receptacle
• 1x HDMI interface brought out to a standard Type-A connector (HDMI availability depends on mounted SoM)
• 1x MIPI-DSI brought out to be used with PEB-AV-12 (MIPI-DSI availability depends on mounted SoM)
• 2x MIPI-CSI-2 camera interfaces brought out as a phyCAM-M interface
• 1x PCIe interface brought out to a Mini PCI Express connector
• 1x PCIe interface brought out to an M.2 Key-M connector
• RS-232 or RS-485 available at 2x5 pin header 2.54 mm RS-232 (up to Mbps) including a handshake and RS-485 Half-Duplex (up to Mbps)
• Up to 16 ADC input pins (Number of useable ADC input signals depends on mounted SoM)
• Reset button
• ON/OFF button
• One multicolor LED
• SAI Audio brought out via an A/V connector
• Digital I/O via an Expansion Connector
• JTAG via an Evaluation Adapter connected to the Expansion Connector and separate 2x10 pin header 2.54 mm
• Expansion connector for various interfaces
  • JTAG 
  • I²C
  • SPI
  • UART
  • SDIO
• Goldcap backup supply for SoM RTC
• on-board measurement of SOM Power Consumption
• All processor interfaces available on-board (may be limited by predefined muxing)

Block Diagram

SoM Feature List on the Libra Development Board

There are several SoMs that can be used with the Libra Development Board. Below is a comprehensive list of features that each SoM contains and can be used with the Libra Development Board. For more information, please contact your PHYTEC representative (Contact Information).

Temperature Range

Most components on the Libra Development Board have an operating temperature range of -40 °C to 85 °C. The following components are the exception:

For this reason, the operation temperature range for the kit variant is: -25 °C to 70 °C. The storage temperature range is -40 °C to 85 °C.

Mechanical Dimensions

For detailed dimensions, refer to the provided CAD data (e.g. DXF file) in the download section of our specific FPSC SoMs:

• phyCORE-i.MX 95 FPSC
• phyCORE-i.MX 8M Plus FPSC
• phyCORE-AM62Lx FPSC
• phyCORE-AM62P FPSC (COMING SOON)

Libra Development Board Components

Libra Development Board Component Placement Diagram

Libra Development Board Component Overview

The Libra Development Board features many interfaces and is equipped with the components listed in the table Connectors and Pin Header. For a more detailed description of each component, refer to the appropriate section listed in the table below. Libra Development Board Components (Top) and Libra Development Board Components (Bottom) highlight the location of each component for easy identification.

Connectors and Pin Header

The table below lists all available connectors on the Libra Development Board.

LEDs

The Libra Development Board is populated with 7 LEDs. Libra Development Board Components (Top) and Libra Development Board Components (Bottom) show the location of the LEDs. Their functions are listed in the table below:

Switches and Buttons

The Libra Development Board is populated with multiple switches and buttons. The table below shows their functions:

Jumpers

The Libra Development Board comes pre-configured with several removable jumpers (JP) and solder jumpers (J). These jumpers enable the flexible configuration of a limited number of features for development purposes.

The function of the removable jumper on the Libra Development Board is shown below. More detailed information can be found in the appropriate section. 

Libra Development Board SBC Component Detail

This section provides a more detailed look at the Libra Development Board components. Each subsection details a particular connector/interface and associated jumpers for configuring that interface.

phyCORE Connector (X1)

Power Supply (X2/X8)

The Libra Development Board can be powered either by a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector (X8) or by a USB Power Delivery Supply (X2).

The Libra Development Board is available with one power supply connector, a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector (X8) suitable for a single 24 V supply voltage. The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE mounted on the Libra Development Board, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board.

The permissible input voltage is 24 V DC if your SBC is equipped with a 2-pole Phoenix Contact MINI COMBICON base strip. A 24 V power supply capable of providing at least (TBD A) is recommended to power the board via the 2-pole base strip. The pin assignment for power supply connector X2: 

USB Power Delivery Connector (X8)

The Libra Development Board can be powered by a USB Power Delivery Supply. The Libra Development Board provides the needed voltage and current with the connected supply and enables the on-board voltages. A 100 W USB-PD supply is recommended to power the Libra Development Board.

RTC Backup Supply

The Libra Development Board has a double-layer capacitor equipped to back up the VDD_RTC rail of the phyCORE FPSC SoM. The mounted 330 mF capacitor is capable of backing up the SoM RTC for at least (TBD) at 25 °C. 

UART

The Libra Development Board features 3 UART interfaces. This paragraph describes their default and alternative purposes.

UART1 (full flow control) is configurable to provide one of three functions via 2 integrated (U38/U40) and one hardware switch S5. The following table explains the necessary settings for a desired UART1 target:

UART2 (full flow control) is connected to the USB debug channel 2 via the default setting of JP1. UART3 is connected to the USB debug channel 1 via the default setting of JP1.

UART Design Consideration

When designing a custom carrier board, remember the TTL level is 1.8 V.

RS-232/RS-485 (X27)

Pin header connector X27 provides the UART1 signals of the phyCORE FPSC SoM at either RS-232 or RS-485 level. Mode is selected by routing UART1 to the applicable converter. Please refer to PLACE LINK TO UART1 TARGET SELECTION. The RS-232 interface is intended to be used as data terminal equipment (DTE) and allows for a 5-wire connection, including the signals RTS and CTS for hardware flow control. RS-485 is available in Half-Duplex (3-wire). The table below shows the signal mapping of the RS-232 and RS-485 level signals at connector X27. 

CAN FD (X29/X31)

The phyCORE FPSC SoM FLEXCAN1 and FLEXCAN2 interfaces are brought out at X29 and X31, each as CAN FD. The maximum permissible CAN FD data rate is 8 Mbit/s. For development purposes, a 120 Ω termination can be added by closing SW5 (CAN1) or SW6 (CAN2). For standard use, it is possible to mount a more suitable split termination in a customer-specific BOM.

The pinout is chosen to fit the official standard CAN pinout and is displayed in the table below. on a DE-9 plug (D-Sub 9 pin), where CAN_L is pin 2, CAN_H is pin 7, GND is pin 3 and VCC_5V is pin 9.

Ethernet (X21/X22/X25)

The Libra Development Board is equipped with 3 RJ45 connectors. The table below describes the properties of each Ethernet interface:

The LEDs for LINK (green) and ACTIVITY (orange) indications are integrated into the connector. The Ethernet transceivers support Auto MDI-X, eliminating the need for a direct connect LAN or cross-over path cable. They detect the TX and RX pins of the connected device and automatically configure the PHY TX and RX pins accordingly.

Ethernet Design Consideration

The data lanes should be routed with a differential impedance of 100 Ohm. The center taps of each pair's transformer have to be connected to GND through a 100nF capacitor. The LED pins are open-drain outputs of the SoM without a resistor, so they should be connected to the cathodes of the LEDs through a resistor.

USB Type-A 3.0 Interface (X16)

 The Libra Development Board provides a USB 3.0 interface at the USB Type-A connector X16. It is a Host interface made available through a 4-port USB HUB.

USB-C 3.2 GEN 1 Interface (X18)

The Libra Development Board provides a USB-C 3.2 GEN 1(10 Gbps) interface. The USB Serial Downloader requires this interface to be able to boot from USB. The lower socket is connected via a USB 3.2 Gen 1 hub to USB2 of the phyCORE FPSC SoM.

USB 3.2 Gen1 Design Considerations

Series capacitors are already present on the phyCORE FPSC SoM. It is not necessary to provide additional series capacitors in the TX lines. Double-check the signal direction of the high-speed lines where TX is output and RX is input on phyCORE FPSC SoM. The TX and RX lines should be routed with an impedance of 50 Ohms to a ground plane and 100 Ohms differential impedance. Route USB D lines with 45 Ohms to Ground and 90 Ohms differential impedance.

USB Debug (X14)

The primary debug interface is UART3. UART4 is the debug interface for the M7 core. Both UART interfaces are connected to a UART-to-USB Converter (U15 FTDI FT4232H). The USB interface is brought out at a USB-C socket (X14). Use the following terminal settings to connect to Libra Development Board serial interfaces:

• Speed: 115200 baud
• Data bits: 8
• Stop bits: 1
• Parity: None
• Flow control: None

The USB debug interface is also capable of manipulating the Boot Mode signals through FT4232H bank D and triggering a reset through FT4232H bank C.

The table below shows the pinout of the USB Debug connector:

Secure Digital Memory Card / MultiMedia Card (X60)

The Libra Development Board provides a standard microSDHC card slot at X60 for use with SD/MMC interface cards. It allows for a fast, easy connection to peripheral devices like microSD and MMC cards. Power to the SD interface is supplied by inserting the appropriate card into the SD/MMC connector. It also features card detection, a lock mechanism, and a smooth extraction function by pushing the card in and out.

SD / MM Card Design Considerations

Series resistors might be required to adapt the drive strength of the card. SD interface should be routed with an impedance of 50 Ohms to a ground plane. The trace length between CLK, CMD, and DATA lanes should be matched and kept as short as possible. Avoid Vias and take care of the signal current return path.

Mini PCIe (X52)

The 1-lane PCI express interface provides PCIe Gen. 3.0 functionality, which supports up to 8 GT/s operations. Various control signals are implemented with GPIOs. The PCIE1 interface is brought out at the Mini PCIe connector X52 shown above. PCIe clock is generated by the dedicated PCIe clock generator U51.

The table below shows in-depth information, such as pin assignment and signals used to implement special features of the Mini PCIe interface.

PCIe Design Considerations

100nF AC coupling capacitors are placed at the output of the phyCORE FPSC SoM in series to the TX lanes. A clock generator on the carrier board generates the PCIe clock.

M.2 Key-M (X54)

The second 1-lane PCI express interface provides PCIe Gen. 3.0 functionality, which supports up to 8 GT/s operations. The mounted M.2 Key-M connector is mainly used for SSD cards. Various control signals are implemented with GPIOs. The PCIE2 interface is brought out at the M.2 Key-M connector X54 shown above. PCIe clock is generated by the dedicated PCIe clock generator U51. The M.2 Key-M connector is only available with the FPSC SoM PCL-079

The table below shows in-depth information such as pin assignment and signals used to implement special features of the M.2 Key-M interface.

Camera Connectivity

phyCAM-M MIPI CSI Camera Connectors (X32/34)

The phyCORE FPSC SoM on the Libra Development Board offers 2 independent interfaces to connect digital camera boards with the MIPI CSI-2 interface. The 4-lane MIPI CSI-2 interfaces are brought out as phyCAM-M camera interfaces at connectors X32 and X34. The pin assignments of connectors X32 and X34 are shown below. The phyCAM-M camera connectors fit the phyCAM-M product family with different colors and monochrome sensors. Suitable camera modules are e.g. VM-016-COL-M (1 MPix) or VM-017-BW-M (5 Mpix) which can be delivered with a complete objective. Contact the PHYTEC Sales Team for advice on how to tailor a camera module to your application.

The suitable cable can be found in the table below.

Camera Design Considerations

Regarding camera connections when designing a customer carrier board:

1. The differential impedance should be 100 Ohm for all lanes to a Ground Plane. The lanes should be matched.
2. phyCAM-M interfaces offer 3.3 V or 5 V supply voltages (selected by interface pin 26). Both voltages should be provided by the board to guarantee full compatibility with the phyCAM-M interface.
   
3. Each phyCAM interface needs a different I²C address if connected to the same I²C Bus. Place a Pull-up resistor at pin 24 to select the secondary address.
   

General information and design guidelines for PHYTEC camera interfaces can be found here:

• German:  L-867Bd.A9 phyCAM Basis-Spezifikation und Design-In Guide
• English:  L-867Be.A9 phyCAM Basis Specification and Design-In Guide

Specific information for each PHYTEC camera module can be found on that module's download page: PHYTEC Embedded Vision (Deutsch) or PHYTEC Embedded Vision (English).

HDMI (X37)

The Libra Development Board provides a High-Definition Multimedia Interface (HDMI) which is compliant with HDMI 2.0a. It supports a maximum resolution of 1920x1080p60, 1280x720p60, 720x480p60, and 640x480p60. Please refer to the applicable phyCORE FPSC SoM Applications Processor Reference Manual for more information. This feature is not available for all mountable FPSC SoMs.

The HDMI interface is brought out at a standard HDMI type A connector (X20) on the Libra Development Board and is comprised of the following signal groups:

• Three pairs of data signals
• One pair of clock signals
• The Display Data Channel (DDC)
• The Consumer Electronics Control (CEC)
• The Hot Plug Detect (HPD) signal
• Audio Return Channel (ARC)

All signals are routed from the phyCORE‑Connector to the HDMI receptacle through ESD Protection Diodes. 

HDMI Design Considerations

The differential impedance should be 100 Ohm for all lanes to a Ground Plane. The lanes should be matched. The DDC lanes need pull-up resistors between 1.5k and 2k to 5V through a diode. The CEC lane needs a 27k pull-up resistor connected to 3.3 V through a diode. This prevents leaking current in a power-off state.

Audio/Video (SAI2/LVDS0)

The phyCORE FPSC SoM offers one LVDS display interface that supports two output channels. The Audio/Video (A/V) connectors X46 and X50 provide an easy way to add typical A/V functions and features to the Libra Development Board. Standard interfaces such as 4-lane LVDS, I2S, I2C, and USB, as well as different supply voltages, are available at the two A/V female dual-entry connectors.  A special feature of these connectors is their connectivity from the top or bottom. The A/V connector is intended to be used with phyBOARD Expansion Boards and to add specific audio/video connectivity with custom expansion boards. A/V connector X46 makes all signals for display connectivity available, while X50 provides signals for audio and touchscreen connectivity as well as an I2C bus and additional control signals. The tables below show the pin assignment of connectors X46 and X50. 

Audio/Video Design Considerations

The differential impedance of LVDS2 lanes should be 100 Ohm and 50 Ohm to a Ground-Plane for all lanes. Lanes should be matched. The audio signals should have a single-ended impedance of 50 Ohm to a ground plane.

LVDS1 (X43/X44)

The phyCORE FPSC SoM offers one LVDS display interface that supports two output channels. The video connectors X43 and X44 provide an easy way to connect a display to the Libra Development Board. The pinout of both connectors fits the Glyn LVDS Display Family with different display sizes and display resolutions. In addition to the Glyn LVDS signals, there are USB and I²C for touch brought out at X34 as well. The connectors are intended to be used with PHYTEC KLCD-AC163. The tables below show the pin assignment of connectors X43 and X44. 

LVDS Design Considerations

The differential impedance of LVDS0 lanes should be 100 Ohm and 50 Ohm to a Ground-Plane for all lanes. The lanes should be matched.

MIPI-DSI (X39)

The phyCORE-i.MX 8M Plus FPSC offers one MIPI-DSI display interface (not available on phyCORE-i.MX 95 FPSC). MIPI-DSI has 4 channels, supporting one display with a resolution of up to 1920 x 1080 at 60Hz. The following table shows the pin assignment of connector X39 (Hirose DF12(4.0)-36DP-0.5V(86)).

MIPI-DSI Design Considerations

The differential impedance of MIPI-DSI1 lanes should be 100 Ohm and 50 Ohm to a ground plane for all lanes. The lanes should be matched.

Expansion Connector (X56)

The expansion connector X56 provides an easy way to add other functions and features to the Libra Development Board. Standard interfaces such as SPI, USB, JTAG, UART, SDIO, and I2C are available at the expansion connector. The expansion connector is intended to be used with a phyBOARD Evaluation Adapter. The expansion connector can also add specific functions with custom expansion boards. Information on the Evaluation Adapter for the expansion connector can be found in the Application Guide for phyBOARD Expansion Boards (phyBOARD-Wega Expansion Guide (L-793_0)).

The pinout of the expansion connector is shown in the table below:

Fan (X68)

If heatsinking is required for the phyCORE FPSC SoM, a PWM-controlled fan can be connected to the Libra Development Board. The fan's supply voltage is 5 V, and the PWM signal is brought out as open drain. The frequency generator signal, which can be used to monitor fan rotation, is connected to test pad TP55 and comes with a pull-up resistor to 3.3 V.

A Hirose DF13-4P-1.25V (75) socket is used as a connector with the following pinout:

JTAG (X10)

If heatsinking is required for the phyCORE FPSC SoM, a PWM-controlled fan can be connected to the Libra Development Board. The fan's supply voltage is 5 V, and the PWM signal is brought out as open drain. The frequency generator signal, which can be used to monitor fan rotation, is connected to test pad TP55 and comes with a pull-up resistor to 3.3 V.

A Hirose DF13-4P-1.25V (75) socket is used as a connector with the following pinout:

On-board Functionalities

Multicolor (RGB) LED (D31)

The Libra Development Board provides one multicolor (RGB) LED (D31). The LED is connected to an LED driver (NXP PCA9533/01) controlled by the I2C3 bus. The location for D31 can be found in LEDs.

EEPROM (U57)

The Libra Development Board provides a 2 kbit EEPROM (ST M24C02-RMC6TG) for general use. It is controlled by the I2C2 bus. The EEPROMs write protection pin is connected to TP60. Write protection can be enabled by mounting an R333 pull-up resistor. In this case, the EEPROM can be written if TP60 is tied to Ground only. The EEPROM I²C address can be fully customized by jumpers J21, 22, and 23. The default address is 0x51.

Quad SPI NOR (U62)

The Libra Development Board features a 512MBit Quad SPI NOR at U62.

ADC (X73) 

TBD

SPI ADC (X71) 

TBD

Temperature sensor (U56)

The Libra Development Board is equipped with a P3T1750DPZ I3C temperature sensor. 

Peripheral current measurement (U5/U7/U9)

TBD

Global Board Reset (X_nRESET_OUT)

The X_nRESET_OUT signal (X_POR_B at phyCORE FPSC SoM) is used to hold all devices with an external reset pin in the reset state. X_nRESET_OUT will be released after all board voltages are powered up and allows the phyCORE FPSC SoM to boot. X_nRESET_OUT is brought out at several connectors like the Expansion Connector (X56).

X_nRESET_OUT Design Considerations

Note that there is a 10 kOhms pull-up resistor phyCORE FPSC SoM VDD_IO voltage. It is recommended to use this signal as an open drain.

On-board Power Supplies

The Libra Development Board provides supply voltages on several connectors to power external devices. Be sure not to exceed the maximum permissible current that can be drawn from each power domain. In the table below, each source is listed with the location where a voltage connected to the source can be found:

In addition to these currents, Libra Development Board delivers current for USB_VBUS of X16/X18 (2x 900 mA), phyCAM-M Interfaces (2x 1500 mA 3.3 V or 5 V depending on VCC_SELECT pin), HDMI connector (150 mA).

On-board Measurement of SoM Power Consumption

The input current of the SoM supply rail VDD_SOM can be measured on board to determine the power consumption of the SOM. A current sense amplifier translates the supply current into a proportional voltage VOUT_CC_SOM, which can be measured at  X12 (on PCB top side) and X12 (on PCB bottom side). The mounted amplifier features a gain of 100V/V. The SoM input current I_{SOM_IN} in Ampere is determined by inserting VOUT_CC_SOM into the following equation.

Subsequently, the SoM input power may be derived from I_{SOM_IN} and VOUT_CC_SOM using the following formula: 

For example, measuring 400 mV at X12, the input current will be 1 A.  With a SoM input voltage of 5.0 V the input P_{SOM_IN} is 5 W.

Switches

The Libra Development Board has several switches and buttons for various uses. The locations for all switches can be found in Switches and Buttons.

System Reset Button (S2)

The Libra Development Board is equipped with a system reset button at S2. Pressing this button will assert reset through a voltage supervisor U11 that will pull the X_nRESET_IN pin (X1 Pin Y21) of the phyCORE FPSC SoM low, causing the module to reset with a complete power cycle.

System ON/OFF Button (S3)

The Libra Development Board is equipped with an ON/OFF button at S3 and is connected to X_ONOFF of the phyCORE FPSC SoM. For more information, refer to the applicable CPU's Reference Manual.

Boot Switch (S1)

The Libra Development Board features a boot switch with four individually switchable ports to select the phyCORE FPSC SoM default bootsource. The Boot_Mode signals may also be accessed through pin header X9. Descriptions of the various boot modes can be found in Boot Mode Selection. The available boot options differ depending on the mounted FPSC SoM. All available options are displayed in the table below:

Boot Mode Design Considerations

Bootpin voltages should be valid when X_POR_B (X_nRESET_IN at Libra Development Board) is released.

Additional System-Level Hardware Information

I2C Connectivity

The I2C1 interface of the phyCORE FPSC SoM is not connected to the Libra Development Board. The table below lists the connectors and pins with I2C connectivity and on-board devices. The I²C addresses are hexadecimal in 7-bit representation of the default Linux representation.

To avoid conflicts when connecting external I2C devices to the Libra Development Board, the addresses of the onboard I2C devices must be considered. The table below lists the addresses already in use; the default address is printed in bold. The I²C addresses are hexadecimal in 7-bit representation which is the default Linux representation.

Revision History

Contact Information

If you have any questions, design considerations, or are interested in further information, please contact your nearest PHYTEC office.

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