phyCORE-LPC3180

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Visit NXP LPC3180 Product Summary Page to find data sheets, manuals, erratas, application notes, etc...

FAQ

phyCORE-LPC3180

phyCORE-LPC3180: Dimensions

Question:

 I need to plug the LPC3180 module to our PCB board and would require more detail information of the connector and its dimensions.

Answer:

Figure 13 in the phyCORE-LPC3180 Hardware Manual http://www.phytec.com/pdf/manuals/L-681e.pdf should give you all the dimensions for the Molex connector. It is important to use the 4 mounting holes as the reference for any additional dimensions. The SBC module edges are not that accurate due to the PCB panelization we use and cutting the panels into individual units comes with fairly big tolerances.

 

phyCORE-LPC3180: Serial Communication Example

Question:

I need examples of how to use serial communication for the LPC3180.

Answer:

We currently don't have any examples for that but we have examples for IAR. Here's the basic procedure for getting UART5 to work in polling mode (see LPC3180 manual from NXP for register descriptions):

    • Set the DLAB bit to "1" in the U5LCR register
    • Write to the U5DLM & U5DLL registers to set the baud rate.. this is calculated from either HCLK or PERIPH_CLK.. best bet is to set the registers (see later steps) to use HCLK as the clock source...if using Keil & have used config wizard to init clocks, then look to this for HCLK value...probably going to be set to 104MHz if maximum operation frequency is set.
    • Set the DLAB bit in the U5LCR register to "0"
    • Write to the U5CLK register to set the X & Y values (see baud rate calculations in manual)
    • Set the CLK_SEL bit to "1" in the U5CLK register... this will select HCLK as the clock source for uart baud generation
    • Set the UART5_CLK bit to "1" in the UART_CLKMODE register to enable the
      UART5 clock domain
    • Set the WLS bits in the U5LCR register to 0x3 for 8 bits, no parity, 1 stop bit
    • Set the FCTRL bit in the U5FCR register to "1" for proper fifo operation
    • Set the TFR bit to "1" in the U5FCR register to reset the TX fifo
    • Set the RFR bit to "1" in the U5FCR register to reset the RX fifo
    • Set the FCRFE bit to "1" in the U5FCR register to enable the TX/RX fifos

 

To send a byte:
1) write 8 bits of data to the U5THR register
2) poll the TEMT bit in the U5LSR register to wait until the byte is transmitted

 

To receive a byte:
1) poll the DR bit in the U5LSR register...as long as it is 0 no data has been received in the receive buffer
2) read the data out of the U5RBR register after the DR bit in U5LSR has been set

to read and write the registers just map a variable equal to the register width to the memory location of the register like so:

The U5LSR register is located at 0x40080014 (per the lpc3180 manual) and is a an 8 bit register:

 

#define U5LSR (*(volatile unsigned char*)0x40080014)

void main(void)
{
....
U5LSR = 0x6; // access example
}

The Keil 3180 header file should have all of these register defined. Look to this instead of defining each register manually.

 

phyCORE-LPC3180: Interrupt driven UART

Question:

 I'd like to transmit data using interrupts. Once the output buffer is filled in I'm enabling THRE interrupts in UxIER register and I'm expecting the interrupt to show up immediately to fetch the first character from a buffer. Unfortunately, I don't see this happening. The interrupt is not generated as expected. If I just write one byte to UxTHR (from debugger for example) then, after that bytes go out, I see an interrupt. Why isn’t the interrupt generated when it’s just enabled? The interrupt controller is configured to act on level high.

Answer:

We do not have any interrupt driven UART examples, unfortunately. I assume the reason the UART does not trigger an interrupt even though the buffer is empty when the THRE interrupt is enabled is because it is already empty and has not come to the state of empty due to transmitting characters previously in the buffer. If it triggered on the act of being empty then it would continually keep triggering until something was put in it instead of triggering only when becoming empty. This would of course lead to a stack overflow very quickly as the UART kept interrupting itself. Therefore, enabling the interrupt doesn't create the same edge that the UART circuitry will create when the buffer becomes empty, hence no interrupt.

 

phyCORE-3180: Is the generic USB device supported as well as the Ethernet adapter in the Linux BSP?

The SMC2209ETH/USB is supported. I am unsure what other devices are supported in the BSP. This was given to us by NXP “as-is”. I imagine various generic devices are supported. I know mass storage drives are supported.

phyCORE-LPC3180: Is there any reason that two USB devices couldn’t be used at the same time, either from a software of hardware perspective?

I don’t see any reason that this is a limitation as long as you have a HUB. There is only one USB port on the LPC3180 despite the appearance of 3connetors on our Carrier Board. All of these connectors go to the exact same interface. Since the USB interface is an OTG interface, all three connector types were designed in to facilitate the type of connector customers may integrate into their own system.

phyCORE-LPC3180: What kind of keyboard may connect to X203 on PCM-976?

The keyboard header connector only provides a connection interface to the keyboard pins on the controller. There is no other special circuitry connected. just a direct connection from processor to header. That being said, because of this, there is no keyboard you can just plug directly into the header port that I know of. The appropriate pull-up/pull-down, and key isolation diodes would have to be supplied by the user on their own system, or a little development board. The keyboard port is designed for a matrix keyboard that can support up to 8x8 keys. Basically when you press a key it connects a ROW to COLUMN. The processor detects this and starts a “scan” to detect exactly which key was pressed. The pull-up/down resistors can be found in the NXP LPC3180 hardware manual under the keyboard section (22k and 1M resistors I believe). As for the isolation diodes, these are not required, but they prevent “ghosting” which occurs when they are not installed and more than one key is pressed. When multiple keys are pressed without the diodes the processor will also think several other keys have been pressed which actually haven’t. Doing a quick Google search for “matrix keypad schematic” or something similar should demonstrate this.

phyCORE-LPC3180: Power Consumption

Question:

What's the typical current consumption of the board when running Linux?

Answer:

Here are some power consumption numbers for the phyCORE-LPC3180:
VCC=3.0V
After reset:  24.56mA (avg)
U-boot booting:       78.6mA (max)
U-boot prompt:        64.2mA (avg)
Linux booting:        155.76mA (max)
Linux prompt: 92.16mA (avg)
Linux file copy from USB to SD: 142.08mA (max)
 
These numbers also include peripheral circuitry on the carrier board, so actual numbers for the module itself will be less.

 

phyCORE-LPC3180: SD card

Question:

We are trying to use an SD-card with our platform and we can't get it to work. The start-up auto mount doesn’t find the card and there is the same problem with the manually mount described in the Quick-start guide.

We get this error message:

<Mounting SD/USB storage

<No SD card or unknown filesystem

We have tried to format the SD-card with both vFat(Fat32) and Linux-format(ext2) with the same result. The jumper settings are as described in section 3 page 11 of the manual.

Answer:

As long as J300 is set to 1+2 (SD power always on when board is powered) and
JP302 is set to 1+2 (MMC_DETECT signal connected to processor GPI_5 input) I
am pretty sure it should work fine. I would encourage trying another SD card and going from there.

 

phyCORE-LPC3180: Will the removal of jumper J306 cause the module to be damaged?

When removing that jumper, there will be no VCC supplied to the rest of the circuitry including the SBC module. If you want to connect a multimeter between the two jumper pads to measure current draw, things will be fine. There will be no damage to be expected with J306 removed, as long as you are careful during the desolder process and do not damage the solder pads.

phyCORE-LPC3180: USB faulty

Question:

Is there a fundamental incompatibility that is preventing USB from working on the LPC3180 on the 1248.1 Carrier Board?

Answer:

You must short USB_ID to GND for proper host operation under Linux. The problem you are experiencing is because without the USB_ID shorted to GND, USB_VBUS is not being driven to 5V. The driver is configured to drive USB_VBUS to 5V when USB_ID is connected to GND. The easiest way to connect the ID pin to GND is by placing a solder bridge between the USB_ID pin and the GND pin on the USB OTG connector X303. If you turn the board so the USB connectors face your body, the GND & USB_ID pins are the two pins closest to the USB device connector X302.

 

phyCORE-LPC3180: Is the floating point unit (FPU) supported with the Linux BSP?

Yes, FPU is supported

phyCORE-LPC3180: Adding application program to Linux

Question:

How do I add a simple application program to the existing Linux kernel without rebuilding the kernel?

Answer:

You must unzip the root filesystem and include the executable in the file system. The process will basically be:

    • Unzip filesystem
    • Mount filesystem
    • Copy application into filesystem (into /usr/bin for example)
    • Unmount filesystem
    • Zip file system
    • Add header to filesystem
    • Reflash filesystem to NAND Flash

See our Linux Quickstart manual (http://www.phytec.com/pdf/manuals/L-698e.pdf) section "5.5 Root File System".

 

phyCORE-LPC3180: Linux Cross compiler

Question:

How do I get the cross compiler working?

Answer:

Unpack the “arm-linux-gcc-2004-ql-vfp.tar.gz” into /usr/local/arm/gnu by doing the following:

    • Make the directory /usr/local/arm/gnu if it doesn’t already exist
    • Copy the .tar.gz file into this directory
    • At the prompt type: % tar -zxvf arm-linux-gcc-2004-ql-vfp.tar.gz

 

phyCORE-LPC3180: Sample SPI implementation

Question:

I can't find any sample implementation for using the SPI bus on LPC3180.

Answer:

The Linux BSP for the phyCORE-LPC3180 includes SPI driver support. Find out more here: http://www.phytec.com/products/linux/bsp-LPC3180.html

 

phyCORE-LPC3180: Permanent storage in Linux

Question:

Is there a way to permanently store Linux specific information on the LPC3180 so one doesn’t lose password after recycling power?

Answer:

The entire system is run from a RAM disk which means its volatile and nothing is saved. Normally you would have to rebuild the image to include what you wanted. The user would have to get the NAND system working to save anything and so far we have been unsuccessful in getting this working. We can provide the procedure for accessing the NAND under Linux and the user can attempt to fiddle around with it.

 

phyCORE-LPC3180: Download updated versions

Question:

I am developing a stand-alone application. I need for it to be able to run on its own without the JTAG interface, and to be able to update new versions of the firmware into the Flash.  I have successfully used Phytec's Bootflash utility to write the SIBL, U-Boot, the Linux image, and the Linus File system to the Flash as outlined in section 3.3 of the L-698e.pdf file.

My question is, now that I have Linux and U-Boot running, how do I use these to download updated versions of the firmware that I am developing?

Answer:

You do not need U-Boot/Linux to update your firmware, and in fact you couldn't use them to do it.It sounds like you need two things:

(1) A bootloader to boot your application,

(2) a tool to do field firmware updates.

Currently there exists 3 secondary bootloaders for the LPC3180: (1) Keil bootloader, (2) IAR bootloader, and (3) SIBL. Keil and IAR bootloaders are only available when using their tools. SIBL is available under GPL. Normally SIBL is intended for extracting images from NAND Flash and booting U-Boot, however, it can be used to boot a general application like you need. The only requirement is that you have an image header attached to your application when using SIBL. The image header can be found in the SIBL source on our PHYTEC Spectrum CD. You will see a file called "image.h" which contains the image header struct. U-Boot provides a tool called "mkimage" that takes a binary file and pre-appends this header to create an image that SIBL can boot. If you look in our Linux Quickstart (http://www.phytec.com/pdf/manuals/L-698e.pdf) at the section that covers building U-Boot you will see an example of using the mkimage tool. When creating your own image you can use the "-O uboot" option just like the Quickstart says, despite your application not being U-Boot. SIBL doesn't care about this parameter. You must use "-T firmware" to indicate you have an application that is executable. SIBL basically does the following things:

1. Initializes the clocking scheme

2. Initializes the NAND Flash

3. Initializes the SDRAM

4. Searches for images in the NAND flash and loads them into RAM (at the location specified in the image header).

5. Jumps to the entry poitn of the first executable/firmware image it finds (and has already loaded from NAND flash).

Despite SIBL being primarily used for U-Boot/Linux, SIBL doesn't care what image it boots. This is why you can put an image header on your own binary and use SIBL to boot it. Some things to remember:

1. Your application likely won't require typical startup code

2. Your application should not initialize the SDRAM, NAND Flash, or clocking (you could change clocking at a later point if you wanted).

3. You must specify the entry point of your application when you build it. You need to know this for the 'mkimage' tool.

4. You must place your application at 0x4000 or later in the NAND Flash. The first block of NAND flash is reserved for a secondary bootloader (SIBL in this case).

The second thing you're looking for is the ability to update your firmware in the field. You can do this with two methods:

1. A bootloader that supports this via serial, or some other data transfer interface.

2. A software tool that supports booting an application over UART5#1 does not exist, so unless you wrote something yourself or modified SIBL to support this you're out of luck. #2 does exist in the form of a software application written by NXP called the "LPC3180 Loader". You can use this tool to reflash SIBL and reflash your application in the field via serial. The loader should be supplied on your spectrum CD with the linux source. It's in a folder called "flashloader".


phyCORE-LPC3180: PCB layout

Question:

 I am about to start the PCB layout of our product and need to place the Molex connectors for the LPC3180 SBC. Do you have any detailed PCB layout info?

 

Answer:

Attached you will find a more detailed drawing of the phyCORE-LPC3180 SBC module. You should use the mounting holes as your primary reference point and then go from there to the Molex connector center points. Components in YELLOW are on the bottom side of the units. The SBC is symmetrical.


Download: 1247.2_dimension.pdf, 1248.1_dimension.pdf

 

phyCORE-LPC3180: Download updated versions of stand-alone application

Question:

I am developing a stand-alone application using the Rowley Crossworks compiler. I have successfully used Phytec's Bootflash utility to write the SIBL, U-Boot, Linux image and Linux filesystem to the flash. Now that I have these running, how do I use them to download updated versions of my application? I am aware of the bootup option using UART5 and the GPI_1/SERVICE_N signal of the LPC3180 but our final hardware design may not have provisions for this.

Answer:

First of all, you do not need to install Linux/U-Boot in order to update the firmware, in fact, you couldn't use them to do it.

Next, you would need two things:

    • A bootloader to boot your application
    • A tool to do field firmware updates

Currently, there exists 3 secondary bootloaders for the LPC3180:

(1) Keil bootloader,

(2) IAR bootloader,

(3) SIBL.

Keil and IAR bootloaders are only available when using their tools. SIBL is available under GPL, I believe. Normally, SIBL is intended for extracting images from NAND Flash and booting U-Boot. However, it can be used to boot a general application. The only requirement is that you have an image header attached to your application when using SIBL. The image header can be found in the SIBL source on our PHYTEC Spectrum CD. You will see a file called "image.h" which contains the image header struct. U-Boot provides a tool called "mkimage" that takes a binary file and pre-appends this header to create an image that SIBL can boot.

If you look in our Linux QuickStart (http://www.phytec.com/pdf/manuals/L-698e.pdf) at the Section 5.3,  you will see an example of using the "mkimage" tool. When creating your own image, you can use the "-O uboot" option just like the QuickStart says, despite your application not being U-Boot. SIBL doesn't care about this parameter. You must use "-T firmware" to indicate you have an application that is executable.

SIBL basically does the following things:

    • Initializes the clocking scheme
    • Initializes the NAND Flash
    • Initializes the SDRAM
    • Searches for images in the NAND flash and loads them into RAM (at the location specified in the image header)
    • Jumps to the entry point of the first executable/firmware image it finds (and has already loaded from NAND flash)

Despite SIBL being primarily used for U-Boot/Linux, SIBL doesn't care what image it boots. This is why you can put an image header on your own binary and use SIBL to boot it.

Some things to remember:

    • Your application likely won't  require typical startup code
    • Your application should not initialize the SDRAM, NAND Flash, or clocking (you could change clocking at a later point if you want)
    • You must specify the entry point of your application when you build it. You need to know this for the "mkimage" tool.
    • you must place your application at 0x4000 or later in the NAND Flash. The first block of NAND flash is reserved for a secondary bootloader (SIBL in this case)

The second thing you're looking for is the ability to update your firmware in the field. You can do this with two methods:

    • A bootloader that supports this via serial or some other data transfer interface
    • A software tool that supports booting an application over UART5

#1 doesn't exist, unless you wrote something yourself or modified SIBL to support this. #2 does exist in the form of a software application written by NXP called the "LPC3180 Loader".  You can use this tool to reflash SIBL and reflash your application in the field via serial. The loader should be supplied on your Spectrum CD with the Linux source in a folder called "flashloader".

phyCORE-LPC3180: Communicating to board via USB and RS-232

Question:

I need a driver that a Windows application can use to communicate with the LPC3180 over USB. Also, I was wondering if there is reference code for communicating with the LPC3180 over RS-232

Answer:

Unfortunately, only drivers for Linux and WinCE exist. We do not have code for communicating with LPC3180 over RS-232 but this interface is fairly easy to work with and shouldn’t be too hard to figure out by reading the hardware manual http://www.phytec.com/pdf/manuals/L-681e.pdf

 

phyCORE-LPC3180: Linux Tool chain

Question:

I downloaded the linux port zip file from your website but this file only contains a linux kernel, not arm-linux-gcc cross compile tool chain.

Answer:

We use the ARM Linux GCC toolchain to build Linux Kernel Image and bootloader. All the material related to Linux on the phyCORE-LPC3180 can be found here:
http://www.phytec.com/products/linux/bsp-LPC3180.html
The toolchain is also available via this link:
http://www.phytec.com/zip/LPC3180-Linux/arm-linux-gcc-2004-q1-vfp.tar.gz

phyCORE-LPC3180: Executing from Flash

Question:

I have problems executing the LPC3180 demo code from Flash memory. When I execute from Flash, program crashes and moves on to program_start without any action. Then I execute Erase Option, the program seems to be running with LEDs flashing.

Answer:

It is normal for the LEDs to blink after an erase function and exit the debugger. The code runs from external SDRAM at this point hence if you recycle power, it should not blink. As for executing demo from Flash, there could be several reasons as to why this is so. Check if you updated/copied over all files as described in Section 3.1.3 and 3.1.4 of the QuickStart manual http://www.phytec.com/pdf/manuals/L-698e.pdf . Make sure you don’t have anything else connected to the hardware, like a serial cable. Hit the ‘Run’ command after loading the code to Flash. Verify that you installed the KickStart version that came with the PHYTEC kit.

 

phyCORE-LPC3180: Executing from xRAM

Question:

 

I am able to run the demos from iRAM, not xRAM. I am running the IAR compiler using a JLINK. When I download code to run in xRAM, the debug log displays:

Tue Aug 07 10:39:42 2007: Loaded macro file: C:\Documents and Settings\jnalasco\MyDocuments\ANDYN20\Processors\IAR\Gettingstarted\config\LPC3000_xRAM.mac

Tue Aug 07 10:39:42 2007: DLL version: V3.72a, compiled Jun 18 2007 18:58:11

Tue Aug 07 10:39:42 2007: Firmware: J-Link compiled Jun 14 2007 14:36:33 ARM Rev.5

Tue Aug 07 10:39:42 2007: JTAG speed is fixed to: 1000 kHz

Tue Aug 07 10:39:43 2007: Hardware reset with strategy 1 was performed

Tue Aug 07 10:39:43 2007: Initial reset was performed

Tue Aug 07 10:39:43 2007: J-Link found 2 JTAG devices. ARM core Id: 17900F0F(ARM9), ARM core Id: 00000000(ARM9)

Tue Aug 07 10:39:43 2007: Device at TAP0 selected

Tue Aug 07 10:39:43 2007: Resetting target using RESET pin

Tue Aug 07 10:39:43 2007: CP15.0.0: 0x41069264: ARM, Architecure 5TEJ

Tue Aug 07 10:39:43 2007: CP15.0.1: 0x1D192192: ICache: 32kB (4*256*32), DCache: 32kB (4*256*32)

Tue Aug 07 10:39:43 2007: J-Link: ARM9 CP15 Settings changed: 50078 from 78, MMU Off, ICache Off, DCache Off

Tue Aug 07 10:39:43 2007: Hardware reset with strategy 0 was performed

Tue Aug 07 10:39:48 2007: Write memory error @ address 0x31080020, word access: Core error.

Tue Aug 07 10:39:49 2007: Error in C:\Documents and Settings\jnalasco\My Documents\ANDYN20\Processors\IAR\Gettingstarted\config\LPC3000_xRAM.mac at line 61, col 18: Operation error.

Tue Aug 07 10:39:49 2007: Error while calling macro execUserPreload

Tue Aug 07 10:39:49 2007: Failed to load debugee: C:\Documents andSettings\jnalasco\MyDocuments\ANDYN20\Processors\IAR\Gettingstarted\LPC3180 Ext SDRAM\Exe\GettingStarted.d79

Answer:

What is happening here is that the processor is telling the debugger that it can't access one of the SDRAM registers. When you choose the xSDRAM configuration, the debugger downloads and executes an SDRAM initialization macro before loading your application code into SDRAM. Make sure you have the latest version of IAR Embedded Workbench. We have had new releases on the JLink driver break operation with the LPC3180 in the past. Try getting a version like the 3.14c drivers we have on our website since it works correctly http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM9-LPC3180.html . Scroll down to the "Technical Documentation and Demos" section and you'll see it as the last item in the list of files to download. J-Link drivers are available from Segger at http://www.segger.com . Once you download and install the JLink drivers, copy the jlink.exe and jlinkarm.dll from the Segger install folder into your IAR bin directory.

 

 

phyCORE-LPC3180: Hex file

Question:

How can I download the hex file into Flash and execute directly without ULINK2?

Answer:

Please take a look at our QuickStart manual for KEIL and the demos provided on the CD-ROM. Also available online: http://www.phytec.com/pdf/manuals/L-690e.pdf
http://www.phytec.com/zip/Demos_PCM-031_K.zip

 

phyCORE-LPC3180: Flash Programming

 

Question:

I want to program to flash.  I seem to understand from the documentation that I need some sort of a bootloader. I cannot seem to program to flash...

Answer:

The steps for programming the Flash depend on the tools you are using. Please refer to the appropriate QuickStart instructions below:

Keil: http://www.phytec.com/pdf/manuals/L-690e.pdf

IAR: http://www.phytec.com/pdf/manuals/L-689e.pdf

Software Demo Download from : http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM9-LPC3180.html

Linux: http://www.phytec.com/products/linux/bsp-LPC3180.html

For further support please contace support@phytec.com

 

phyCORE-LPC3180: USB Host for PCM-976 (1248.1)

The following article only applies to PHYTEC Carrier Board PCM-976 verion 1248.1. Carrier Board 1248.1 has jumper settings for forced Host mode.

USB Host is supposed to output 5V on the "VBUS" pin of the USB connector. This pin is connected to the VBUS pin of the ISP1301 transceiver on our board. When the proper bit in a configuration register on the ISP1301 is set it will then drive the VBUS pin to 5V. This is required for proper host mode operation. Currently NXP has provided a "software workaround" by temporarily forcing the OTG driver into host mode through a setting in a file in linux. Although this does properly switch the mode so the transceiver is operating as host, it does NOT set the bit required to drive VBUS to 5V.

The FORCED host mode must drive VBUS to 5V by setting the proper bit in the ISP1301 configuration register. Unfortunately the current OTG driver does not handle it in this way, but there is a hardware workaround:

 

Currently the OTG drivers are configured to drive VBUS to 5V when the USB_ID pin is grounded. So you can simply install a jumper wire on the carrier board that connects the USB_ID pin to GND. You can do this either on the USB OTG (miniAB) connector or from the expansion bus on the molex. I recommend the USB connector (see attached schematics).

 1)     Orient the Carrier Board so that the USB connectors are pointing towards you.

 2)     Locate the USB mini connector. Find the 5 pins on the PCB just near the center of the mini connector (not the Sheild Pins).

 3)     The USB_ID pin and Ground pin are the two pins closest to the USB device connector.

 4)     Solder these two pins together. \

 5)     Now your USB driver should properly put the board in Host mode so you can use your Hub

 6)     Reboot Linux on phyCORE-LPC3180

 7)     Change directory as follows:. ~ # cd  /sys/devices/platform/container-dev-1

 8)     Force the mode to host with the following command            

 /sys/devices/platform/container-dev-1 # echo > forced_mode host

Error: otg FSM in unkownen state. Forceing to idle

ohci ohci1: new USB bus registered, assigned bus number 1

hub 1-0:1.0: USB hub found

hub 1-0:1.0: 2 ports detected

ohci ohci1: new USB bus registered, assigned bus number 2

/sys/devices/platform/container-dev-1 # usb 2-1: new full speed USB device using ohci and address 2

hub 2-1:1.0: USB hub found

hub 2-1:1.0: 4 ports detected

usb 2-1.2: new full speed USB device using ohci and address 3

eth0: register usbnet at usb-lpc3180-1.2, ASIX AX8817x USB 2.0 Ethernet, 00:10:60:0a:55:f8

 

 

 

 

phyCORE-LPC3180: Voltage tolerance

Question:

Does the module need +/- 0.1V tolerance on the 3.0V?

Answer:

This is more or less a constraint of the supervisor. The nominal reset voltage is 2.8V but can be as high as 2.85V. It is probably best to operate the module at 3.0V, but the maximum voltage is set by the controller at 3.3V.

 

phyCORE-LPC3180: UART

Question:

I am unable to write to UART4 and UART6. The pin is multiplexed to UART as well as GPIO.

Answer:

Please refer to the NXPLPC3180 User Manual. Look at the UARTCLK_CTRL registers in Chapter 4 of the manual. It is likely that you don’t have the clocks to those UARTs enabled.

 

phyCORE-LPC3180: SD/MMC card speed

Question:

Would the LPC3180 fulfill my requirements of an A/D input capable of 200K 16bps, with SD/MMC card slot and 32MB or RAM?

Answer:

The LPC3180 has 32MB of RAM and SD card interface but you would need SPI interface since it can operate up to 52MHz.

 

phyCORE-LPC3180: Power Consumption

<font size="2">Current measurements, not measured under full loading conditions, show reading/writing to SDRAM is approximately 70 mA @ 3.0 V.</font>

Linux

phyCORE-LPC3250: "Error opening block device" using Linux ls comand

Bitte immer beachten, dass eine SD Karte zum LPC3250 Kit NICHT High Density sein darf (nur normale, 512 Mbyte sind ausreichend), ebenso muss die Karte mit FAT32 formattiert sein! FAT32 LBA führt zu Problemen (bei ls kommt dann Error opening block device).

 

Wenn Sie den Inhalt der Karte versehenlich gelöscht / zerstört haben oder die Karte verloren haben, finden Sie in der rechten Spalte unter Downloads / Software das Image für die SD Card.

phyCORE-3180: Is the generic USB device supported as well as the Ethernet adapter in the Linux BSP?

The SMC2209ETH/USB is supported. I am unsure what other devices are supported in the BSP. This was given to us by NXP “as-is”. I imagine various generic devices are supported. I know mass storage drives are supported.

phyCORE-LPC3180: Adding application program to Linux

Question:

How do I add a simple application program to the existing Linux kernel without rebuilding the kernel?

Answer:

You must unzip the root filesystem and include the executable in the file system. The process will basically be:

    • Unzip filesystem
    • Mount filesystem
    • Copy application into filesystem (into /usr/bin for example)
    • Unmount filesystem
    • Zip file system
    • Add header to filesystem
    • Reflash filesystem to NAND Flash

See our Linux Quickstart manual (http://www.phytec.com/pdf/manuals/L-698e.pdf) section "5.5 Root File System".

 

phyCORE-LPC3180: Linux Cross compiler

Question:

How do I get the cross compiler working?

Answer:

Unpack the “arm-linux-gcc-2004-ql-vfp.tar.gz” into /usr/local/arm/gnu by doing the following:

    • Make the directory /usr/local/arm/gnu if it doesn’t already exist
    • Copy the .tar.gz file into this directory
    • At the prompt type: % tar -zxvf arm-linux-gcc-2004-ql-vfp.tar.gz

 

phyCORE-LPC3180: Sample SPI implementation

Question:

I can't find any sample implementation for using the SPI bus on LPC3180.

Answer:

The Linux BSP for the phyCORE-LPC3180 includes SPI driver support. Find out more here: http://www.phytec.com/products/linux/bsp-LPC3180.html

 

phyCORE-LPC3180: Permanent storage in Linux

Question:

Is there a way to permanently store Linux specific information on the LPC3180 so one doesn’t lose password after recycling power?

Answer:

The entire system is run from a RAM disk which means its volatile and nothing is saved. Normally you would have to rebuild the image to include what you wanted. The user would have to get the NAND system working to save anything and so far we have been unsuccessful in getting this working. We can provide the procedure for accessing the NAND under Linux and the user can attempt to fiddle around with it.

 

phyCORE-LPC3180: Download updated versions

Question:

I am developing a stand-alone application. I need for it to be able to run on its own without the JTAG interface, and to be able to update new versions of the firmware into the Flash.  I have successfully used Phytec's Bootflash utility to write the SIBL, U-Boot, the Linux image, and the Linus File system to the Flash as outlined in section 3.3 of the L-698e.pdf file.

My question is, now that I have Linux and U-Boot running, how do I use these to download updated versions of the firmware that I am developing?

Answer:

You do not need U-Boot/Linux to update your firmware, and in fact you couldn't use them to do it.It sounds like you need two things:

(1) A bootloader to boot your application,

(2) a tool to do field firmware updates.

Currently there exists 3 secondary bootloaders for the LPC3180: (1) Keil bootloader, (2) IAR bootloader, and (3) SIBL. Keil and IAR bootloaders are only available when using their tools. SIBL is available under GPL. Normally SIBL is intended for extracting images from NAND Flash and booting U-Boot, however, it can be used to boot a general application like you need. The only requirement is that you have an image header attached to your application when using SIBL. The image header can be found in the SIBL source on our PHYTEC Spectrum CD. You will see a file called "image.h" which contains the image header struct. U-Boot provides a tool called "mkimage" that takes a binary file and pre-appends this header to create an image that SIBL can boot. If you look in our Linux Quickstart (http://www.phytec.com/pdf/manuals/L-698e.pdf) at the section that covers building U-Boot you will see an example of using the mkimage tool. When creating your own image you can use the "-O uboot" option just like the Quickstart says, despite your application not being U-Boot. SIBL doesn't care about this parameter. You must use "-T firmware" to indicate you have an application that is executable. SIBL basically does the following things:

1. Initializes the clocking scheme

2. Initializes the NAND Flash

3. Initializes the SDRAM

4. Searches for images in the NAND flash and loads them into RAM (at the location specified in the image header).

5. Jumps to the entry poitn of the first executable/firmware image it finds (and has already loaded from NAND flash).

Despite SIBL being primarily used for U-Boot/Linux, SIBL doesn't care what image it boots. This is why you can put an image header on your own binary and use SIBL to boot it. Some things to remember:

1. Your application likely won't require typical startup code

2. Your application should not initialize the SDRAM, NAND Flash, or clocking (you could change clocking at a later point if you wanted).

3. You must specify the entry point of your application when you build it. You need to know this for the 'mkimage' tool.

4. You must place your application at 0x4000 or later in the NAND Flash. The first block of NAND flash is reserved for a secondary bootloader (SIBL in this case).

The second thing you're looking for is the ability to update your firmware in the field. You can do this with two methods:

1. A bootloader that supports this via serial, or some other data transfer interface.

2. A software tool that supports booting an application over UART5#1 does not exist, so unless you wrote something yourself or modified SIBL to support this you're out of luck. #2 does exist in the form of a software application written by NXP called the "LPC3180 Loader". You can use this tool to reflash SIBL and reflash your application in the field via serial. The loader should be supplied on your spectrum CD with the linux source. It's in a folder called "flashloader".


phyCORE-LPC3180: Download updated versions of stand-alone application

Question:

I am developing a stand-alone application using the Rowley Crossworks compiler. I have successfully used Phytec's Bootflash utility to write the SIBL, U-Boot, Linux image and Linux filesystem to the flash. Now that I have these running, how do I use them to download updated versions of my application? I am aware of the bootup option using UART5 and the GPI_1/SERVICE_N signal of the LPC3180 but our final hardware design may not have provisions for this.

Answer:

First of all, you do not need to install Linux/U-Boot in order to update the firmware, in fact, you couldn't use them to do it.

Next, you would need two things:

    • A bootloader to boot your application
    • A tool to do field firmware updates

Currently, there exists 3 secondary bootloaders for the LPC3180:

(1) Keil bootloader,

(2) IAR bootloader,

(3) SIBL.

Keil and IAR bootloaders are only available when using their tools. SIBL is available under GPL, I believe. Normally, SIBL is intended for extracting images from NAND Flash and booting U-Boot. However, it can be used to boot a general application. The only requirement is that you have an image header attached to your application when using SIBL. The image header can be found in the SIBL source on our PHYTEC Spectrum CD. You will see a file called "image.h" which contains the image header struct. U-Boot provides a tool called "mkimage" that takes a binary file and pre-appends this header to create an image that SIBL can boot.

If you look in our Linux QuickStart (http://www.phytec.com/pdf/manuals/L-698e.pdf) at the Section 5.3,  you will see an example of using the "mkimage" tool. When creating your own image, you can use the "-O uboot" option just like the QuickStart says, despite your application not being U-Boot. SIBL doesn't care about this parameter. You must use "-T firmware" to indicate you have an application that is executable.

SIBL basically does the following things:

    • Initializes the clocking scheme
    • Initializes the NAND Flash
    • Initializes the SDRAM
    • Searches for images in the NAND flash and loads them into RAM (at the location specified in the image header)
    • Jumps to the entry point of the first executable/firmware image it finds (and has already loaded from NAND flash)

Despite SIBL being primarily used for U-Boot/Linux, SIBL doesn't care what image it boots. This is why you can put an image header on your own binary and use SIBL to boot it.

Some things to remember:

    • Your application likely won't  require typical startup code
    • Your application should not initialize the SDRAM, NAND Flash, or clocking (you could change clocking at a later point if you want)
    • You must specify the entry point of your application when you build it. You need to know this for the "mkimage" tool.
    • you must place your application at 0x4000 or later in the NAND Flash. The first block of NAND flash is reserved for a secondary bootloader (SIBL in this case)

The second thing you're looking for is the ability to update your firmware in the field. You can do this with two methods:

    • A bootloader that supports this via serial or some other data transfer interface
    • A software tool that supports booting an application over UART5

#1 doesn't exist, unless you wrote something yourself or modified SIBL to support this. #2 does exist in the form of a software application written by NXP called the "LPC3180 Loader".  You can use this tool to reflash SIBL and reflash your application in the field via serial. The loader should be supplied on your Spectrum CD with the Linux source in a folder called "flashloader".

phyCORE-LPC3180: Communicating to board via USB and RS-232

Question:

I need a driver that a Windows application can use to communicate with the LPC3180 over USB. Also, I was wondering if there is reference code for communicating with the LPC3180 over RS-232

Answer:

Unfortunately, only drivers for Linux and WinCE exist. We do not have code for communicating with LPC3180 over RS-232 but this interface is fairly easy to work with and shouldn’t be too hard to figure out by reading the hardware manual http://www.phytec.com/pdf/manuals/L-681e.pdf

 

phyCORE-LPC3180: Linux Tool chain

Question:

I downloaded the linux port zip file from your website but this file only contains a linux kernel, not arm-linux-gcc cross compile tool chain.

Answer:

We use the ARM Linux GCC toolchain to build Linux Kernel Image and bootloader. All the material related to Linux on the phyCORE-LPC3180 can be found here:
http://www.phytec.com/products/linux/bsp-LPC3180.html
The toolchain is also available via this link:
http://www.phytec.com/zip/LPC3180-Linux/arm-linux-gcc-2004-q1-vfp.tar.gz

phyCORE-LPC3180: Executing from Flash

Question:

I have problems executing the LPC3180 demo code from Flash memory. When I execute from Flash, program crashes and moves on to program_start without any action. Then I execute Erase Option, the program seems to be running with LEDs flashing.

Answer:

It is normal for the LEDs to blink after an erase function and exit the debugger. The code runs from external SDRAM at this point hence if you recycle power, it should not blink. As for executing demo from Flash, there could be several reasons as to why this is so. Check if you updated/copied over all files as described in Section 3.1.3 and 3.1.4 of the QuickStart manual http://www.phytec.com/pdf/manuals/L-698e.pdf . Make sure you don’t have anything else connected to the hardware, like a serial cable. Hit the ‘Run’ command after loading the code to Flash. Verify that you installed the KickStart version that came with the PHYTEC kit.

 

phyCORE-LPC3180: Flash Programming

 

Question:

I want to program to flash.  I seem to understand from the documentation that I need some sort of a bootloader. I cannot seem to program to flash...

Answer:

The steps for programming the Flash depend on the tools you are using. Please refer to the appropriate QuickStart instructions below:

Keil: http://www.phytec.com/pdf/manuals/L-690e.pdf

IAR: http://www.phytec.com/pdf/manuals/L-689e.pdf

Software Demo Download from : http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM9-LPC3180.html

Linux: http://www.phytec.com/products/linux/bsp-LPC3180.html

For further support please contace support@phytec.com

 

phyCORE-LPC3180: USB Host for PCM-976 (1248.1)

The following article only applies to PHYTEC Carrier Board PCM-976 verion 1248.1. Carrier Board 1248.1 has jumper settings for forced Host mode.

USB Host is supposed to output 5V on the "VBUS" pin of the USB connector. This pin is connected to the VBUS pin of the ISP1301 transceiver on our board. When the proper bit in a configuration register on the ISP1301 is set it will then drive the VBUS pin to 5V. This is required for proper host mode operation. Currently NXP has provided a "software workaround" by temporarily forcing the OTG driver into host mode through a setting in a file in linux. Although this does properly switch the mode so the transceiver is operating as host, it does NOT set the bit required to drive VBUS to 5V.

The FORCED host mode must drive VBUS to 5V by setting the proper bit in the ISP1301 configuration register. Unfortunately the current OTG driver does not handle it in this way, but there is a hardware workaround:

 

Currently the OTG drivers are configured to drive VBUS to 5V when the USB_ID pin is grounded. So you can simply install a jumper wire on the carrier board that connects the USB_ID pin to GND. You can do this either on the USB OTG (miniAB) connector or from the expansion bus on the molex. I recommend the USB connector (see attached schematics).

 1)     Orient the Carrier Board so that the USB connectors are pointing towards you.

 2)     Locate the USB mini connector. Find the 5 pins on the PCB just near the center of the mini connector (not the Sheild Pins).

 3)     The USB_ID pin and Ground pin are the two pins closest to the USB device connector.

 4)     Solder these two pins together. \

 5)     Now your USB driver should properly put the board in Host mode so you can use your Hub

 6)     Reboot Linux on phyCORE-LPC3180

 7)     Change directory as follows:. ~ # cd  /sys/devices/platform/container-dev-1

 8)     Force the mode to host with the following command            

 /sys/devices/platform/container-dev-1 # echo > forced_mode host

Error: otg FSM in unkownen state. Forceing to idle

ohci ohci1: new USB bus registered, assigned bus number 1

hub 1-0:1.0: USB hub found

hub 1-0:1.0: 2 ports detected

ohci ohci1: new USB bus registered, assigned bus number 2

/sys/devices/platform/container-dev-1 # usb 2-1: new full speed USB device using ohci and address 2

hub 2-1:1.0: USB hub found

hub 2-1:1.0: 4 ports detected

usb 2-1.2: new full speed USB device using ohci and address 3

eth0: register usbnet at usb-lpc3180-1.2, ASIX AX8817x USB 2.0 Ethernet, 00:10:60:0a:55:f8

 

 

 

 

Keil ARM / RealView

phyCORE-LPC2294: JTAG error message

Question:

JTAG interface reports “Couldn’t stop ARM device” when I upload the blinky.hex file.

Answer:

There are several things that you should check to assure proper use of the device:

Make sure that the external flash is erased before programming it to iFlash. Unplug the USB cable from the ULink and restart uVision. Go to http://www.keil.com/support/docs/2763.htm to make sure you have the most recent ULink drivers. If you are using an old Phytec Spectrum CD, go to our website to obtain the latest blinky.hex file available in the section “Documents and Demos” http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM7-LPC229x.html#documentation.

 

phyCORE-LPC2294: Demo updates

Question:

I have a copy of the old Phytec Spectrum CD. Where can I get updates?

Answer:

Please refer to our website to obtain the latest demos available in the section “Documents and Demos” http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM7-LPC229x.html#documentation. Also, check for the latest version of the uVision tools at http://www.keil.com/demo/eval/arm.htm

phyCORE-LPC2294: XFlash erase

Question:

I am unable to get my board to communicate with the JTAG/ULINK for XFlash download/erase.

Answer:

Check if there is anything in the external flash that modifies the LPC2294 controller configuration in a way that does not allow any JTAG communication. If you have troubles erasing external Flash, force the chip into ISP mode by using BOOT and RESET push button sequence. Press both buttons; release the reset button and then the boot button a few seconds later. After putting the module into ISP mode, click on the ‘LOAD’ icon or Flash/Erase in uVision3 with the XFLash target being active.        

RealView ICE

Question:

Does the RealView ICE support the NXP i.MX31 processor?

Answer:

Yes

phyCORE-LPC3180: Serial Communication Example

Question:

I need examples of how to use serial communication for the LPC3180.

Answer:

We currently don't have any examples for that but we have examples for IAR. Here's the basic procedure for getting UART5 to work in polling mode (see LPC3180 manual from NXP for register descriptions):

    • Set the DLAB bit to "1" in the U5LCR register
    • Write to the U5DLM & U5DLL registers to set the baud rate.. this is calculated from either HCLK or PERIPH_CLK.. best bet is to set the registers (see later steps) to use HCLK as the clock source...if using Keil & have used config wizard to init clocks, then look to this for HCLK value...probably going to be set to 104MHz if maximum operation frequency is set.
    • Set the DLAB bit in the U5LCR register to "0"
    • Write to the U5CLK register to set the X & Y values (see baud rate calculations in manual)
    • Set the CLK_SEL bit to "1" in the U5CLK register... this will select HCLK as the clock source for uart baud generation
    • Set the UART5_CLK bit to "1" in the UART_CLKMODE register to enable the
      UART5 clock domain
    • Set the WLS bits in the U5LCR register to 0x3 for 8 bits, no parity, 1 stop bit
    • Set the FCTRL bit in the U5FCR register to "1" for proper fifo operation
    • Set the TFR bit to "1" in the U5FCR register to reset the TX fifo
    • Set the RFR bit to "1" in the U5FCR register to reset the RX fifo
    • Set the FCRFE bit to "1" in the U5FCR register to enable the TX/RX fifos

 

To send a byte:
1) write 8 bits of data to the U5THR register
2) poll the TEMT bit in the U5LSR register to wait until the byte is transmitted

 

To receive a byte:
1) poll the DR bit in the U5LSR register...as long as it is 0 no data has been received in the receive buffer
2) read the data out of the U5RBR register after the DR bit in U5LSR has been set

to read and write the registers just map a variable equal to the register width to the memory location of the register like so:

The U5LSR register is located at 0x40080014 (per the lpc3180 manual) and is a an 8 bit register:

 

#define U5LSR (*(volatile unsigned char*)0x40080014)

void main(void)
{
....
U5LSR = 0x6; // access example
}

The Keil 3180 header file should have all of these register defined. Look to this instead of defining each register manually.

 

phyCORE-LPC3180: Interrupt driven UART

Question:

 I'd like to transmit data using interrupts. Once the output buffer is filled in I'm enabling THRE interrupts in UxIER register and I'm expecting the interrupt to show up immediately to fetch the first character from a buffer. Unfortunately, I don't see this happening. The interrupt is not generated as expected. If I just write one byte to UxTHR (from debugger for example) then, after that bytes go out, I see an interrupt. Why isn’t the interrupt generated when it’s just enabled? The interrupt controller is configured to act on level high.

Answer:

We do not have any interrupt driven UART examples, unfortunately. I assume the reason the UART does not trigger an interrupt even though the buffer is empty when the THRE interrupt is enabled is because it is already empty and has not come to the state of empty due to transmitting characters previously in the buffer. If it triggered on the act of being empty then it would continually keep triggering until something was put in it instead of triggering only when becoming empty. This would of course lead to a stack overflow very quickly as the UART kept interrupting itself. Therefore, enabling the interrupt doesn't create the same edge that the UART circuitry will create when the buffer becomes empty, hence no interrupt.

 

phyCORE-LPC3180: Hex file

Question:

How can I download the hex file into Flash and execute directly without ULINK2?

Answer:

Please take a look at our QuickStart manual for KEIL and the demos provided on the CD-ROM. Also available online: http://www.phytec.com/pdf/manuals/L-690e.pdf
http://www.phytec.com/zip/Demos_PCM-031_K.zip

 

phyCORE-LPC3180: Flash Programming

 

Question:

I want to program to flash.  I seem to understand from the documentation that I need some sort of a bootloader. I cannot seem to program to flash...

Answer:

The steps for programming the Flash depend on the tools you are using. Please refer to the appropriate QuickStart instructions below:

Keil: http://www.phytec.com/pdf/manuals/L-690e.pdf

IAR: http://www.phytec.com/pdf/manuals/L-689e.pdf

Software Demo Download from : http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM9-LPC3180.html

Linux: http://www.phytec.com/products/linux/bsp-LPC3180.html

For further support please contace support@phytec.com

 

Alternative to Philips Flash Utility

Question:

Is there a way to erase the flash without using the Philips flash utility? I am using the KEIL software development tool.

Answer:

You can erase both on-chip and external/on-board Flash from within Keil's uV3. Section 3.3 of the QuickStart tells you about the required Flash algorithms.

 

Issues with ULINK

Question:

I am unable to program iFLASH using ULINK.

Answer:

Check if Keil ULINK is detected by your system by looking under Project > Options for target > Debug > use Keil ULINK > Setting option. Once the system has detected the ULINK, it should show your device in the JTAG device chain field. If your device is detected, then you only will be able to program the on chip flash of the controller. Before entering the debugger, you have to program the on chip flash and then enter the debugger.

 

phyCORE-LPC2294: JTAG error

Question:

I have an error message “JTAG Device Chain Error” when downloading the blinky demo into xFLASH.

Answer:

Make sure you have the latest version of the CARM tools from http://www.keil.com/update/arm.asp , install MDK-ARM Version 3.15b and download the latest blinky demo at http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM7-LPC229x.html#documentation

 

phyCORE-LPC2294: Using IAR J-Link with Keil uVision3

Question:

How can the Keil EasyWEB demo be used with an IAR J-Link?

Answer:

Keil provides support for the J-Link with the update that can be downloaded at:  http://www.keil.com/update/sw/carm/2.32a

This update has added RDI support which allows you to connect the µVision3 Debugger to RDI-compliant devices. Detailed information is available in the Getting Started User's Guide — RDI Interface Driver.

 

phyCORE-LPC2294: VICVectAddr

 

Question:

I have a simple question in regards to the implementation of the interrupts. I have found the sample code written that comes with the installation:

long timeval;
/* Timer Counter 0 Interrupt executes each 10ms @ 60 MHz CPU Clock */
void tc0 (void) __irq {
++timeval;
T0IR = 1; // Clear interrupt flag
VICVectAddr = 0; // Acknowledge Interrupt
}

The question is: What value do we assign to VICVectAddr to acknowledge interrupt? ie if we have more that one interrupts namely, comRX and Timer? do we feed in "0" (VICVectAddr = 0) in any case?

Answer:

The VICVectAddr Register contains the jump address for the ISR after a hardware interrupt occurred. Shortly before ending the ISR this register should be written in order to execute a sort of End of Interrupt. Since Philips didn't specify which value one should write to this register it doesn't matter what you write. The only important thing is that the register is written to. It is possible to write "0" to this register, no matter from which ISR initiated the write access.

 

phyCORE-LPC2294: Trouble with Demo

<font size="4">Question:
</font>

I am using the Demo Keil uVision3 development system sent with a PHYTEC LCP2294 board. Going through the QuickStart app note, I have noticed some differences between the pictures and the explanations. I've solved some of them but I'm stuck at selecting the target processor. I click on the pull down menu but only get two choices: "Simulator" and "LPC2100". I then clicked on the "Options for Target" button and under the "Device" panel I find LPC2294 (the pull-down menu label remains at LPC2100). Once selected, I followed the instructions and downloaded the "Blinky" code. The code downloaded but did not run. I, then, downloaded the pre-compiled (.hex) file using RS232 connection and it worked fine. Is there something I am missing in the instructions? Any help would be greatly appreciated. Also, do you have any sample code for using the Ethernet port? I understood that there is no support on the CAN (DeviceNet) side but I thought there would be something on the Ethernet side.

<font size="4">Answer:</font>

It sounds like you have the wrong demos. Please refer to the demos on the Spectrum CD, which were included in your Kit. Browse to the phyBASIC folder and copy the phyCORE-LPC2294 demos to your C: drive. There is also an Ethernet demo on the Spectrum CD …\PhyExt\pC-LPC2294\Keil.

phyCORE-LPC2294: Compatibility with ARM Multi-ICE RealView development/debug system

 

Question:

I'm about to purchase a phyCORE-ARM7/LPC229x Rapid Development Kit and would like to know if it is compatible with my ARM Multi-ICE RealView development/debug system. TheARM Multi-ICE uses a 20-pin JTAG interface and CodeWarrior/AXD for code development and debug interface.

Answer:

The ARM Multi-ICE is in the list of development tool support from Philips for the LPC2292/94 processor. There is a 20-pin JTAG interface on our board so phyCORE-LPC2294 should be compatible with these tools.

 

IAR

phyCORE-LPC3180: Serial Communication Example

Question:

I need examples of how to use serial communication for the LPC3180.

Answer:

We currently don't have any examples for that but we have examples for IAR. Here's the basic procedure for getting UART5 to work in polling mode (see LPC3180 manual from NXP for register descriptions):

    • Set the DLAB bit to "1" in the U5LCR register
    • Write to the U5DLM & U5DLL registers to set the baud rate.. this is calculated from either HCLK or PERIPH_CLK.. best bet is to set the registers (see later steps) to use HCLK as the clock source...if using Keil & have used config wizard to init clocks, then look to this for HCLK value...probably going to be set to 104MHz if maximum operation frequency is set.
    • Set the DLAB bit in the U5LCR register to "0"
    • Write to the U5CLK register to set the X & Y values (see baud rate calculations in manual)
    • Set the CLK_SEL bit to "1" in the U5CLK register... this will select HCLK as the clock source for uart baud generation
    • Set the UART5_CLK bit to "1" in the UART_CLKMODE register to enable the
      UART5 clock domain
    • Set the WLS bits in the U5LCR register to 0x3 for 8 bits, no parity, 1 stop bit
    • Set the FCTRL bit in the U5FCR register to "1" for proper fifo operation
    • Set the TFR bit to "1" in the U5FCR register to reset the TX fifo
    • Set the RFR bit to "1" in the U5FCR register to reset the RX fifo
    • Set the FCRFE bit to "1" in the U5FCR register to enable the TX/RX fifos

 

To send a byte:
1) write 8 bits of data to the U5THR register
2) poll the TEMT bit in the U5LSR register to wait until the byte is transmitted

 

To receive a byte:
1) poll the DR bit in the U5LSR register...as long as it is 0 no data has been received in the receive buffer
2) read the data out of the U5RBR register after the DR bit in U5LSR has been set

to read and write the registers just map a variable equal to the register width to the memory location of the register like so:

The U5LSR register is located at 0x40080014 (per the lpc3180 manual) and is a an 8 bit register:

 

#define U5LSR (*(volatile unsigned char*)0x40080014)

void main(void)
{
....
U5LSR = 0x6; // access example
}

The Keil 3180 header file should have all of these register defined. Look to this instead of defining each register manually.

 

phyCORE-LPC3180: Interrupt driven UART

Question:

 I'd like to transmit data using interrupts. Once the output buffer is filled in I'm enabling THRE interrupts in UxIER register and I'm expecting the interrupt to show up immediately to fetch the first character from a buffer. Unfortunately, I don't see this happening. The interrupt is not generated as expected. If I just write one byte to UxTHR (from debugger for example) then, after that bytes go out, I see an interrupt. Why isn’t the interrupt generated when it’s just enabled? The interrupt controller is configured to act on level high.

Answer:

We do not have any interrupt driven UART examples, unfortunately. I assume the reason the UART does not trigger an interrupt even though the buffer is empty when the THRE interrupt is enabled is because it is already empty and has not come to the state of empty due to transmitting characters previously in the buffer. If it triggered on the act of being empty then it would continually keep triggering until something was put in it instead of triggering only when becoming empty. This would of course lead to a stack overflow very quickly as the UART kept interrupting itself. Therefore, enabling the interrupt doesn't create the same edge that the UART circuitry will create when the buffer becomes empty, hence no interrupt.

 

phyCORE-LPC3180: Executing from xRAM

Question:

 

I am able to run the demos from iRAM, not xRAM. I am running the IAR compiler using a JLINK. When I download code to run in xRAM, the debug log displays:

Tue Aug 07 10:39:42 2007: Loaded macro file: C:\Documents and Settings\jnalasco\MyDocuments\ANDYN20\Processors\IAR\Gettingstarted\config\LPC3000_xRAM.mac

Tue Aug 07 10:39:42 2007: DLL version: V3.72a, compiled Jun 18 2007 18:58:11

Tue Aug 07 10:39:42 2007: Firmware: J-Link compiled Jun 14 2007 14:36:33 ARM Rev.5

Tue Aug 07 10:39:42 2007: JTAG speed is fixed to: 1000 kHz

Tue Aug 07 10:39:43 2007: Hardware reset with strategy 1 was performed

Tue Aug 07 10:39:43 2007: Initial reset was performed

Tue Aug 07 10:39:43 2007: J-Link found 2 JTAG devices. ARM core Id: 17900F0F(ARM9), ARM core Id: 00000000(ARM9)

Tue Aug 07 10:39:43 2007: Device at TAP0 selected

Tue Aug 07 10:39:43 2007: Resetting target using RESET pin

Tue Aug 07 10:39:43 2007: CP15.0.0: 0x41069264: ARM, Architecure 5TEJ

Tue Aug 07 10:39:43 2007: CP15.0.1: 0x1D192192: ICache: 32kB (4*256*32), DCache: 32kB (4*256*32)

Tue Aug 07 10:39:43 2007: J-Link: ARM9 CP15 Settings changed: 50078 from 78, MMU Off, ICache Off, DCache Off

Tue Aug 07 10:39:43 2007: Hardware reset with strategy 0 was performed

Tue Aug 07 10:39:48 2007: Write memory error @ address 0x31080020, word access: Core error.

Tue Aug 07 10:39:49 2007: Error in C:\Documents and Settings\jnalasco\My Documents\ANDYN20\Processors\IAR\Gettingstarted\config\LPC3000_xRAM.mac at line 61, col 18: Operation error.

Tue Aug 07 10:39:49 2007: Error while calling macro execUserPreload

Tue Aug 07 10:39:49 2007: Failed to load debugee: C:\Documents andSettings\jnalasco\MyDocuments\ANDYN20\Processors\IAR\Gettingstarted\LPC3180 Ext SDRAM\Exe\GettingStarted.d79

Answer:

What is happening here is that the processor is telling the debugger that it can't access one of the SDRAM registers. When you choose the xSDRAM configuration, the debugger downloads and executes an SDRAM initialization macro before loading your application code into SDRAM. Make sure you have the latest version of IAR Embedded Workbench. We have had new releases on the JLink driver break operation with the LPC3180 in the past. Try getting a version like the 3.14c drivers we have on our website since it works correctly http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM9-LPC3180.html . Scroll down to the "Technical Documentation and Demos" section and you'll see it as the last item in the list of files to download. J-Link drivers are available from Segger at http://www.segger.com . Once you download and install the JLink drivers, copy the jlink.exe and jlinkarm.dll from the Segger install folder into your IAR bin directory.

 

 

phyCORE-LPC3180: Flash Programming

 

Question:

I want to program to flash.  I seem to understand from the documentation that I need some sort of a bootloader. I cannot seem to program to flash...

Answer:

The steps for programming the Flash depend on the tools you are using. Please refer to the appropriate QuickStart instructions below:

Keil: http://www.phytec.com/pdf/manuals/L-690e.pdf

IAR: http://www.phytec.com/pdf/manuals/L-689e.pdf

Software Demo Download from : http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM9-LPC3180.html

Linux: http://www.phytec.com/products/linux/bsp-LPC3180.html

For further support please contace support@phytec.com

 

phyCORE-LPC2294: IAR tutorial

Question:

Where can I find tutorials for the IAR tools to use on the LPC2294 board?

Answer:

The relevant parts of the IAR CD that comes with the IAR-specific LPC2294 kit is available on our website at:http://www.phytec.com/zip/download/KPCM-023-IAR_CD contents.zip

phyCORE-LPC2294: Using IAR J-Link with Keil uVision3

Question:

How can the Keil EasyWEB demo be used with an IAR J-Link?

Answer:

Keil provides support for the J-Link with the update that can be downloaded at:  http://www.keil.com/update/sw/carm/2.32a

This update has added RDI support which allows you to connect the µVision3 Debugger to RDI-compliant devices. Detailed information is available in the Getting Started User's Guide — RDI Interface Driver.

 

phyCORE-LPC2294: IAR EWARM Tools

There are two version of the IAR EWARM tools on the CD included in phyCORE-LPC2294 Rapid Development Kit:
1) Evaluation version: Full functioning IDE, Debugger, Compiler, linker, etc... limited by 30 days.
2) KickStart: Compiler limited by 32K, no time limitation.

phyCORE-LPC2294: Internal Flash won't execute after JLink Disconnect

 

Problem:

I have the phyCORE-LPC2294 module and development board with IAR tools. Is there something special I need to do to get my application to run stand-alone? I can successfully download and run the blinky demo, and my own application, but neither will run without the j-link emulator. I have read, and followed the IAR “Getting Started” pdf and I am using the “internal FLASH” linker command file.

Solution:

There are several reasons that this behavior may be experienced resulting in several appropriate solutions:

First are you running the included workspace "phytec_pcm023" which should have been included on your IAR EWARM CD? This project includes several demos (blinky, debug, hello), all of which have internal and external Flash targets.  Ensure that the workspace running is the appropriate one.

 

Next a file "cstartup.s79" must be added to the project manually.  The path to this file is:

C:...\Program Files\IAR Systems\Embedded Workbench 4.0\ARM\src\lib\cstartup.s79

In IAR Embedded right click on the target "blinky - Internal Flash" and choose Add>>Add Files option. Browse to the appropriate path (Note that the default is to show .c files so change the file type option to show all files). Once this file is added to the project try to build and debug and once the Internal Flash is programmed disconnect the JLink and recycle power. The LED should continue to blink.

If it still isn't working then are you disconnecting the Jtag after a download by disconnecting the USB cable from the Jtag? or by actually disconnecting the Jlink by removing from the module at the Jtag pin header on module? If you just disconnect the USB cable while the program is running, it will not execute while the Jtag is still connected to module and the USB cable is unplugged.

Keep in mind that if you have a program in both internal and external flash, the program in external Flash will always execute upon a reset (not the code in internal flash). Be sure there is nothing in external Flash if you are trying to program and execute from internal Flash. The "Full Chip Erase" erases the external Flash and then programs external Flash. The "External Flash - Erase Only" demo erases the external Flash. Please run the "Erase Only" demo and then run the Internal Flash demo. Disconnect power, disconnect Jlink from module (remove ribbon cable from Jtag pin header), reconnect power.

 

 

phyCORE-LPC2294: VICVectAddr

 

Question:

I have a simple question in regards to the implementation of the interrupts. I have found the sample code written that comes with the installation:

long timeval;
/* Timer Counter 0 Interrupt executes each 10ms @ 60 MHz CPU Clock */
void tc0 (void) __irq {
++timeval;
T0IR = 1; // Clear interrupt flag
VICVectAddr = 0; // Acknowledge Interrupt
}

The question is: What value do we assign to VICVectAddr to acknowledge interrupt? ie if we have more that one interrupts namely, comRX and Timer? do we feed in "0" (VICVectAddr = 0) in any case?

Answer:

The VICVectAddr Register contains the jump address for the ISR after a hardware interrupt occurred. Shortly before ending the ISR this register should be written in order to execute a sort of End of Interrupt. Since Philips didn't specify which value one should write to this register it doesn't matter what you write. The only important thing is that the register is written to. It is possible to write "0" to this register, no matter from which ISR initiated the write access.

 

phyCORE-LPC2294: IAR Workbench and .HEX files

Question:

In IAR workbench I found lots of output format in the linker tab option. there are 3/4 types of .hex type file format ( such as- tektronix , mpds-i). But none of those are working with LPC2294.
What type of .hex file type do I need for LPC2294 so that I can install directly via flash utility?
How to generate that type of .hex if that is not included there?

Answer:

1) Open the phytec_pcm023 demo in IAR
2) Select the internal Flash target in the project workspace pull down menu.
3) In the main menu select "Project"->"Options"
4) In the "Category" window, select "Linker".
5) Select the "Output" tab.
6) Check "override default".
7) Name output file "blinky.hex" or whatever you want to call it.
8) Check "other" under "format".
9) Select "intel-extended" for output format, click OK.
10) Rebuild project.

11) Program the .hex file found here with Philips flash utility:
C:\Program Files\IAR Systems\Embedded Workbench 4.0\ARM\src\examples\Philips\LPC2294\phytec_pcm023\Internal Flash\Exe

Windows Embedded CE

phyCORE-LPC3250: "Error opening block device" using Linux ls comand

Bitte immer beachten, dass eine SD Karte zum LPC3250 Kit NICHT High Density sein darf (nur normale, 512 Mbyte sind ausreichend), ebenso muss die Karte mit FAT32 formattiert sein! FAT32 LBA führt zu Problemen (bei ls kommt dann Error opening block device).

 

Wenn Sie den Inhalt der Karte versehenlich gelöscht / zerstört haben oder die Karte verloren haben, finden Sie in der rechten Spalte unter Downloads / Software das Image für die SD Card.

phyCORE-LPC3180: Communicating to board via USB and RS-232

Question:

I need a driver that a Windows application can use to communicate with the LPC3180 over USB. Also, I was wondering if there is reference code for communicating with the LPC3180 over RS-232

Answer:

Unfortunately, only drivers for Linux and WinCE exist. We do not have code for communicating with LPC3180 over RS-232 but this interface is fairly easy to work with and shouldn’t be too hard to figure out by reading the hardware manual http://www.phytec.com/pdf/manuals/L-681e.pdf

 

Fragen und Antworten zu ähnlichen Produkten

Aktivierung von weiteren UARTS unter Linux

Im Kit Linux demo kernel sind nicht alle UARTs aktiviert. Das läßt sich jedoch ganz einfach nachholen, denn das BSP unterstützt alle 7 UARTs:

Nach dem Aufruf von "ptxdist kernelconfig" navigieren Sie bitte zu "System Type" / "LPC32XX chip components" / "Standard UARTs", schalten dort die gewünschten UARTs ein und bauen das BSP neu.

Is there any tool/software to program the PhyCORE-LPC3250 NOR flash?

Currently there are integrated tools for programming NOR Flash within IAR and KEIL tools.
See section 6 in the KEIL QuickStart manual:
http://www.phytec.com/pdf/manuals/L-717e.pdf
 
This could also be done with different tools but users would have to write their own programming algorithms.

phyCORE-LPC3250: Restoring the Kickstart and Stage 1 Loaders

Problem:
The Kickstart and Stage 1 Loaders have been erased and now I am unable to boot Linux or WinCE.

NOTE: Each phyCORE-LPC3250 SOM comes shipped with the Kickstart and Stage 1 Loaders pre-flashed to the board. Erasing the first blocks of NAND Flash, or flashing code using the IAR or Keil tools will overwrite the Kickstart & Stage 1 Loaders, requiring them to be restored via the process described below. Note that the Kickstart and Stage 1 Loaders are not required for IAR or Keil tools, but are required for Linux and WinCE.

Solution:
Restoring the Kickstart and Stage 1 Loaders can be done over serial using the LPC3250 serial loader tool. The tool allows you to upload a restore executable that runs by taking advantage of the UART5 processor boot mode.

To begin, make sure the boot jumper JP21 is closed on your phyCORE-LPC3250 Carrier Board. This will place the SOM into UART5 boot mode after reset. The "5" that is echoed to your serial terminal after a power-up or reset is indicative of the LPC3250 attempting a UART5 boot.

Next, download the latest Common Driver Library (CDL) which contains the LPC3250 serial loader tool from the following link: http://www.standardics.nxp.com/support/software/lpc32xx.cdl.drivers/zip/lpc32xx.cdl.zip

Extract the contents and navigate to the LPC3250 serial loader install executable and run it:
nxpmcu\software\csps\lpc32xx\tools\LPC3250 loader\LPC3250_Loader.exe

Now download the NXP "BSP howto" for the phyCORE-LPC3250 RDK and follow the instructions in section "4.3 Restoring the kickstart and stage 1 applications". See the following link for the PDF: http://www.standardics.nxp.com/support/software/lpc32xx.cdl.drivers/pdf/using.lpc32xx.csp.phytec.bsp.pdf

Download and use the following "restore.bin" when following section 4.3: http://www.phytec.com/zip/restore.bin

phyCORE-LPC3250: "Error opening block device" using Linux ls comand

Bitte immer beachten, dass eine SD Karte zum LPC3250 Kit NICHT High Density sein darf (nur normale, 512 Mbyte sind ausreichend), ebenso muss die Karte mit FAT32 formattiert sein! FAT32 LBA führt zu Problemen (bei ls kommt dann Error opening block device).

 

Wenn Sie den Inhalt der Karte versehenlich gelöscht / zerstört haben oder die Karte verloren haben, finden Sie in der rechten Spalte unter Downloads / Software das Image für die SD Card.

LPT-to-JTAG Interface for ARM (JA-001, JA-001-PXA)

Question:

 I have trouble communicating with a parallel port JTAG interface. What should I try?

 Answer:

 1.    The BIOS settings for the Parallel port should be one of the following: ECP, EPP or PS/2 Bi-directional.

 2.    In Windows XP: make sure to turn off the parallel port plug and play scanning "feature". This feature of Windows XP will interrupt parallel port communications between the PC and LPT-to-JTAG interface. This will yield what looks like sporatic communications. Turning of the autoscan "feature" may be turned off for the parallel port in the WINXP registry…….

 3.    The parallel cable connecting the PC parallel port and the LPT-to-JTAG interface MUST be IEEE1284 compliant. If the cable is not marked with the IEEE1284 text, then it is not compliant.

 4.    In Windows XP/2000, the parallel port dialog checkbox entitled "Enable Legacy Plug and Play" should be checked. This setting is located in the Control Panel à System à Hardware à Device Manager à Ports à Printer Port (LPTx) dialog. You must reboot your PC after this setting to take effect.

 5.    Make sure to turn off any applications which may be trying to access the printer port (such as a Print Manager) before running software to debug with LPT-to-JTAG interface.

 6.    Also beware that some laptops, in particular some of the IBM Thinkpads, do not implement a standard parallel port even though they claim they do. If you encounter this problem on a laptop and have access to a desktop machine, it is best to try the experiment on the desktop in order to rule out other issues.

Wie groß ist der Performance-Unterschied bei Bestückung mit SLOW oder FAST SRAMs?

Bei Bestückung mit Fast SRAMs kann man bei Vollausbau ( 4* SRAM + notwendiges CPLD) mit einem Wait State die Speicher ansprechen. D.h Ansprechzeiten von ca. 33ns.
Bei einer Bestückung ohne CPLD (also max 2*SRAM) können die Zugriffszeiten nochmals auf 0 Waitstates reduziert werden. (16ns Zugriffszeit)
Im Bereich der SLOW-SRAMs macht das CPLD keinen großen Unterschied, da hier mit einer Laufzeit von ca. 6-8ns fürs CPLD und einer minimalen Zugriffzeit des SRAM von 55ns eine minimlae Zeit von 64ns für den Zugriff einzustellen wäre (3 Waitstat -> ca. 66ns). Dabei ist dann kein Waitstate einzusparen, wenn das CPLD nicht auf dem Board bestückt ist.

Zum CPLD gilt es noch zu sagen, dass dieses bestückt werden muss, sobald eine zweite Speicherbank auf dem Modul bestückt wird, egal ob Flash order RAM. Nur so ist es möglich, den gesamten Speicher mit nur zwei CS-Signalen des Prozessors anzusprechen. Werden für FAST SRAM 0 Waitstate gefordert, kann nur jeweis eine Speicherbank bestückt werden.

Strombedarf des LPC2294

Fragenkatalog:

 Nach Durchsicht des HW-Manuals haben wir versucht, die Stromaufnahme zu ermitteln:
- im laufenden Betrieb: VCC1 3.3 V -> /300 mA typical
- im Sleep-Mode: keine Angabe gefunden.

Fragen:
1.1)      Die Stromaufnahme im laufenden Betrieb :
            -> bedeutet 300 mA typical den vollen Betrieb aller Komponenten:
               was ist angeschlossen bzw. aktiv: 4x SRAM, 4 x Flash, Ethernet-Komponenten, 2x CAN-Bus ?
            -> welche CPU-Frequenz liegt dem zugrunde?
            -> wie viel Stromreduktion können wir bei teilweiser Deaktivierung von SRAM und  Flash erreichen ?

1.2)      Ethernet-Komponenten:
            -> welche Stromaufnahme?
            -> lassen sich diese komplett trennen vom System ?
            -> alternativ: können diese per SW diabled werden:
                wie ist dann die Stromaufnahme ?
           
1.3)      Wie ist die Stromaufnahme im Sleep-Mode
            -> bei welcher Bestückung / welchen Bausteinen (SRAM/Flash) wie hoch ?

 

Antworten:

> Fragen:
> 1.1)      Die Stromaufnahme im laufenden Betrieb :
>             -> bedeutet 300 mA typical den vollen Betrieb aller Komponenten:
>                was ist angeschlossen bzw. aktiv: 4x SRAM, 4 x Flash,
> Ethernet-Komponenten, 2x CAN-Bus ?
>             -> welche CPU-Frequenz liegt dem zugrunde?
>             -> wie viel Stromreduktion können wir bei teilweiser
> Deaktivierung von SRAM und  Flash erreichen ?

Dies Angabe bezieht sich auf das Modul mit Vollausbau, d.h. 8MByte Slow SRam (min. 55ns Zugriffszeit) , 16MByte Flash, 1K EEPROM, RTC, Ethernet, CAN und der Ausführung des Bootloaders uboot mit RAM-Test, Flashtest, und Ethernettest in sequentieller Art. Alle Clocks der notwendigen Peripherie waren damit eingeschaltet. Was weiterhin zu beachten ist, ist dass bei dieser Bestückung ein SLOW SRAM eingesetzt wurde. Dieses hat einen wesentlich niedrigeren Stromverbrauch als die herkömmlichen Fast SRams während des Betriebes als auch während der Standy-Phase.

Die Stromaufnahme im Power Down Mode wurde nicht gemessen, daher auch keine Angaben. Diese sind natürlich prinzipiell aus der Summe der Ströme der extern angeschlossenen Devices im Power Down und der Stromaufnahme des Controllers zu  ermitteln. Werde mal versuchen, dies zu tun für oben genannte Bestückung:

Folgende Stromaufnahmen habe ich bei dem Board nochmals mit dem folgenden Softwarezustand gemessen: Uboot 1.1.4 läuft und hält am Prompt:

Stromaufnahme normal :                ca. 270mA ohne Aktivität
Stromaufnahme bei Flash löschen:      ca. 300mA
Stromaufnahme RAM-Test:            ca. 270mA           

Stromaufnahme IDLE :             ca. 240mA wobei hier die Peripheral Clocks noch aktiv sind. z.B UART, CAN, SPI, I2C, LPC
Stromaufnahme Power Down:         ca. 234mA

Ein Board mit FAST SRAM hat an dieser Stelle bei einer Bestückung mit 1MByte FAST SRAM und 2MBYTE Flash eine Stromaufnahme am Prompt einer Applikation von minimum 330mA. Kommen jetzt noch Aktionen hinzu wie z.B Flash löschen, so steigt die Aufnahme des Stromes bis auf ca. 380mA an. Die ist mit der Stromaufnahme des FAST SRAM zu begründen, das hier wesentlich höher liegt als das SLOW SRAM.

 
Die genannten Messwerte entstanden bei 60 MHz.


>
> 1.2)      Ethernet-Komponenten:
>             -> welche Stromaufnahme?

Stromaufnahme Ethernet kann nur durch Vergleich zweier Boards einmal mit bzw. einmal ohne in gleicher Bestückung erfolgen. Habe ich zwei dieser Boards, kann ich mal nachmessen... Leider habe ich keine zwei Boards, die gleiche Speicherbestückung besitzen und nur in Ethernet sich unterscheiden. Damti kann ich diese Messung nicht durchführen


>             -> lassen sich diese komplett trennen vom System ?

Nein. Ist der Ethernetcontroller bestückt, so ist er direkt mit der Betriebsspannung verbunden. Ein Trennen ist nicht möglich.

>             -> alternativ: können diese per SW diabled werden:
>                 wie ist dann die Stromaufnahme ?

Ein Abschalten der PHY als auch des MII Interfaces des LAN91C111 ist möglich. Eine gesonderte Stromaufnahme wurde hier aber noch nicht gemessen, da dies einen etwas höheren Aufwand bedeutet. Werde versuchen, diese Messungen mal nachzuholen...

Leider ist es mir nicht gelungen die Bits in dem Controller zu beschreiben, da die gar nicht so einfach mit den mir zu Verfügung stehenden Softwaremitteln ist, aber ich konnte einen Unterschied zwischen initialisiertem Ethernet Interface und nicht initialisiertem Interface feststellen. Der Unterschied hier liegt im Bereich von ca. 30mA

>            
> 1.3)      Wie ist die Stromaufnahme im Sleep-Mode
>             -> bei welcher Bestückung / welchen Bausteinen
> (SRAM/Flash) wie hoch ?

Bestückung siehe oben!
Stromaufnahme siehe oben!

Eine weitere Option des Modus ist es, die RAM-Spannung von der Betriebsspannung des Systems zu trennen und separat von außen zuzuführen. Damit hat man die Möglichkeit das SRAM (nur sinnvoll mit SLOW SRAMs) während Power Off des Moduls zu puffern. Damit reduziert sich dann die Stromaufnahme währenddessen auf ein Minimum von ca. 20-50µA je nach bestücktem Slow SRAM.

phyCORE-LPC2294: Issues with P016 as EXTINT0

Question:

I am unable to use Port P016 pin as External Internal 0.

Answer:

Port P016 is not by default available as a GPIO. By default, jumper J501 connects this port to the Ethernet Controller. For additional information regarding jumper settings for J501, please refer to the Hardware Manual under Section 3 

 

phyCORE-LPC2294: JTAG error message

Question:

JTAG interface reports “Couldn’t stop ARM device” when I upload the blinky.hex file.

Answer:

There are several things that you should check to assure proper use of the device:

Make sure that the external flash is erased before programming it to iFlash. Unplug the USB cable from the ULink and restart uVision. Go to http://www.keil.com/support/docs/2763.htm to make sure you have the most recent ULink drivers. If you are using an old Phytec Spectrum CD, go to our website to obtain the latest blinky.hex file available in the section “Documents and Demos” http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM7-LPC229x.html#documentation.

 

phyCORE-LPC2294: Demo updates

Question:

I have a copy of the old Phytec Spectrum CD. Where can I get updates?

Answer:

Please refer to our website to obtain the latest demos available in the section “Documents and Demos” http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM7-LPC229x.html#documentation. Also, check for the latest version of the uVision tools at http://www.keil.com/demo/eval/arm.htm

phyCORE-LPC2294: GPIO registers

Question:

Where can I find documentation and descriptions for IOPIN0, IPSET0, IODIR0, IOPIN1 and IOSET1?

Answer:

Those are GPIO registers. Please refer to Section 9 of the User Manual at http://www.phytec.com/pdf/datasheets/LPC2xxx_UM_2007.pdf

 

phyCORE-LPC2294: HyperTerminal issue

Question:

I am unable to produce output at the HyperTerminal for the Hello World demo.

Answer:

Use the upper DB-9 female connector on the Carrier Board, which is UART1 and no longer UART2. Also, in serial.c, change the PLLCFG_Val EQU value from 24 to 25.

 

phyCORE-LPC2294: XFlash erase

Question:

I am unable to get my board to communicate with the JTAG/ULINK for XFlash download/erase.

Answer:

Check if there is anything in the external flash that modifies the LPC2294 controller configuration in a way that does not allow any JTAG communication. If you have troubles erasing external Flash, force the chip into ISP mode by using BOOT and RESET push button sequence. Press both buttons; release the reset button and then the boot button a few seconds later. After putting the module into ISP mode, click on the ‘LOAD’ icon or Flash/Erase in uVision3 with the XFLash target being active.        

phyCORE-LPC2294: Pin layout

Question:

Where can I find pin layouts of the header connected to the CPLD?

Answer:

A component placement diagram of our phyCORE-LPC2294 SBC module can be found in Section 18 of the corresponding Hardware Manual.

phyCORE-LPC2294: Using DTR/RTS signals

Question:

Which jumper links to configure for the LPC2000 flash utility to use the DTR/RTS signals for the reset and boot loader operation on the phyCORE-LPC2294 mounted on a Phytec HD200 Carrier Board?

Answer:

Using the DTR/RTS signals for reset and boot loader operation is not supported on our Carrier Boards. PHYTEC has FlashTools software that can use these CTS/DSR signals for starting the boot mode. Unfortunately NXP/Philips is using different signals for their ISP loader and Flash Utility.

 

phyCORE-LPC2294: Ethernet errors

Question:

The board is not working for the LAN91C111 Ethernet device. I have mounted the LPC2294 on my own development board as oppose to the HD200 Carrier Board.

Answer:

There is an Ethernet limitation to the LPC2294 which stems from the Carrier Board and is only present when connecting at 100Mbit speed. At this baud rate, the auto-negotiation phase will not correctly be finished so there will be no error free transmission. However, the problem will not occur at 10Mbit speed. This limitation is caused by the length of the signal traces for the Ethernet lines, as well as the way the signal lines are routed. The HD200 board works well with many other phyCORE modules which only support 10Mbits/s speed, specifically modules developed prior to the LPC2294. Unfortunately, the LPC2294 has inherited this limitation. The operation at 100Mbits/s is possible with shorter signal traces than on our development board. If you design your own carrier board, be sure that these signal traces are straight and as short as possible.

 

phyCORE-LPC2294: Loading code on iFlash vs. xFlash

Question:

When I download the blinky demo onto the board, I receive an error message saying “Cannot communicate with device”.

Answer:

Check if you downloaded the code into internal and/or external Flash. There are different targets within each of the demo examples. You may have something stuck in iFlash that prevents another program in xFlash from booting. I suggest you bring the system into bootloader mode by pushing Reset and Boot push-buttons simultaneously

 

phyCORE-LPC2294: Development tools compatibility

Question:

Is the LPC2294 compatible with ARM Multi-ICE RealView development/debug system? The ARM Multi-ICE uses a 20 pin JTAG interface and CodeWarrior/AXD for code development and debug interface

Answer:

Yes. The ARM Multi-ICE is in the list of development tools supported from Philips for the LPC2294 processor. There is a 20pin JTAG interface on the board so it should be compatible with these tools (see Chapter 25 in the User Manual at http://www.phytec.com/pdf/datasheets/LPC2xxx_UM_2007.pdf ).

 

phyCORE-LPC2294: VICVectAddr

Question:

I noticed in a sample code that came with the installation of the LPC2294 assigned VICVectAddr = 0. What value do we need to assign to acknowledge an interrupt?

Answer:

<font face="Times New Roman" size="3">The VICVectAddr Register contains the jump address for the ISR after a hardware interrupt occurred. Shortly before ending the ISR this register should be written in order to execute a sort of End of Interrupt. Since Philips didn't specify which value one should write to this register it doesn't matter what you write. The only important thing is that the register is being written. It is possible to write "0" to this register, no matter from which ISR initiated the write access.</font>

phyCORE-LPC2294: Measuring power consumption

Question:

I attempt to measure the power consumption of the LPC2294 processor, but I have not been able to find a location where I can isolate the 3.3V and 1.8V inputs and attach an ammeter to measure it.

Answer:

Please see section 13 in the phyCORE-LPC2294 Hardware Manual for power consumption values of the SBC module.http://www.phytec.com/pdf/manuals/L-658e.pdf

With some effort and a few module modifications it is possible to measure the 1.8V. You would have to desolder pins #1 and #3 on Q600 and lift these pins off the solder pad. You then measure the current via J618. In order to figure out the current draw of the 3.3V you would simply take the 1.8V out of the combined consumption of the SBC module.

Alternative to Philips Flash Utility

Question:

Is there a way to erase the flash without using the Philips flash utility? I am using the KEIL software development tool.

Answer:

You can erase both on-chip and external/on-board Flash from within Keil's uV3. Section 3.3 of the QuickStart tells you about the required Flash algorithms.

 

phyCORE-LPC2294: Clock Frequencies

Question:

What is the clock frequency of the on-chip oscillator and the external crystal?

Answer:

The quartz frequency of the external clock source is 10 MHz. The CPU runs at 60 MHz internal speed. We use a Jauch quartz crystal from their JXE75 series. The multiplication is done inside the LPC2294 controller by configuring the PLL registers. For more information, please refer to Section 14 of the Hardware Manual.

phyCORE-LPC2294: GPIO Port for SPIO slave chip select

Question:

I need to access the EEPROM of the SPI bus but I do not know which GPIO port and pin are the SPI 0 slave chip select?  The manual says:
"P10" (which I take to mean port 1, bit 0) and the schematic says
"P010" (which I take to mean port 0, bit 10).

Answer:

SPI0 is used on the phyCORE module and per default master mode is selected,
see settings for J619. And the chip select signal from P010 connects to the
on-board EEPROM as /PCS0. Please refer to Section 3 of the Hardware Manual for more information.http://www.phytec.com/pdf/manuals/L-658e.pdf

phyCORE-LPC2294: Ethernet default settings

Question:

Do I have to configure any jumpers on the LPC2294 to use the Ethernet port?

Answer:

There is no jumper (re)configuration required to use Ethernet on this board.

phyCORE-LPC2294: Single-chip

Question:

How do I set up the module to work in single-chip?

Answer:

The module is configured to use the xFLASH at /CS0 as boot device. You can change that to iFLASH by removing resistor R203 on the module. Please refer to Section 4.1 in the Hardware Manual.

 

 

phyCORE-LPC2294: Ethernet Controller

Question:

Where can I get the card that mounts with connector RJ45 on LAN91C111 Ethernet Controller?

Answer:

Section 17 of the Hardware Manual describes the details on the Ethernet interface. Our Rapid Development Kit for the phyCORE-LPC2294 includes both the HD200 Carrier Board and the EAD-003 Ethernet add-on module. Please note that you need the latest version of the PHYTEC Carrier Board HD200 with part number PCM-997-V3 and PCB# 1179.6 in order to get the full 100MBit/s speed through Ethernet. Older versions of this Carrier Board had a limitation to only 10 MBit/s due to some signal routing issues.

 

phyCORE-LPC2294: CTS/RTS lines

Question:

I need to connect to the CTS/RTS lines on the DB-9 socket P1B. JP3 and JP6.

Answer:

There are no RS-232 transceivers for these additional modem control signals. Only Rx and Tx go through an on-board RS-232 transceiver. If you wish to use these signals you need to route them through such an transceiver somewhere on your carrier board or an expansion board. You should NOT attempt to connect these jumpers and use these signals without proper level conversion.

phyCORE-LPC2294: EINT0 Interrupt

Question:

Do you have any code showing how to set up the EINT0 interrupt for the ethernet controller for the LPC2294?

Answer:

LPC2294 fails to write 0x0d to EXTMODE register even when VPBDIV=0 as advised in the device errata http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/errata.lpc2294.pdf The EXTMODE register prior to write was 0x0f and gets 0x00 just after attempting to set to 0x0d. Since this issue is related to the EXTINT.1 Errata, the same workaround applies with an additional step. Before writing to the EXTMODE and EXTPOLAR registers:

    • Write 0x0 to VPBDIV
    • Then write the same value to VPBDIV
    • Then write the desired value to EXTMODE or EXTPOLAR register.
    • Restore the VPBDIV to the previously saved value or simply write to the register again with the desired value.

While testing this in a debugger environment, please don't single-step through these steps. A breakpoint could be placed after Step 4 and you would see the EXTMODE and EXTPOLAR registers reflecting the correct values.

 

phyCORE-LPC2294: SPI and Ethernet interfaces

Question:

I need to use both SPI interfaces along with the Ethernet controller in my application. If I remove jumpers J611-J614, will I be able to use the Ethernet interface?

Answer:

The MAC address is pre-programmed into the EEPROM. You should be able to configure the Ethernet controller to retrieve the specific configuration data elsewhere. This would likely cause a software modification.

 

phyCORE-LPC2294: Connect to Chip Select

Question:

When we connect the chip select signal to SSEL0 (P0.20) and SSEL1 (P0.7), the signals gets grounded. Are these ports being used for some other purposes?

Answer:

According to the circuit diagrams and the user manual of the LPC 2294, SSEL1 (at P0.20) and SSEL0 (at P0.7) is used for SPI-Master/Slave Selection. There are two jumpers which may ground signals P0.20 and P0.7. However, the default settings of jumper J620 (which connects to signal P0.20/SSEL1) and jumper J619 (which connects to signal P0.7/SSEL0) is open (see section 3.22 in the phyCORE-LPC2294 Hardware Manual L-658: http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM7-LPC229x.html#documentation ). Hence the signal level at both pins should be 3.3V given the fact that 100kOhm pull up resistors at R621 and R622 are connected to P0.20 and P0.7. Therefore, the signals should not be grounded. There are no other connections of these signals to any other components on the phyCORE module.

It is possible that you could have changed the default settings of the signal direction, given that P0.20 is a multiplexed pin sharing functions with MAT1.3/SSEL1/EINT3 and the same with P0.7 with SSEL0/PWM2/EINT2. In order to use these pins as SPI Master/Slave select signals, you need to configure the PINSEL0 register on the LPC2294 controller. For more details, please refer to the LPC 2294 User Manual Section 6.1)

 

phyCORE-LPC2294: CAN interface

Question:

I am unable to establish CAN communication.

Answer:

You are using the CAN transceiver that is on the SBC module. U605 for CAN channel #1 and U606 for CAN channel #2. CAN signals with the CAN_High and CAN_LOW levels are routed to the Molex connectors and from there to JP31 and JP32 on the PHYTEC Carrier Board HD200. Setting both jumpers to position 2+3 (default) routes the CAN signal to DB-9 connector P2A (bottom connector on the dual stacked device). Figure 19 in the Hardware Manual shows the default jumper settings for the HD200 board in combination with the LPC2294 SBC module. The LPC2294 controller operates with a 10 MHz crystal. The CPU will run at 60 MHz.

 

phyCORE-LPC2294: Erase Memory

Question:

I noticed that the Reset pin of the Boot Flash memory should be connected to 12V in order to temporary unprotect the sectors to be erased/programmed. Can you explain the configuration used in your schematic that would allow one to erase/program the memory?

Answer:

The connection of the Reset pin to the 12V is a feature of the Flash-device. Using the unlock commands of the flash will allow you to unprotect the flash for write/erase access.

 

phyCORE-LPC2294: JTAG error

Question:

I have an error message “JTAG Device Chain Error” when downloading the blinky demo into xFLASH.

Answer:

Make sure you have the latest version of the CARM tools from http://www.keil.com/update/arm.asp , install MDK-ARM Version 3.15b and download the latest blinky demo at http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM7-LPC229x.html#documentation

 

phyCORE-LPC2294: Jumper Settings

Question:

What are the default settings for J600 and J601?

Answer:

Jumpers J600 and J601 are closed at position 1+2 as default configuration. See section 3.13 in the phyCORE-LPC2294 hardware manual. See figure 6 or figure 35 for Jumper location. The side that has only a small black square is where pin #1 is. The "solid" line is pin#3. For putting the jumper to position 2+3 you would need to move them "down" on pad.

 

phyCORE-LPC2294: Using address and data lines as GPIO

Question:

Since the LPC2294 does not have an external memory bus, what do I do to use the address and data lines as GPIO?

Answer:

Remove resistor R204 to select internal flash and configure PINSEL2 register bit 27:25 so that the address lines can be used as IOs. R203 is not to depopulate because it is not placed in respect of a 32bit external data bus. Depopulating of the external memory is not necessary because the memory will be inactive if the CS signals are not active. Ensure that the CS signal lines are inactive for all populated external devices. If this is not possible the external devices have to be removed.

phyCORE-LPC2294: Stand-alone run

Question:

How do I get my application to run stand-alone?

Answer:

<font face="Times New Roman" size="3">First, be sure that there is nothing in external flash if you are trying to program and execute from internal flash. If you have a program in both internal and external flash, the program in external flash will always execute upon a reset (not the code in internal flash). To erase the external flash, select the "External Flash - Erase Only" from the target pull down menu (Refer to Section 3.1.1 in the QuickStart ). Next, disable External Flash from booting by modifying the system startup configuration. This can be done by removing some resistors on the module. Please refer to Section 4.1 on the Hardware Manual available at the same link provided.</font>

phyCORE-LPC2294: Configuring target settings

Question:

I am not able to run new projects in the internal RAM.

Answer:

The configuration options for internal and external RAM are created manually; they are not default created when making a new project. This has to be configured manually. Begin by making a copy of the provided sample demo ‘Blinky’ and use it as a basis for your own code to eliminate going through the project settings. For more information on configuring the target settings, please refer to the QuickStart in Section 3.

 

phyCORE-LPC2294: Board Connector part number

Question:

I am trying to create a daughter card to mate with the LPC2294 X2 Expansion Bus connecter and I was wondering where can I get specific part number of LPC2294 board connectors?

Answer:

The Molex connector that mates with X2 on the phyCORE HD200 Carrier Board for phyCORE-LPC2294 has the following part numbers:

    • PHYTEC internal part number: VM042
    • Molex part number: 52760-1679
phyCORE-LPC2294: SPI controller

Question:

I am trying to use SPI0 bus to drive ADS1217 chip and I was wondering why is pin MISO0 high when I use a separate /CS to drive the ADS1217?

Answer:

If you wish to directly connect the SPI ADC to the controller ports, you need to add pull up resistors. An external pull up is required at the corresponding port while using the pull ups on the Phytec SBC module for the other 3 lines if the /PCS0 line is separated.

phyCORE-LPC2294: Pull up resistors and jumpers on SPI

Question:

Do I have to add pull up resistors on signals P04 and P06 when I remove jumpers J612, J613 and J614?

Answer:

If jumpers that connect the controller pins to the SPI EEPROM are removed, pull up resistors are no longer effective for signals P04 and P06. The pull ups are not on the controller port side. The function of the pull up resistors is to ensure a proper high level with 3.3V on the SPI bus. This also improves the slew rate of the ports.

 

phyCORE-LPC2294: Pin mapping

Question:

Where can I find information about the mapping between the two 50-pin and the 54-row patch area?

Answer:

Please refer to the Hardware Manual under Section 16.3.11 

phyCORE-LPC2294: Bypassing SPI EEPROM

Question:

I require both SPI ports for my application as well as the Ethernet Controller in my application. Is there a way which I can bypass SPI EEPROM (U607)?

Answer:

You can remove SMP jumpers/resistors J611, J612, J613, and J614 on the phyCORE SBC module. This will disconnect the EEPROM U607 from the SPI bus. You can access the signals with the Port Pin label and number at the Molex connectors. For more information regarding onboard EEPROM U607, please refer to the Hardware Manual under Section 3.18

 

phyCORE-LPC2294: ETM-port

Question:

I have trouble getting the trace signals from the phyCORE-LPC2294. There are bootstrapping pins to enable or disable ETM. Is the P1.20/Tracesync pin pulled LOW during reset to enable ETM? This pin has an internal pull-up, so if there is no external pull-down then ETM will be disabled. Similarly, is P1.26/RTCK pulled LOW at reset to enable the JTAG debug pins?

Answer:

 

Normally the JTAG Port on the phyCORE-LPC2294 is enabled, but the ETM-port is disabled, because the resistor for enabling the ETM-Interface is not populated on the phyCORE board. You need to enable the ETM Trace port by switching on/off the Dip Switches S1 of the PTA-002. The special settings for this are described on the schematic of the PTA-002.

phyCORE-LPC229x: Hardware port layouts

Question:

There are four DB9 connectors on the board. Which two are the serial ports and which two are the CAN bus ports?

Answer:

 

Please refer to Section 16.3 in the Hardware Manual:  www.phytec.com

phyCORE-LPC229x: Flash Organization

Question:

What is the flash configuration?

Answer:

Flash access is always in a 16-bit * 2 fashion. Or in other words you want to use WORD mode rather than BYTE mode.

phyCORE-LPC2294: Porting uCLinux 2.6

Question:

Has the LPC2294 been made for porting with uCLinux 2.6?

Answer:

Please refer to the uCLinux pdf and zip file on our website in the “RTOSes” section

http://www.phytec.com/products/sbc/ARM-XScale/phyCORE-ARM7-LPC229x.html#RTOS

 

phyCORE-LPC2294: IAR tutorial

Question:

Where can I find tutorials for the IAR tools to use on the LPC2294 board?

Answer:

The relevant parts of the IAR CD that comes with the IAR-specific LPC2294 kit is available on our website at:http://www.phytec.com/zip/download/KPCM-023-IAR_CD contents.zip

phyCORE-LPC2294: MICTOR connector

Question:

What is the part number of the MICTOR connector?

Answer:

AMP 2-767004-2

phyCORE-LPC2294: Test Code for Maxim DS-2401

Question:

I attached a Maxim to the LPC2294 Carrier Board and would like to request any test code available to test this device.

Answer:

We do not have any demo code for the silicon serial number chip and access via GPIO1 on the LPC2294 controller. The only test code we have is for 8051 and C166 architecture

phyCORE-LPC2294: Using Second Serial Interface P1B

 

Question:

When developing with the phyCORE-LPC2294 and HD 200 Dev. board and use the second serial interface P1B arises. Is it correct to close JP3 and JP6 for RTS/CTS or is there another way to enable these lines? Should JP1 and JP8 be closed for TxD1 and RxD1?

Answer:

There are no RS-232 transceivers for these additional modem control signals. Only Rx and Tx go through an on-board RS-232 transceiver. If you wish to use these signals you need to route them through such an transceiver somewhere on your carrier board or an expansion board. You should NOT attempt to connect these jumpers and use these signals without proper level conversion.

 

phyCORE-LPC2294: Processor Revisions

 

In general there are three different revisions existing for the LPC2294. 

Rev A (LPC2294) is the initial device release and has the top markings as:

  LPC2294xxx

  xxxxxxx

  xxYYWWR

Rev B (LPC2294/00) is the second release, which typically has the following top markings:

   LPC2294xxx  

   /00

   xxxxxxx

   xxYYWWR

Additional information on the revision functional deviations can be found in the errata sheet:

 

http://www.phytec.com/pdf/manuals/LPC2294_errata.pdf

The following part numbers have been used on the Phytec modules:

    • LPC2294JBD144
    • LPC2294HBD144/00
    • LPC2294HBD144/01

J = temperature range of -40/+105 (Rev A) 

H = temperature range of -40/+125

/00 = Revision B

/01 = Revision C

Currently the LPC2294/00 is the part number that is currently populated on our PCM-023 modules.

 

phyCORE-LPC2294: Pull-up Resistor on Address and Data Bus

Question:

Why does the pC-LPC2294 hardware manual recommend using a 100k pull-up resistor on address and data bus even though there is already a pull-up on-chip?

Answer:

This is recommended because the on-chip pull-ups tend to be too weak, consequently it is recommended to use a 100k pull-up against VCC.  This is indicated on page 83 of the hardware manual, which can be found at:

http://www.phytec.com/pdf/manuals/L-658e.pdf

 

phyCORE-LPC2294: Using IAR J-Link with Keil uVision3

Question:

How can the Keil EasyWEB demo be used with an IAR J-Link?

Answer:

Keil provides support for the J-Link with the update that can be downloaded at:  http://www.keil.com/update/sw/carm/2.32a

This update has added RDI support which allows you to connect the µVision3 Debugger to RDI-compliant devices. Detailed information is available in the Getting Started User's Guide — RDI Interface Driver.

 

phyCORE-LPC2294: Hardware Design Problem

Question:

There is an apparent problem with the hardware design of your PCM-023-SK-2294.  The problem is with the compatibility of the RESET I/O signal, pin 15, of the JLINK-KS device and the reset circuitry of the PCM-023-SK-2294. We want to use the Hardware Reset option when debugging, but we can’t because of an apparent design flaw.  Besides this problem, just having the JLINK-KS device connected appears to cause the supervisory chip to sink too much current when it is asserting the /RESET signal.  Please refer to the schematic named phyCORE-LPC2292/2294 that comes with the IAR rapid development kits.

I tracked down a problem with the JLINK-KS not being able to reset the Phytec board.  The reset I/O pin of the JLINK-KS, see pin 15 http://www.segger.com/jlink.html, is connected to pin 15, JTAG_SRST, on X701 and connects directly to the Phytec board’s /RESET net (see sheet 7 of the Phytec schematic).  The /RESET net is driven by the TI supervisory chip, U601 pin 5 (/RES) (see sheet 6 of the Phytec schematic). The problem is that the /RES pin is not an open drain output on the TI part, it is a totem pole output (TI makes a special point of stating this in there data sheet so it isn’t a misinterpretation on my part: “† Outputs are totem-pole configuration. External pullup or pulldown resistors are not required”.

The JLINK-KS isn’t able to pull the /RESET line low (and we probably should be glad for that as it would mean we are shorting out the /RES output while it is driving high), and it only goes down to about 1.8 V when we choose Hardware Reset in the options for Reset Setup in the Jlink/Jtrace Category of the IAR EWARM. This creates a problem as we wish to perform a hardware reset when restarting the application.

Answer:

There was a redesign on this board and we now ship PCB revision 1231.1. This redesign should address these issues. See the attached redesign revision note.


Revision history for phyCORE-LPC2292
========================================

Part number:      PCM-023

Project start:    20.04.2004

Project engineer:       Dipl.-Ing.(FH) Arnd Beuscher (A.B.)
Participating engineer:      Dipl.-Ing.(FH) E.Schumann  (E.S.)
=============================================================================

20.04.2004        1231.0-001    Start QA (spec) phyCORE-LPC2292
20.04.2004        1231.0-001    Completion QA (spec) (A.B)

20.04.2004        1231.0-001    Start circuit diagram (A.B)
20.04.2004        1231.0-001    Completion circuit diagram

21.07.2005        1231.1-001    Start Redesign (A.B.)
                                - Diode D603 added in /RESET path
                                - J622 and Q601 added for generating RESET based
                on /RESET signal due to Debugger issues

 

phyCORE-LPC2294: Disable CAN: Jumper Configuration

<font size="4">Question:</font>

What are the default settings for J600 and J601 on the phyCORE-ARM7/LPC229x (part # PCM-023)? I would like to disable the CAN interfaces to do a self test, but it seems that the transceivers are always enabled.

<font size="4">Answer:</font>

Jumpers J600 and J601 configure CAN signals. Per default, CAN is active and the Jumpers are closed at position 1+2. See section 3.13 in the phyCORE-LPC2294 hardware manual:

<font color="#006699">http://www.phytec.com/manuals/L-658e.pdf</font>

Setting the jumper to position 2+ 3 disables CAN. Refer to figure 6 or figure 35 for Jumper location. The side with the small black square locates pin #1.

phyCORE-LPC2294: Disable External Memory

Question:

We plan to use this microcontroller in single-chip mode (w/o external RAM and Flash). Can you please give me some hints on how to set-up the phyCORE module to work in single-chip? I think I need to change some jumpers/resistors, but can't find how-to instructions.

Answer:

The phyCORE-LPC2294 is configured to use the external Flash at /CS0 as boot device. You can change that to internal Flash by removing resistor R203 on the phyCORE module. See section 4.1 "System Startup Configuration" in the Hardware Manual:
http://www.phytec.com/manuals/L-658e.pdf

Please see the phyCORE-LPC2294 schematics and a component placement diagram showing the location of that resistor.

phyCORE-LPC2294: CAN Optical Isolation

 

Question:

Are CAN signals optically-isolated on the phyCORE-ARM7/LPC2294 (PCM-023-xxx)?

Answer:

Section 3.14 of the phyCORE-ARM7/LPC2294 Hardware Manual describes configuration of CAN signal isolation:
http://www.phytec.com/manuals/L-658e.pdf

Default configuration of the phyCORE-LPC2294 is without optical isolation of CAN signals generated by the CAN transceivers at U605 and U606. To configure EXTERNAL (off-module) optical isolation removal of these two CAN transceivers, as well as closing of solder jumpers at J602, J604 and J605 on the phyCORE module is required.

In addition, some removable Jumpers on the phyCORE HD200 Development Board must be set. This is described in section 15.3.6, paragraph/scenario #2 or #3. This depends on whether a CAN supply voltage is supplied through the CAN bus cable (scenario #3)) or not. If there is no CAN supply voltage from the bus you can also use the supply of the Development Board (scenario #2). In this later case you wouldn't have galvanic separation since you are using the same ground potential for the module logic and the CAN optocouplers/transceivers. Switching between scenario #2 and #3 is easy. It just requires opening/closing two or three removable jumpers on the Development Board.

 

phyCORE-LPC2294: CAN Examples

CAN example programs for the LPC2000 series devices incl. LPC2294 can be
found on the following URL:
http://www.keil.com/download/docs/291.asp
Simply download the .ZIP file linked there.

Also, there is a great deal of CAN related information and examples at:
http://www.ESAcademy.com

phyCORE-LPC2294: IAR EWARM Tools

There are two version of the IAR EWARM tools on the CD included in phyCORE-LPC2294 Rapid Development Kit:
1) Evaluation version: Full functioning IDE, Debugger, Compiler, linker, etc... limited by 30 days.
2) KickStart: Compiler limited by 32K, no time limitation.

phyCORE-LPC2294: Interfacing Memory to CS3

 

Problem:

I am interfacing a 16-bit memory device using Chip Select CS3 at the memory bank 0x8300 0000. We found that chip select is becoming active for every instruction executed. The chip select CS3 is also becoming active when the instructions are accessing the memory bank. We are monitoring the CS3 on the phyCORE Development board at the pin F-29. We are using Ashling path finder for debugging.

Solution:

The chip selects seem to misbehave while using the Ashling's path-finder. If you run the code by downloading through Philips Flash Utility the chip selects will work fine.

 

phyCORE-LPC2294: Internal Flash won't execute after JLink Disconnect

 

Problem:

I have the phyCORE-LPC2294 module and development board with IAR tools. Is there something special I need to do to get my application to run stand-alone? I can successfully download and run the blinky demo, and my own application, but neither will run without the j-link emulator. I have read, and followed the IAR “Getting Started” pdf and I am using the “internal FLASH” linker command file.

Solution:

There are several reasons that this behavior may be experienced resulting in several appropriate solutions:

First are you running the included workspace "phytec_pcm023" which should have been included on your IAR EWARM CD? This project includes several demos (blinky, debug, hello), all of which have internal and external Flash targets.  Ensure that the workspace running is the appropriate one.

 

Next a file "cstartup.s79" must be added to the project manually.  The path to this file is:

C:...\Program Files\IAR Systems\Embedded Workbench 4.0\ARM\src\lib\cstartup.s79

In IAR Embedded right click on the target "blinky - Internal Flash" and choose Add>>Add Files option. Browse to the appropriate path (Note that the default is to show .c files so change the file type option to show all files). Once this file is added to the project try to build and debug and once the Internal Flash is programmed disconnect the JLink and recycle power. The LED should continue to blink.

If it still isn't working then are you disconnecting the Jtag after a download by disconnecting the USB cable from the Jtag? or by actually disconnecting the Jlink by removing from the module at the Jtag pin header on module? If you just disconnect the USB cable while the program is running, it will not execute while the Jtag is still connected to module and the USB cable is unplugged.

Keep in mind that if you have a program in both internal and external flash, the program in external Flash will always execute upon a reset (not the code in internal flash). Be sure there is nothing in external Flash if you are trying to program and execute from internal Flash. The "Full Chip Erase" erases the external Flash and then programs external Flash. The "External Flash - Erase Only" demo erases the external Flash. Please run the "Erase Only" demo and then run the Internal Flash demo. Disconnect power, disconnect Jlink from module (remove ribbon cable from Jtag pin header), reconnect power.

 

 

phyCORE-LPC2294: External Memory Controller

 

Question:

I am trying to interface with an external memory device. I am using the LPC2294 development board.  What setup do I have to do in the Keil compiler to specify the memory addresses I am using, and is there any additional set up that needs to be done on the phyTec board?
We have assumed that we will be using /CS0 as the chip select for the external device, I am not sure if this is the right assumption or not. I am also assuming that when I access a variable at a particular address, the proper chip select signal will automatically be asserted, I am not sure if that is the right assumption.

Answer:

/CS0 is not an available CS signal. You will want to use /CS3.

/CS0 wired through CPLD to on board Flash
/CS1 wired through CPLD to on board RAM
/CS2 Ethernet
/CS3 Available

Please look at the phyCORE-LPC2294 Hardware Manual http://www.phytec.com/manuals/L-658e.pdf.

You will not need to modify anything on the PHYTEC development board to use /CS3.

Regarding software implementation, if you need to boot the software from this new external Flash device then you will need to modify the startup code and Configure the target settings in Keil "Options for Target", 'Target' tab. In order to use the Keil Flash Programmer you will need to add a Flash Programming algorithm in the "Options for Target", "utilities" tab, "Flash download setup".

If you do not require booting from your new Flash device you will need to modify the startup code (i.e. PINSEL2 and BCFG3 registers).

 


phyCORE-LPC2294: XTAL Frequency

Question:

What is the frequency of the onchip XTAL?

Answer:

The XTAL1 is 10 MHz.

Integrating LPC2292

 

Question:

I need some help. We plan to use the LPC2292 part in our designs for the first time. I have no idea, or help from Philips, on how to do a layout for this device. Can you guide me in the proper way to layout my PCB with this device? I appreciate any help you can provide.

Answer:

PHYTEC currently only supports the Philips LPC2294 controller on our phyCORE-LPC2294 SBC module and Rapid Development Kit. Go to: http://www.phytec.com/sbc/32bit/pclpc229x.htm for more details. With the purchase of this Rapid Development Kit you will receive a hard copy of the circuit diagrams. This example circuitry can be used as a guideline for your own designs. If you are considering using the PHYTEC insert-ready subassembly in your application you only need to concentrate on designing your specific I/O or interface circuitry. By integrating the phyCORE module you save time to market and NRE cost. For more information on OEM of PHYTEC SBC modules in target applications go to: http://www.phytec.com/oem/oem.htm

 

Carrier Board HD200: Molex Connectors for expansion bus

 

Question:

What are the exact dimensions (or part#) of the 160-Pin Molex Female Receptacles that will connect with the Molex Male Headers located on the HD200 Carrier Board?

Answer:

An overview of the part numbers of the Molex connectors is available on our website at http://www.phytec.com/pdf/PHYTEC_Molex_P-N_Overview.pdf

There are also spec sheets available online at  http://www.phytec.com/products/related-products/molexconnectors.html

 

phyCORE-LPC2294: Disable External Flash to Execute Code in Internal Flash

 

You do not have to disable the External Flash in order to execute code in Internal Flash. If you do not have code in external Flash, the code in internal Flash will always execute. However, if you want to you can modify this system startup configuration by removing some resistors on the module. Please see http://www.phytec.com/pdf/manuals/L-658e.pdf section 4.1.

 

phyCORE-LPC2294: Flash Memory Configuration

Question:

On your phyCORE-LPC2294 (PCM-023-SK-2294), the ext. Flash memory on Bank 0 seems to be AM29BL800BT (Quickstart Manual). If I check online I don't get a clear picture of the organization of this memory module. Is it 8-bit or 16-bit organized?

Answer:

We use two 16-bit data bus width Flash devices in parallel connected to a 32-bit data bus on the LPC2294. The Flash chip's /BYTE input is pulled high thus enabling WORD configuration of the memory chip.

phyCORE-LPC2294: Trouble with Demo

<font size="4">Question:
</font>

I am using the Demo Keil uVision3 development system sent with a PHYTEC LCP2294 board. Going through the QuickStart app note, I have noticed some differences between the pictures and the explanations. I've solved some of them but I'm stuck at selecting the target processor. I click on the pull down menu but only get two choices: "Simulator" and "LPC2100". I then clicked on the "Options for Target" button and under the "Device" panel I find LPC2294 (the pull-down menu label remains at LPC2100). Once selected, I followed the instructions and downloaded the "Blinky" code. The code downloaded but did not run. I, then, downloaded the pre-compiled (.hex) file using RS232 connection and it worked fine. Is there something I am missing in the instructions? Any help would be greatly appreciated. Also, do you have any sample code for using the Ethernet port? I understood that there is no support on the CAN (DeviceNet) side but I thought there would be something on the Ethernet side.

<font size="4">Answer:</font>

It sounds like you have the wrong demos. Please refer to the demos on the Spectrum CD, which were included in your Kit. Browse to the phyBASIC folder and copy the phyCORE-LPC2294 demos to your C: drive. There is also an Ethernet demo on the Spectrum CD …\PhyExt\pC-LPC2294\Keil.

phyCORE-LPC2294: Ethernet Issues

Question:

Are there any known issues with the Ethernet?

Answer:

There is an Ethernet limitation to the phyCORE-LPC2294 which actually stems from the Development board and is only present when connecting at 100Mbit speeds. The Development Board HD200 will only work with baudrats up to 10MBit/s. If you use a hub or switch with 10/100MBit/s auto negotiation the demo will not work because the LAN Controller tries to setup the 100MBits, but this baudrate will not work on the HD200 Development board. At 100Mbit speeds the auto-negotiation phase will not correctly be finished and so there will be no error free transmission.

The problem is the length of the signal traces for the Ethernet lines as well as the way the signal lines are routed cause the 10MBit limitation. The HD200 board works with many other phyCORE modules which only support 10Mbits/s speeds (developed prior to the phyCORE-LPC2294). Unfortunately the phyCORE-LPC2294 inherited this limitation. Internal tests at PHYTEC have confirmed that the operation of the PHYCORE Module at 100Mbits/s is possible with shorter signal traces than on our development board. When designing your own carrier board you must be sure these signal traces are straight and as short as possible.

Please see the errata for the LPC2294
http://www.phytec.com/manuals/Datasheets/LPC2294_errata.pdf

phyCORE-LPC2294: Flash Memory Write Access Control

Question:

On the phyCORE-ARM7/LPC229x (part # PCM-023), how does the PLD that controls the Flash operate? I am asking because I would like to write to the Flash, but in order to do so, I need to write a specific sequence to them before writing can take place. Are they always organized in a 2x16 configuration, or does the PLD somehow make it a 4x8 configuration sometimes?

Answer:

Flash access is always in a 16-bit * 2 fashion. Or, in other words, you want to use WORD mode rather than BYTE mode.

phyCORE-LPC2294: Compatibility with ARM Multi-ICE RealView development/debug system

 

Question:

I'm about to purchase a phyCORE-ARM7/LPC229x Rapid Development Kit and would like to know if it is compatible with my ARM Multi-ICE RealView development/debug system. TheARM Multi-ICE uses a 20-pin JTAG interface and CodeWarrior/AXD for code development and debug interface.

Answer:

The ARM Multi-ICE is in the list of development tool support from Philips for the LPC2292/94 processor. There is a 20-pin JTAG interface on our board so phyCORE-LPC2294 should be compatible with these tools.

 

phyCORE-LPC2294: Choosing Between phyCORE-LPC2292 and phyCORE-LPC2294

Question:

How does one pick a 2292 or a 2294 controller when ordering from PHYTEC? I went through the ordering process and it comes up with 229x.

Answer:

Our phyCORE-LPC229x is populated with the LPC2294 as a standard configuration. If you require the LPC2292 we can do this at a minimum order quantity, however, the LPC2294 is the superset and for all purposes is the same as the LPC2292.

phyCORE-LPC2294: JTag Communication Error

 

Problem:

JTag Communication Error

Resolution:

Please make sure you have the power plugged into the board and that your USB-to-JTAG interface is correctly connected.

Additionally, if you have "broken" code in external Flash that modifies the LPC2294 controller configuration in a way that does not allow any JTAG communication, this could cause such errors. But forcing the chip into ISP mode, hence not executing whatever code resided in external Flash, allows you to erase that code and reprogram the chip properly.

Please try the following:

Force the board into ISP (In System Programming) mode by pressing both the Boot (S-1) and Reset (S-2) buttons on the development board (near the DB-9 connectors). Next, release the Reset button (S-2), followed by the Boot button (S-1) a couple seconds later. Now you should be able to connect to the board so that you can erase whatever may be in extermal Flash.

 

phyCORE-LPC2294: Processor Clock Frequency Calculation

<font size="4">Question:</font>

What is the processor clock frequency if the PLL configuration register is set to 0X00000025?
PLLCFG_Val EQU 0x00000025

<font size="4">Answer:</font>

The processor clock is 60MHz. See below for calculation.

The PLLCFG register is bits are 7:0 consisting of two functions, a PLL Divider and PLL Multiplier and a reserved bit 7.

MSEL4:0 (PLL Multiplier value) Supplies the value "M" in the PLL frequency calculations.
For details on selecting the right value for MSEL4:0 see section "PLL Frequency Calculation" from the LPC2294 Users Manual.

PSEL6:5 (PLL Divide value) Supplies the value "P" in the PLL frequency calculations.

For details on selecting the right value for PSEL6:5 see section "PLL Frequency Calculation" from the LPC2294 Users Manual.

The PLL equations use the following parameters:
FOSC the frequency from the crystal oscillator
FCCO the frequency of the PLL current controlled oscillator
cclk the PLL output frequency (also the processor clock frequency)
M PLL Multiplier value from the MSEL bits in the PLLCFG register
P PLL Divider value from the PSEL bits in the PLLCFG register

PLL Example calculation:

System design asks for Fosc= 10 MHz and requires cclk = 60 MHz.
Based on these specifications, M = cclk / Fosc = 60 MHz / 10 MHz = 6. Consequently, M-1 = 5 will be written as PLLCFG 4:0.
Value for P can be derived from P = Fcco / (cclk * 2), using condition that Fcco must be in range of 156 MHz to 320 MHz. Assuming
the lowest allowed frequency for Fcco = 156 MHz, P = 156 MHz / (2*60 MHz) = 1.3. The highest Fcco frequency criteria produces
P = 2.67. The only solution for P that satisfies both of these requirements and is listed in Table 27 (Refer to the LPC2294 user manual) is P = 2.
Therefore, PLLCFG 6:5 = 01 will be used.

phyCORE-LPC2294: External Oscillator Frequency

 

Question:

What is the external oscillator frequency?

Answer:

On the standard configuration of the phyCORE-LPC2294 with part number PCM-023-SK-2294, the external oscillator is 10Mhz.

 

phyCORE-LPC2294: Differences in the Interrupt Implementation between LPC2100 and LPC229x

Question:

Are there differences in the interrupt implementation between LPC2100 and LPC229x?

Answer:

According to an Applications Engineer at Philips, there is no difference in the interrupt implementation between these processors.

Connecting emulators

In order to connect an emulator with a 2.5 mm cable to a phyCORE-LPC229x or phyCORE-AT91 you can use the PHYTEC JTAG adapter, part number JA-002. If the JA-002 JTAG adapter is not included in your Rapid Development Kit you can order this item from PHYTEC or through one of our distributors.

The JA-002 JTAG adapter has two configuration jumpers.

Proper operation of the iSYSTEM iC3000 Emulator requires the jumpers settings shown in the picture below.

Link: JA-002_for_iSYSTEM.jpg

Proper operation of the HITEX Tanto or Tantino requires the jumpers settings shown in the picture below.

Link: JA-002 for HITEX.jpg