phyCORE-MPC555

QuickStart Instructions

Components Placement Diagrams

  • PL1169.0
  • PL1169.1
  • PL1169.2
  • PL1169.3

Module Connector

PHYTEC Order Number: VB082

Development Tools

For support to the development tools please contact the tool developer.

 

JTAG Emulators

FAQ

phyCORE-MPC555

LPT-to-BDM Interface for MPC5x5 or MCF548x

Question:

 I have trouble communicating with a parallel port JTAG interface. What should I try?

 Answer:

 1.    The BIOS settings for the Parallel port should be one of the following: ECP, EPP or PS/2 Bi-directional.

 2.    In Windows XP: make sure to turn off the parallel port plug and play scanning "feature". This feature of Windows XP will interrupt parallel port communications between the PC and LPT-to-JTAG interface. This will yield what looks like sporatic communications. Turning of the autoscan "feature" may be turned off for the parallel port in the WINXP registry…….

 3.    The parallel cable connecting the PC parallel port and the LPT-to-JTAG interface MUST be IEEE1284 compliant. If the cable is not marked with the IEEE1284 text, then it is not compliant.

 4.    In Windows XP/2000, the parallel port dialog checkbox entitled "Enable Legacy Plug and Play" should be checked. This setting is located in the Control Panel à System à Hardware à Device Manager à Ports à Printer Port (LPTx) dialog. You must reboot your PC after this setting to take effect.

 5.    Make sure to turn off any applications which may be trying to access the printer port (such as a Print Manager) before running software to debug with LPT-to-JTAG interface.

 6.    Also beware that some laptops, in particular some of the IBM Thinkpads, do not implement a standard parallel port even though they claim they do. If you encounter this problem on a laptop and have access to a desktop machine, it is best to try the experiment on the desktop in order to rule out other issues.

phyCORE-MPC555: Mit dem CW8.7 geht das Löschen des internen Flash schief

Die Kommunikation mit dem SRAM via BDM sowie Debugging des Beispiels ist problemlos möglich. Jedoch kommt beim Versuch, das interne Flash zu löschen und neu zu programmieren, die Fehlermeldung:
    -- Error received: Flash driver reports the following error(s):  Chip reported error during erase

1.) NXP liefert auf der CD des CW8.7 zwar bereits eine ganze Menge aktueller PHYTEC-Files mit, die dortigen Flash-Binaries sind jedoch leider veraltet.

Bitte gehen Sie in das Verzeichnis
C:\Programme\NXP\CodeWarrior EPPC 5xx V8.7\bin\Plugins\Support\Flash_Programmer\EPPC
und ersetzen Sie die dortigen beiden Files mpc555.elf sowie mpc555sh.elf durch die beiden von der PHYTEC Spectrum-CD aus deren Verzeichnis
phyCORE-MPC555/Tools/CW8.1/bin/Plugins/Support/Flash_Programmer/Eppc

 

2.) Bitte sicherstellen, dass das interne Flash aktiviert ist:

Entweder per Hardware, indem JP15=1+2 konfiguriert ist.

Oder per Software, indem im Config-File phyCORE-MPC555_init.cfg die Zeile
writespr 638 0xFFF00800 ; IMMR=0xFFF00800
existiert und nicht mit Semikolon auskommentiert ist

phyCORE-MPC555 4MB Flash und 4MB RAM: Modul geht in Reset, Reset LED blinkt

Frage:

Bei dem Betrieb unseres phyCORE-MPC555 kommt es zu sparadischen Ausfällen. Wir haben ein Modul mit 4 BM Flash und 4 MB RAM und das Modul fällt besonders nach langem Betrieb in den Resetzustand und die Reset LED blinkt. Das Modul betreiben wir auf der Basisplatine aus dem Development Kit

Antwort: 

Eine Überprüfung ergab, daß das mitgelieferte Netzteil mit 500 mA bei diesem Modulausbau an der Grenze liegt. Benutzen Sie nach Möglichkeit ein 9V Netzteil mit einem Nennstrom von 1A.

NXP MPC555 Dokumentation

Auf der Homepage von NXP auf der MPC555 Product Summary Page finden Sie  Application Notes, Datasheets und Reference Manual und vieles mehr zu dem MPC555 Controller

Link: MPC555 Product Summary Page

phyCORE-MPC555: Error: "AbatronProtocolPlugin: BDI: No response from BDI"

 

Problem:

When I try to download to the board I get an error message in Metrowerks CodeWarrior stating: "AbatronProtocolPlugin: BDI: No response from BDI"

Solution:

The problem is that you do not have the correct BDM interface selected in your project's Target Settings. The phyCORE development board has an on board BDM interface integrated into the board circuitry. The default interface setting in Metrowerks CodeWarrior is the Abatron BDM interface and you will get such an error if the correct interface is not selected.

Follow these steps:
* From CodeWarrior IDE menu, select Edit -> "Project name" Settings (or Alt+F7)
* In the 'Target Settings Panel' under 'Debugger' select 'Remote Debugging'
* In the 'Connection Settings' pull down menu change Abatron Serial to MSI Wiggler
* Click Apply and Ok

 

phyCORE-MPC555: "PowerPC Exception: External Exception 0x0500"

 Problem:

I have downloaded the MIOS demo to the MPC555. When I run the program I get a "PowerPC Exception: External Exception 0x0500" error.

Resolution:

It's not an error, it's a feature. The Metrowerks Debugger is configured to  catch the exception. To run it without catching, disable the exception in your target settings.
Also, be sure you are using the "ram debug" target, not the "ram" target for downloading/debugging.  The difference is, that the exception table is placed into SRAM and the SRAM space is relocated to address 0x0. Program  exception occurs due to on address 0x500 is no valid opcode in the ram target. To avoid confusion you can delete the "ram" target.

 

Another possibility for this behaviour is, if under "Edit / ram Settings / Debugger / Remote Debugging" You have chosen Connection "MSI Wiggler", but under "Edit Connection..." the entry "FPU Buffer Address" has not been set to 0x10000000.

phyCORE-MPC555: Simulink Resets back to "Abatron Serial"

 

<font size="4">Problem:</font>

Simulink seems to reset "Remote Connections setting" back to "Abatron Serial" as soon as I try to "Install MPC5xx Bootcode" to the target. I started with "MSI Wiggler 0x10000000" before starting to Install bootcode.

<font size="4">Solution:</font>

Did you configure a "MPC555DK Wiggler" connection, documented as
follows?

http://www.mathworks.com/access/helpdesk/help/toolbox/mpc555dk/ppc_app3 .html#17137

Simulink should always use the "MPC555DK Wiggler" connection.

phyCORE-MPC555: Example of Link Command File for RAM/ROM

Question:

Do you have an example of link command file for the memory partition of the ram, rom ?

Answer:

The rom target uses the Linker Command File burnrom.lcf included in the Hello_Fl demo project.
The ram target does not use a Linker Command File. The Linker settings are made in the ram Settings, EPPC Linker panel.

phyCORE-MPC555: VG96 Socket Crimp Connectors

Question:

Do you know of any VG96 socket connectors that are suitable for connection to the VG96 plug on your phyCORE-MPC555 Development Board? I would prefer a crimp connector solution.

Answer:

There are VG96 socket strips available with crimp connection for attaching flat band cables.

Go to:
http://www.reichelt.de/
In the Search/Suche field, enter the part number "FEDERL. 96FSK".

These are standard parts and should also be available in the U.S..

phyCORE-MPC555: Slow to boot

Question:

We are using your phyCORE-MPC555 on our own carrier board and we see that one of the units boots up very slowly. While it typically takes about 5 seconds for our firmware to start up this particular unit takes ca. 30 seconds. We checked the power supply circuitry and it seems to be okay. Could this have something to do with the reset signals on the board and external circuitry connected to these lines?

Answer:

The /HRESET pin should only be connected to an open collector driver, or better left unconnected. If there are any capacitors or resistors (pull-ups) connected to these signals then the reset behavior can be affected negatively. It would be better to use the /HRESIN signal if you wish to connect a push button for releasing a hardware reset.

phyCORE-MPC555: Molex Connectors

 

Question:

On the original PHYTEC MPC 555, PHYTEC had an assigned part number for the 160 pin connector that mated to the PHYTEC MPC555 SBC. Does PHYTEC sell the 160 pin mate connector that the MPC555 board would plug into? If yes, could you let me know the part number and availability of the connector?

Answer:

The mating connector for our phyCORE-MPC555 (part# PCM-001-xxx) can be purchased from PHYTEC. Our internal part number is VB082. You need two to mate with one phyCORE module. They are available from stock.

Here is a table that shows you all the available connectors for our phyCORE modules:

http://www.phytec.com/devbd/phycore/molexconnectors.htm

Please note that there will be a part number change going from the leaded connectors to the lead free version. Right now we only have the leaded parts in stock. Below are the Molex part numbers for the lead free version once available.

55091-0809 lead free part #55091-0879
55091-1009 lead free part #55091-1079
55091-1609 lead free part #55091-1679

On the above link you can download the Molex connector specs for your layout. Simply click on the applicable Molex part number.

 

phyCORE-MPC555: Input Capacitance

Question:

Where in the documentation can I find the input capacitance value of MPC555's pins?

Answer:

Please refer to the MPC555 user manual, section for Electrical Characteristics. The input capacitance will depend on the pin.

phyCORE-MPC555: Initialized Program Entry Point

 

Question:

I would like to see what the program is doing before my main() function. So can someone point me out where I can find the EPPC Linker > Entry point such as reset or __start or where is the beginning of the program? I checked the file: __ppc_eabi_init.c but I could not find the entry point Is this entry embedded in the library file?

Answer:

The Entry Point function _start is a global function defined in Runtime.PPCEABI.H.a __start.o which is a library file.

Before your main() is executed, the function usr_init() is invoked, providing board level initialization code for the phyCORE-MPC555. The usr_init() function is defined in phyCORE-MPC555_init.c (startup code).

Refer to the ram.MAP file from the phyCORE-MPC555 Hello_Fl demo.

 

phyCORE-MPC555: Memory Module

 

Question:

I would like to understand the memory address on the board I ordered. This board includes 1 MB external SRAM, 512 MB external Flash, 448 KB on-chip Flash and 4 KB serial eeprom. Is the based memory on 0x00000000? Or I can change on the chip selector. Also, do you have an example of link command file for the memory partition of the ram, rom ?

Answer:

Please see section 6 of the phyCORE-MPC555 Hardware Manual.
The rom target uses the Linker Command File burnrom.lcf included in the Hello_Fl demo project.
The ram target does not use a Linker Command File. The Linker settings are made in the ram Settings, EPPC Linker panel.

 

phyCORE-MPC555: Closing the Jumper

Question:

It says in the quickstart guide that we have to Close Jumper JP6. What does it mean?

Answer:

Closing the Jumper means you are establishing a connection between two pins, so you need to put the Jumper "on" the pins.

phyCORE-MPC555: Error: Wrong CodeWarrior Version

Problem:

I've just received my PHYTEC rapid development kit for MPC555. As explained in the quick start instruction booklet, I've first installed CodeWarrior delivered with the kit (CW for MPC5xx V8.1). After that I've started to install the rapid development kit software but I could not complete the installation because it complained about a wrong CodeWarrior version. What's wrong?

Resolution:

Please read PHYTEC's technical note TN-008.

phyCORE-MPC555: P&E BDM and Memory Read/Write Bus Error

 

Problem:

I have a PHYTEC MPC555 board, Metrowerks Code warrior, and a P&E BDM. When trying to debug I get the following error message:
"PandEProtocolPlugin: Bus error occured while reading/writing memory."

The remote debugging is set to:
EPPC - P&E
Parallel LPT1
IO Delay Count 0
FPU Buffer Address 0x00c00000

Solution:

Please check that the Development board Jumpers are set correctly for external BDM interface.

The default jumper settings of the phyCORE-MPC555 Development Board connect the BDM signals from the MPC555 controller through the phyCORE-MPC555 Molex connector to the on-board BDM interface logic. This allows for BDM communitation through the DB-25 connector. If you want to use an external BDM interface such as the P&E adapter you need to remove Jumpers JP1 through JP9 on the Development board. This disconnects the controller's BDM signals from the on-board interface logic. Jumper JP2 must be configured according to supply voltage requirements of the P&E adapter you have. JP2 connects pin 9 on BDM connector (X4) to either 3.3 V or 5 V.

I have not tried the P&E adapter with the phyCORE-MPC555 board. Have you tried using the on Board wiggler?

 

phyCORE-MPC555: CAN Example Code

 

Question:

I am trying to write application code that makes use of the CAN controllers on the MPC555 on your phyCORE-MPC555 module. Do you have any CAN examples to get me started? I already have the PCAN-USB adapter and a CAN cable.

Answer:

We do have a CAN demo project for the phyCORE-MPC555. It sends CAN messages over the first CAN port (CAN-A, P4) using 1 MBit/s as CAN bitrate and CAN ID 200hex. Connect a CAN cable to the PCAN-USB adapter and watch the messages with PCANview. This demo is included as the attachment "hello_can.zip".

 

phyCORE-MPC555: Demo Using Interrupt Requests

 

Question:

Is there a demo that illustrates the use of  IRQ interrupt requests for the phyCORE-MPC555 (PCM-001)?

Answer:

There is a demo available.

 

phyCORE-MPC-555: QADC Analog Input

<font size="2"></font>

<font size="2"><font size="4">Question:</font> </font>

<font size="2">What is the maximum safe analog input range for QADC on the MPC555?</font>

<font size="2"><font size="4">Answer:</font> </font>

<font size="2">The min/max is -.3v to +5.3V. Please refer to the MPC555 User Manual table G-7.<font color="#0000ff" size="2">
</font>
</font>

<font size="2"></font>

<font size="2">The QADC Analog Input Voltage MIN is V_SSA -.3v and the MAX is V_DDA + 0.3V</font>

<font size="2">V_DDA is set on the module to 5.0V and V_SSA is 0V.</font>

phyCORE-MPC555: TPU troubles

Problem:

I have issues with the TPU on the board. Are there any examples to enable testing the TPU?

Solution:

Attached is  an AppNote discussing TPU programming. You may also refer to the following resource page with links to more demos:

http://www.ee.ualberta.ca/~jasmith/mpc555/#tpu

 

Einspeisen eines extern Taksignals über den EXTCLK-Pin des phyCORE-MPC555 Moduls

Um dies zu konfigurien bedarf es Lötarbeiten auf dem phyCORE-MPC555 Modul, wodurch die Garantie erlischt.
Für das Einspeisen eines extern Taksignals über Pin EXTCLK (1A) ist der Quarz zu entfernen und C10 durch einen 0R Widerstand (Lötbrücke) zu ersetzen.
Weiterhin müssen die Jumper J5, J3, J4 (MODCK[1:3]) entsprechend des gewünschten Clockmodus konfiguriert werden. Siehe Table 8-1 im MPC555 User's Manual.

Ready/Busy-Funktion über /IRQ5 auf PCB 1169.0

Die Ready/Busy-Funktion über /IRQ5 wird bei der Revision 1169.0 nicht unterstützt. Soll der /IRQ5 über den Taster S5 der Trägerplatine PCM-995 angesteuert werden, muß R37 entfernt werden. Siehe auch Release Notes im Hardware Manual zum phyCORE-MPC555 Modul.

CAN und I²C Demo

Auf unserem FTP Server finden Sie entsprechende Demos. 

CAN und I²C-Bus Beispiele

Erase of Flash device

Question:


I am running an example from the PHYTEC Spectrum CD. I run this example in the ROM memory and now I can not erase this memory. How can I erase the Flash memory?

The example is: phyEXT/phyCORE-MPC555/phyCORE-MPC555.mcp

Answer:


You can erase the Flash by simply putting a breakpoint to the correct position in the Flash programming routine. The function for erasing the external Flash is called:

...
f_EraseFlash();
...

The routine that erases the internal Flash device is as follows:

...
for(i=0;i<mod_blocks;i++)> {
error_code=Erase(i);
if(CMF_Error_Occurred(error_code)) Error_Handler(error_code);
}
...

If you have set a breakpoint to this Flash erase function and then exit the debugger you have successfully erased the Flash.</mod_blocks;i++)>

Metrowerks / Freescale Code Warrior PowerPC

phyCORE-MPC5554: Ethernet Bus Control Configuration

Question:

I am trying to use the Ethernet on the phyCORE MPC5554, but I am unable to see LAN91C111 registers.

Answer:

It is important to include the configuration of TSIZ[1:0].  This is used by the CPLD to scope the driver access, so if TSIZ isn't active during access the LAN_BEx signals will never driven correctly.

The complete configurations of the bus control pins are as follows:  

 ; config minimum bus control pins

; TSIZ[0:1] PCR 60/61

;writemem.l 0xc3f900b8 0x04c004c0  ***

writemem.l 0xc3f900b8 0x04c304c3

 

 

; RD/WR & BDIP PCR 62/63
writemem.l 0xc3f900bc 0x04c004c0

; WE[0-4] PCR 64-67
writemem.l 0xc3f900c0 0x04c304c3
writemem.l 0xc3f900c4 0x04c304c3

; OE & TS PCR 68-69
writemem.l 0xc3f900c8 0x04c304c3

; configure the chip selects
; CS[0-3] PCR 0-3
writemem.l 0xc3f90040 0x04c304c3
writemem.l 0xc3f90044 0x04c304c3

; CLKOUT
; PCR 229
writemem.w 0xc3f9020a 0x02c0

phyCORE-MPC565: Difference between Target Initialization(.cfg) and Startup Code (.c) Files

Question:

What is the difference between the files: phyCORE-MPC565_init.c (startup code) and the phyCORE_MPC565_BDM_init.cfg (Target initialization file)? Both initialize some of the same core registers and memory but they serve different purposes.

Solution:

The startup code (phyCORE-MPC565_init.c ) and source code (main.c) object files are processed by the linker and an executable file is created. You can then download this executable into RAM or Flash. However, before any code can be downloaded to the board, CodeWarrior must initialize a couple of things. The file which performs this initialization is the Target Initialization file (phyCORE_MPC565_BDM_init.cfg). This file initializes the PowerPC core registers and memory-mapped control registers. This file is not downloaded to the target as the startup code is. Typically, its job is to configure Flash access space, SDRAM controller and SDRAM memory BEFORE the Debugger can download the application for debugging or before a Flash Programmer can begin its operation and download the application to flash.

 

phyCORE-MPC565: Linker Command File

Question:

Do you have an example of link command file for the memory partition of the ram, rom ?

Answer:

The rom target uses the Linker Command File burnrom.lcf included in the Hello_Fl demo project.
The ram target does not use a Linker Command File. The Linker settings are made in the ram Settings, EPPC Linker panel.

phyCORE-MPC565: Ethernet Controller

Problem:

In the phyCORE-565 manual, there is little information about programming the CS8900 ethernet controller.

Resolution:

PHYTEC now provides an Ethernet demo program for the phyCORE-MPC565 with its on-board CS8900A LAN controller. Here you will find complete Metrowerks project.

Please keep in mind that the CS8900A is operated in I/O mode and that because of the big Endian (MPC565) versus little Endian (CS8900A) byte order. This also affects the meaning of the CS8900A control registers. See sections 9.1 and 9.2 in the phyCORE-MPC565 hardware manual.

phyCORE-MPC565: Initialized Program Entry Point

Question:

I would like to see what the program is doing before my main() function. So can someone point me out where I can find the EPPC Linker > Entry point such as reset or __start or where is the beginning of the program? I checked the file: __ppc_eabi_init.c but I could not find the entry point Is this entry embedded in the library file.

Answer:

The Entry Point function _start is a global function defined in Runtime.PPCEABI.H.a __start.o which is a library file.

Before your main() is executed, the function usr_init() is invoked, providing board level initialization code for the phyCORE-MPC565. The usr_init() function is defined in phyCORE-MPC565_init.c (startup code).

Refer to the ram.MAP file from the phyCORE-MPC555 Hello_Fl demo.

phyCORE-MPC565: Creating a New Project

Problem:

While creating a new project, File -> New -> EPPC New Project Wizard After entering project info (name, location etc..)
In the EPPC New Project Wizard;
Linker: Metrowerks PowerPC EABI Linker
Target: Generic, PowerPC 565 (I do not see phyCORE anywhere)
Programming Language: C
Remote Connection: MSI Wiggler 0x10000000

Is it appropriate to use Generic, PowerPC565 in the "Target" option? Can you suggest what would be the closest since there is no "phyCORE" in the list?

Solution:

Please use the given Hello_Fl project as a template for new projects. The Hello_Fl project already has the target, linker, compiler, debugger, and startup code correctly configured for the phyCORE-MPC565 target. From the project window you can add or remove source files, add code libraries, modify compiler and linker settings, and compile and link your project.

phyCORE-MPC555: CodeWarrior license key

There should be an integrated registration wizard that opens during the CodeWarrior installation from which will instruct you on how to attain the correct license from MetroWerks.

Fragen und Antworten zu ähnlichen Produkten

phyCORE-MPC5554/5567: Wie kann der FPGA programiert werden?

Auf der Homepage von Lattice finden Sie das Datenblatt zu dem ispDOWNLOAD Cabel, das Sie auf Anschluß X4 auf der Basisplatine PCM-979 für das phyCORE-MPC5554/5567 anschliessen können. In der Figure 4 ist die Anschlußschema dargestellt, die auf Anschluß X4 passte. Dieses Programmierkabel gibt es für USB und für LPT

LIN Bus

Der NXP MPC5554 / MPC5567 Controller des phyCORE-MPC5554 / MPC5567 beinhaltet zwei eSCIs (enhanced Serial Communication Interface), die LIN fähig sind. Auf dem phyCORE-MPC5554 /MPC5567 werden die beiden eSCIs als serielle V24 Schnittstelle benutzt und damit an einen RS232 Transceiver angeschlossen. Es ist aber möglich durch Entfernen der Jumper J21 und J22 den zweiten eSCI von dem RS232 Trensceiver zu trennen und dann extern (außerhalb des Moduls) an einen LIN Transceiver wie z.B TJA1020 oder MCP201 anzuschließen und damit einen LIN Bus zu realiesieren.

NXP MPC5567 Dokumentation

Auf der Homepage von NXP auf der MPC5567 Product Summary Page finden Sie  Application Notes, Datasheets und Reference Manual und vieles mehr zu dem MPC5567 Controller

Link: MPC5567 Product Summary Page

LPT-to-BDM Interface for MPC5x5 or MCF548x

Question:

 I have trouble communicating with a parallel port JTAG interface. What should I try?

 Answer:

 1.    The BIOS settings for the Parallel port should be one of the following: ECP, EPP or PS/2 Bi-directional.

 2.    In Windows XP: make sure to turn off the parallel port plug and play scanning "feature". This feature of Windows XP will interrupt parallel port communications between the PC and LPT-to-JTAG interface. This will yield what looks like sporatic communications. Turning of the autoscan "feature" may be turned off for the parallel port in the WINXP registry…….

 3.    The parallel cable connecting the PC parallel port and the LPT-to-JTAG interface MUST be IEEE1284 compliant. If the cable is not marked with the IEEE1284 text, then it is not compliant.

 4.    In Windows XP/2000, the parallel port dialog checkbox entitled "Enable Legacy Plug and Play" should be checked. This setting is located in the Control Panel à System à Hardware à Device Manager à Ports à Printer Port (LPTx) dialog. You must reboot your PC after this setting to take effect.

 5.    Make sure to turn off any applications which may be trying to access the printer port (such as a Print Manager) before running software to debug with LPT-to-JTAG interface.

 6.    Also beware that some laptops, in particular some of the IBM Thinkpads, do not implement a standard parallel port even though they claim they do. If you encounter this problem on a laptop and have access to a desktop machine, it is best to try the experiment on the desktop in order to rule out other issues.

NXP MPC5554 Dokumentation

Auf der Homepage von NXP auf der MPC5554 Product Summary Page finden Sie  Application Notes, Datasheets und Reference Manual und vieles mehr zu dem MPC5554 Controller

Link: MPC5554 Product Summary Page

phyCORE-MPC5554: Ethernet Bus Control Configuration

Question:

I am trying to use the Ethernet on the phyCORE MPC5554, but I am unable to see LAN91C111 registers.

Answer:

It is important to include the configuration of TSIZ[1:0].  This is used by the CPLD to scope the driver access, so if TSIZ isn't active during access the LAN_BEx signals will never driven correctly.

The complete configurations of the bus control pins are as follows:  

 ; config minimum bus control pins

; TSIZ[0:1] PCR 60/61

;writemem.l 0xc3f900b8 0x04c004c0  ***

writemem.l 0xc3f900b8 0x04c304c3

 

 

; RD/WR & BDIP PCR 62/63
writemem.l 0xc3f900bc 0x04c004c0

; WE[0-4] PCR 64-67
writemem.l 0xc3f900c0 0x04c304c3
writemem.l 0xc3f900c4 0x04c304c3

; OE & TS PCR 68-69
writemem.l 0xc3f900c8 0x04c304c3

; configure the chip selects
; CS[0-3] PCR 0-3
writemem.l 0xc3f90040 0x04c304c3
writemem.l 0xc3f90044 0x04c304c3

; CLKOUT
; PCR 229
writemem.w 0xc3f9020a 0x02c0

phyCORE-MPC5200B-IO, phyCORE-MPC5554: Wo finde ich fertige FPGA IP-COREs?

Viele fertige IP-Cores für diverse Aufgaben, Schnittstellen usw. kann man im Internet beim Hersteller von FPGAs finden und in einigen IP-Cores Sammlungen. Eine umfangreiche Sammlung finden Sie z.B. unter http://www.opencores.org/

NXP MPC565 Dokumentation

Auf der Homepage von NXP auf der MPC565 Product Summary Page finden Sie  Application Notes, Datasheets und Reference Manual und vieles mehr zu dem MPC565 Controller

Link: MPC565 Product Summary Page

phyCORE-MPC565: Blinking LED

 Problem:

When power is applied to the board LED D6 blinks before any code is downloaded to the internal Flash.

Resolution:

If power is applied to the board and LED D6 blinks before you programmed the board with demos, you may have received a board with code already in the internal Flash. Please refer to section 2.5.3 of the QuickStart and erase the internal Flash. After you are sure there is no code in the Flash, you can go through the QuickStart instructions for programming to RAM, internal Flash, and external Flash.

 

phyCORE-MPC565: Difference between Target Initialization(.cfg) and Startup Code (.c) Files

Question:

What is the difference between the files: phyCORE-MPC565_init.c (startup code) and the phyCORE_MPC565_BDM_init.cfg (Target initialization file)? Both initialize some of the same core registers and memory but they serve different purposes.

Solution:

The startup code (phyCORE-MPC565_init.c ) and source code (main.c) object files are processed by the linker and an executable file is created. You can then download this executable into RAM or Flash. However, before any code can be downloaded to the board, CodeWarrior must initialize a couple of things. The file which performs this initialization is the Target Initialization file (phyCORE_MPC565_BDM_init.cfg). This file initializes the PowerPC core registers and memory-mapped control registers. This file is not downloaded to the target as the startup code is. Typically, its job is to configure Flash access space, SDRAM controller and SDRAM memory BEFORE the Debugger can download the application for debugging or before a Flash Programmer can begin its operation and download the application to flash.

 

phyCORE-MPC565: Board Freezes at 56MHz Frequency when HRESET high and VDDGOOD low

Problem:

We are using phyCORE MPC565 modules (pcb 1198.2) in our own target boards and they all work well at 40MHz clock setting (MF set to 9). However the boards freeze up (HRESET high, VDDGOOD low) when the clock is bumped up to 56MHz. Some of the boards do this right at startup and some do it after a few minutes or even a couple of hours. We have all the power supplies on the target board at optimum (5V, 3.3V, and 2.6V). All three are capable of sourcing at least 1A each.

Solution:

These effects sound like a non sufficient power supply. Are you having problems operating the same boards at high frequencies on the PHYTEC development board (PCM-991)?

Can you test this? The critical supply voltage is the 2V6. This input voltage should be between 2.6...2.7V. Set the voltage to the middle 2.65V or higher. It is very important that the input voltages are very low impedance.

 

phyCORE-MPC565: Molex Connectors

 

Question:

On the PHYTEC 565 SBC, do you have the spec for the connector that mates to the MPC565 board? We are trying to layout the board that the MPC565 will be plugged into and we need to have the correct layout on our motherboard. Also would you please let me know the commercial and PHYTEC part number for the 200 pin connector that mates to the MPC 565 connector? If PHYTEC sells the mate connector would you let me know the part number and please quote the price and availability of the connector?

Answer:

The mating connector for our phyCORE-MPC565 (part# PCM-019) can be purchased from PHYTEC. Our internal part number is VB107. You need two to mate with one phyCORE module. They are available from stock.

Here is a table that shows you all the available connectors for our phyCORE modules:

http://www.phytec.com/devbd/phycore/molexconnectors.htm

Please note that there will be a part number change going from the leaded connectors to the lead free version. Right now we only have the leaded parts in stock. Below are the Molex part numbers for the lead free version once available.

55091-0809 lead free part #55091-0879
55091-1009 lead free part #55091-1079
55091-1609 lead free part #55091-1679

On the above link you can download the Molex connector specs for your layout. Simply click on the applicable Molex part number.

 

phyCORE-MPC565: KPWAR Keep Alive Register Power Supply

 

Question:

I am curious to see if the KAPWR pin on the Motorola MPC565 could be brought out to a pin on the molex connector instead of being tied to the 2.6 volt rail? The reason I ask is that I have a dedicated standby/keepalive output on my power supply that I would like to tie directly to the KAPWR pin.

If that is not possible, could I just remove the J7 jumper and hand wire from J7 pin 2 to my standby power supply pin?

Answer:

KAPWR pin cannot be brought out to a pin on the molex connector. Looking at the schematic for the phyCORE-MPC565 it sounds reasonable to open J7 and hand wire from J7 pin 2 to your standby power supply. Please take a look at the MCP565 User Manual section 8.8 for more detail on the KAPWR power source requirements. Alternatively, it should also be fine to connect VBAT to KAPWR.

 

phyCORE-MPC565: Ethernet Controller

Problem:

In the phyCORE-565 manual, there is little information about programming the CS8900 ethernet controller.

Resolution:

PHYTEC now provides an Ethernet demo program for the phyCORE-MPC565 with its on-board CS8900A LAN controller. Here you will find complete Metrowerks project.

Please keep in mind that the CS8900A is operated in I/O mode and that because of the big Endian (MPC565) versus little Endian (CS8900A) byte order. This also affects the meaning of the CS8900A control registers. See sections 9.1 and 9.2 in the phyCORE-MPC565 hardware manual.

phyCORE-MPC565: AbatronProtocolPlugin Error

Problem:

When I try to download I get a message saying  "AbatronProtocolPlugin: BDM: No response from BDM" pops up.

Resolution:

The problem is that you do not have the correct BDM interface selected in your project's Target Settings. The phyCORE development board has an on board BDM interface integrated into the board circuitry. The default interface setting in Metrowerks CodeWarrior is the Abatron BDM interface and you will get such an error if the correct interface is not selected.

1) Please refer to section 2.4.1 of the phyCORE-MPC565 Quickstart guide for setting up a Remote Connection. If you have already done this previously skip to next step.

2) The new MSI Wiggler connection, which was added in section 2.4.1, must be set in the Target Settings.

Follow these steps:
* From CodeWarrior IDE menu, select Edit -> "Project name" Settings (or Alt+F7)
* In the 'Target Settings Panel' under 'Debugger' select 'Remote Debugging' select the MSI Wiggler 0x10000000 and click OK.

phyCORE-MPC565: Initialized Program Entry Point

Question:

I would like to see what the program is doing before my main() function. So can someone point me out where I can find the EPPC Linker > Entry point such as reset or __start or where is the beginning of the program? I checked the file: __ppc_eabi_init.c but I could not find the entry point Is this entry embedded in the library file.

Answer:

The Entry Point function _start is a global function defined in Runtime.PPCEABI.H.a __start.o which is a library file.

Before your main() is executed, the function usr_init() is invoked, providing board level initialization code for the phyCORE-MPC565. The usr_init() function is defined in phyCORE-MPC565_init.c (startup code).

Refer to the ram.MAP file from the phyCORE-MPC555 Hello_Fl demo.

phyCORE-MPC565: Executing Code from Flash Without Boot Button

 

Question:

The phyCORE-MPC565 development board needs the boot button to be pressed to start any program residing in Flash. Is there a way to make it start when the power is plugged (without having to press the boot button)?

Answer:

I found one way to avoid the boot push button sequence in order to start code downloaded to Flash on our phyCORE-MPC565 module. There is a jumper on the Development Board that connects the DSCK signal from the controller to external circuitry on the Development Board. The DSCK signal is connected to the boot push button at S1. This jumper is labeled JP33 and the location of that Jumper on the Development Board is shown in figure 15 of the Hardware Manual L-635e_6. If you remove that jumper your program residing in Flash will execute when the power is plugged in or if the reset button is pushed.

You have to make sure JP33 is closed when communicating through the BDM interface for code download or debugging steps. If JP33 remains open you will get an error message in CodeWarrior

 

phyCORE-MPC565: Processor Clock Speed

Problem:

I have mounted the phyCORE-MPC565 on my own carrier board. The processor clock of the MPC565 is running at 20MHz. I am expecting 56MHz. I am measuring the signal, CLKOUT, at pin 1B of the bus. When I mount the phyCORE-MPC565 module on the PHYTEC Development board I get the expected 56MHZ at CLKOUT. What could be causing this?

Solution:

The problem may that the /PORESET is not setting properly. This could be caused by incorrect power supply circuitry on your carrier board. The clock frequency (clock mode) is set during the /PORESET (during power up). While the /POSRESET is active, the bit-pattern (default MODCK[1..3]= 010, 4MHz Quartz, limp-mode) connects to the MODCK[1..3] signals of the MPC565. After /PORESET the signals which connect to the MPC565 become interrupts (irq6, irq7, irq8). If the /PORESET is not activating correctly you may be setting the clock mode inadvertently with the interrupt signals instead of the MODCK signal. Please compare your power supply circuitry to the circuitry on the PHYTEC Development board. Also, look at section 4. Power System & Reset behavior http://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-635E.pdf of the manual.

phyCORE-MPC565: Nexus Port 50 Pin

 

Question:

I am planning on fully utilizing the Nexus capabilities of the MPC565 by incorporating a 50-pin Nexus port on my mainboard (using your MPC565 daughter board). However, in reference to your development board schematic, what is the reason for deviating from NXP's suggested Nexus connections? Why does PHYTEC have a proprietary version of the Nexus port when NXP offers a standard pinout solution? 

Answer:

PHYTEC has a proprietary version because at the time of development and release it was the up-to-date pin assignment, however implement the latest recommendation provided by NXP and the Tool Vendors.

 

phyCORE-MPC565: Disable Internal Pull Up Resistors

<font size="4">Question:</font>

Are there any on-board or internal pull-up resistors for the MPC565 QADC submodule? How can I disable them? Are the any guidelines for connecting analog input signals to the phyCORE-MPC565 module?

<font size="4">Answer:</font>

There are weak pull-up resistors for the analog inputs on the MPC565 controller. These internal resistors can be disabled using the bit field PULL_DIS in the PDMCR register. See section 2.2 in the MPC565 reference Manual for details. When connecting external analog input signals to the module it is important that the circuitry has a low impedance. A high impedance connection will lead to incorrect ADC conversion results. Additional specifications for the QADC submodule can be found in section E14 of the MPC565 Reference Manual.