Information on this Manual

This hardware manual describes the PCL-078 System on Module, referred to as phyCORE®-i.MX 8M Plus FPSC. This manual also specifies the phyCORE-i.MX 8M Plus FPSC design and function. Precise specifications for the NXP® Semiconductor i.MX 8M Plus microcontrollers can be found in the i.MX 8M Plus Microcontroller Data Sheet/Reference Manual.

There will be several changes and additions to this manual. New versions will be released in the future with no notice. Please use this manual's latest version when working with your product.

Future Proof Solder Core

The PCL-078 System on Module, referred to as phyCORE®-i.MX 8M Plus FPSC, is designed according FPSC Featureset 24A.0 Specifications. This will be available as soon as possible.

Libra Development Board

Throughout this manual you may see references to our PCB, the Libra Development Board. The hardware manual, pinout and other aspects are currently being developed and will not be shown in this version of the phyCORE-i.MX 95 FPSC manual. Future versions of this manual will contain more information about the Libra Development Board. 

Design Considerations

The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and is known to work. The schematics have been re-formatted to fit better in this hardware manual.

Many hardware examples and suggestions are given in the following pages. Designing the phyCORE System on Module onto a Carrier Board is generally straightforward. However, before committing to a particular active component selection when designing a carrier board, it is wise to check out the software driver support for those components. A particular device may be supported in, say, for example, Linux but not in Windows Embedded Compact 7. Your overall project may go smoother if you pick components that are already supported in your target OS. The premade selections for our reference designs, for example our Single Board Computers, are typically focused on using components that are well supported under Linux.

Preface

As a member of PHYTEC's product family, the phyCORE® SoM can be populated with different controllers, various types of memory (RAM, NAND flash, eMMC), and many other features. This, in turn, offers increased types of functions and configurations. PHYTEC supports a variety of 8/16/32/64-bit controllers in two ways:

1. As the basis for Rapid Development Kits which serve as a reference and evaluation platform
2. As insert-ready, fully functional phyCORE® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "reinvent" microcontroller circuitry. Furthermore, much of the value of the phyCORE® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative, full-system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®

PHYTEC System on Modules are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Product Change Management and Information Regarding Parts Populated on the SoM

With the purchase of a PHYTEC SoM / SBC, you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our Product Change Management (PCM) team of developers is continuously processing all incoming Product Change Notifications (PCNs) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.

Our general philosophy here is: We will never discontinue a product as long as there is a demand for it.

To fulfill this, we have established a set of methods to fulfill our philosophy:

Avoidance strategies:

• Avoid changes by evaluating the longevity of parts during the design-in phase.
• Ensure the availability of equivalent second source parts.
• Stay in close contact with part vendors to keep up with roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

• Ensure long-term availability by stocking parts through last-time buy management according to product forecasts.
• Offer long-term frame contracts to customers.

Change management in cases of functional changes:

• Avoid impacts on product functionality by choosing equivalent replacement parts.
• Avoid impacts on product functionality by compensating for changes through hardware redesign or backward-compatible software maintenance.
• Provide early change notifications concerning functional, relevant changes to our products.

We refrain from providing detailed part-specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

• Quickstart Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a Board Support Package (BSP), the device tree, and accessing peripherals.
• Hardware Manual:  A detailed description of the System on Module (SoM) and accompanying carrier board. 
• Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; introducing, installing, and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
• BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
• Development Environment Guide:  This guide shows how to work with the Virtual Machine (VM) Host PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running demo projects for these programs on a phyCORE product as well. Information on how to build a Linux host PC yourself is also a part of this guide.
• Pin Muxing Table:  phyCORE SoMs have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case-by-case basis. Most of the documentation can be found on the applicable download page of our products.

These manuals and more can be found in the download section of phyCORE-i.MX 8M Plus FPSC Product page.

Conversions, Abbreviations, and Acronyms

Conventions

The conventions used in this manual are as follows:

• Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low or are driving low.
• A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
• The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the address byte. The correct value of the LSB, which depends on the desired command (read (1), or write (0)), must be added to get the complete address byte. For example, if the given address in this manual is 0x41 =>, the complete address byte = 0x83 to read from the device and 0x82 to write to the device
• Tables that describe all settings show the default position in bold, blue text.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of signal.

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document.

phyCORE-i.MX 8M Plus FPSC Introduction

The phyCORE‑i.MX 8M Plus FPSC belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SoMs represent the continuous development of the PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all Electromagnetic Interference (EMI) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 20 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high-noise environments.

phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 8M Plus FPSC is a subminiature (40 mm x 37 mm) insert-ready System on Module populated with the NXP® Semiconductor i.MX 8M Plus microcontroller. Its universal design enables it to be inserted into a wide range of embedded applications. All controller signals and ports extend from the controller to surface mount technology (FPSC FTGA 1.27 mm grid) connectors aligning four sides of the board, allowing it to be soldered into any target application like a "big chip".

The descriptions in this manual are based on the NXP® Semiconductor i.MX 8M Plus. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 8M Plus FPSC.

phyCORE-i.MX 8M Plus FPSC Features

The phyCORE‑i.MX 8M Plus FPSC offers the following features:

• Insert-ready, sub-miniature (40 mm x 37 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology
• Mounted using FTGA Direct Solder Connector (FPSC FTGA)
• Populated with the NXP® Semiconductor i.MX 8M Plus microcontroller (BGA548 packaging)
• Up to 4 ARM-A53 cores (clock frequency up to 1.8 GHz)
• Machine Learning Neuronal Processing Unit (NPU) with 2.3 TOPS
• 1x Cortex M7 core (800 MHz). All Cortex M7 dedicated interfaces are explicitly made available on the SoM connector.
• Tensilica Hifi4 Audio DSP (800 MHz)
• 3D GPU GC7000UL and 2D GPU GC520L
• Neural Network Accelerator (up to 2.3TOPS)
• on-board Image Signal Processor (up to 12MP resolution/ up to 375MP/s)
• Boot from different memory devices (eMMC Flash standard)
• Single supply voltage of +5.0 V with on-board power management
• Selectable IO voltage between 1.8 V and 3.3 V (1.8 V is the default according to FPSC Specification) 
• All controller-required supplies are generated on-board using sophisticated on-board Power Management
• Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins

• up to 8 GB^[1] LPDDR4 RAM

• up to 64 GB^[1] on-board eMMC in the commercial temperature range (up to 32 GB for I-Temp)
• 4kB^[1]I²C User-EEPROM and 4kB I²C Factory-EEPROM
• 2x USB 3.0/2.0 Dual-Role interfaces with PHY
  

• 2x 1Gbit Ethernet interfaces with TSN support (either one of them with Ethernet transceiver on the phyCORE-i.MX 8 M Plus FPSC enabling a direct connection to an existing Ethernet network; the second as RGMII Signals at logic-level at the signal pins instead)

• 5x I²C interfaces
  
• 2x SPI interfaces
• 1x PCIe interface
• 3x UART interfaces
• 2x CAN-FD interfaces
• 4x PWM outputs
• 1x MIPI DSI-2 interface
• 1x HDMI interface
• 2x MIPI CSI-2 camera interfaces
• 1x LVDS Tx interface 2 channels x4
• 1x 4-bit SD-Card interface
• 1x 4-bit SDIO interface
  
• 1x SAI audio interfaces
• Extreme Low Power RTC Module
• 4x temperature sensors to monitor the board's temperature profile
• All processor interfaces available at the SoM Connector
• Available for different temperature grades (see Product Temperature Grades)

phyCORE-i.MX 8M Plus FPSC Block Diagram

phyCORE-i.MX 8M Plus FPSC Component Placement

phyCORE-i.MX 8M Plus FPSC Minimum Operating Requirements

Before the phyCORE-i.MX 8M Plus FPSC can be used, please make sure the host system meets the minimum operating requirements. These include:

• The stable and clean input power supply of 5.0 V with low ESR bulk capacitors (e.g. 2x 47µ/16V MLCC) paired with some HF blocking capacitors (e.g. 100nF/16V MLCC) connected to the input pins as near as possible (phyCORE-i.MX 8M Plus FPSC Power Consumption). It is recommended to monitor the supplied input voltage against minimum voltage level 4.75 V and drive X_POR_B_VIO low if the input voltage is below.
• Appropriate configuration of the I/O voltage (1.8 V default or 3.3 V) configured by signal X_VIO_Ctrl (External Logic IO Supply Voltage)
• Supply voltage for externally connected peripherals should be controlled by signal X_nPWR_READY to avoid reverse currents (External Logic IO Supply Voltage)
• If external peripherals need a longer reset delay, hold reset signal X_POR_B_VIO as long low as needed (Reset)
• Desired boot configuration - default configuration is "Boot from on-board eMMC" (System Boot Configuration)
• To back up the on-board I2C-RTC, connect a buffer voltage source to input pin X_RTC_VBACKUP (Backup Power (X_RTC_VBACKUP / VIN_SNVS_1V8), RTC)

Pin Description

All controller signals extend to FPSC footprint. These contacts line four sides of the module (referred to as FPSC footprint). This enables phyCORE-i.MX 8 Plus FPSC to be placed into any target application like a "big chip".

PHYTEC provides a complete pinout table for the phyCORE-i.MX 8M Plus FPSC Footprint (X1). This table contains a complete signal path for the phyCORE‑i.MX 8M Plus FPSC and the carrier board PCM-937-L, including signal names, pin muxing paths, and descriptions specific to each pin. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found with the phyCORE-i.MX 8M Plus FPSC Pinout Table.

Jumpers

The phyCORE-i.MX 8M Plus FPSC (PCL-078) is jumperless. There are, however, a few jumpers on the Baseboard PCM-937-L. Information on these jumpers can be found inJumpers.

Power

The phyCORE‑i.MX 8M Plus FPSC operates off of a single power supply voltage. The following section discusses the primary power pins on the phyCORE i.MX 8M Plus Connector X1 in detail.

Primary System Power (VIN)

The phyCORE‑i.MX 8M Plus FPSC is powered by a primary voltage supply with a nominal value of +5.0 V. On-board switching regulators generate the voltage supplies required by the i.MX 8M Plus MCU and on-board components from the primary 5.0 V supplied to the SOM.

For proper operation, the phyCORE‑i.MX 8M Plus FPSC must be supplied with a voltage source of 4.75 ... 5.25 V with a maximum power consumption of a 2.5 A load at the VIN pins on the phyCORE.

                VIN:                        X1 → AA1, AA2, AB1, AC1, AC2, AB3, AA4, AC3

Connect all +5.0 V VIN input pins to your power supply and all GND contacts of the module.

                Corresponding GND:           X1 → all GND contacts of the module

Please refer to section Pin Description for information on additional GND Pins located at the phyCORE i.MX 8M Plus FPSC Connector X1.

For information on various power consumption scenarios that PHYTEC has run, go to phyCORE-i.MX 8M Plus FPSC Power Consumption.

Power Management IC (PMIC) (U3)

The phyCORE-i.MX 8M Plus FPSC provides an on-board Power Management IC (PMIC) at position U3 to generate different voltages required by the microcontroller and the on-board components. The PMIC supports many functions like different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 8M Plus via the on-board I²C bus (I2C1). The I²C address of the PMIC is 0x25.

Power Domains

External voltages to supply the board:

• VIN 5.0 V main supply voltage (4.75 .. 5.5 V / max. 2.5 A)
  
• optional: VIN_SNVS_1V8 low power supply voltage input (1.8 V ±5% / 10mA; if left open, it is provided on-board if VIN is present)
• X_RTC_VBACKUP (e.g. 3.3 V) backup supply voltage for the on-board I2C-Bus RTC U9 (RV-3028-C7)

External Logic IO Supply Voltage

The voltage level (VDD_IO) of the phyCORE’s logic interface circuitry is VDD_1V8 (1.8 V) or VDD_3V3 (3.3 V) which is determined by the configuration input signal X_VIO_Ctrl (X1-AA9). Connect X_VIO_Ctrl to the module input supply voltage VIN (5V) to configure VDD_IO=3.3 V interface voltage level or connect it to GND or leave it open (has onboard pull-down) to select VDD_IO=1.8 V interface voltage level.

To follow the power-up and power-down sequencing mandatory for the i.MX 8M Plus, external devices connected to the phyCORE interface circuitry have to be supplied by an external power supply which is controlled by the output signal X_nPWR_READY (OD driver) which is brought out at pin X1-AB7. X_nPWR_READY should control the external supply voltage which is used to supply the external interface circuitry connected to the phyCORE's interfaces. X_nPWR_READY switches from High-Z to GND to start the external voltage supply or to switch over a power switch. If the on-board interface voltage (VDD_IO) switches off, X_nPWR_READY is released to high impedance. To raise the signal, an external pull-up resistor (eg. 4k7) is needed. It can be connected to voltage levels up to 10V (used Transistor DMN1260UFA has abs. max. 12V) depending on the external power supply control signal requirement. The use of X_nPWR_READY ensures that external components are only supplied when the supply voltages of the i.MX 8M Plus is stable and avoids undefined return currents while the system is powered down.

Backup Power (X_RTC_VBACKUP / VIN_SNVS_1V8)

To back up the on-board I2C-Bus RTC U9 (RV-3028-C7), an external voltage source must be added at Pin X1-AC7 (X_RTC_VBACKUP). The RTC has an extremely low backup current consumption of only 40nA (@3 V). It is also possible to supply the internal RTC and some critical registers of the i.MX 8M Plus' low power domain (NVCC_SNVS_1V8). NVCC_SNVS_1V8 can be supplied over Pin X1-AD8 if VIN is not present.

Manual Power Switch (X_OnOff)

The signal X_OnOff (Pin X1-AC4) is used to manually switch the power of the SOM. X_OnOff signal can be left unconnected if not used. It has a weak on-board pull-up resistor against NVCC_SNVS_1V8 and is held high as long as VIN is present or external backup voltage VIN_SNVS_1V8 is supplied. To drive the signal to GND, use an open collector driver or push button. For more information about ONOFF refer to the NXP Semiconductor i.MX 8M Plus Reference Manual.

Reset

The X_PMIC_RST_B signal (Pin X1-AF3) on the phyCORE-Connector is designated as a "cold reset" input. Driving X_PMIC_RST_B to low (has weak pull-up to SNVS_1V8) will restart the system performing a complete power recycle. X_PMIC_RST_B has a 50ms debouncing circuit. This input can be used for a mechanical reset switch button. X_POR_B_VIO Signal (Pin X1-AB5) can be used to prevent bootup of the i.MX 8M Plus. This can be used as a startup as described in the section Power Management IC. 

System Boot Configuration

Most features of the i.MX 8 Plus microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured before initialization via pin termination.

The system start-up configuration includes:

• Boot mode selection
• Boot device selection
• Boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 8M Plus after POR. The ROM code detects the boot mode by using the boot mode pins (BOOT_MODE[3:0]), while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO input pins (X_BOOT_MODE[3:0]).

Boot Mode Selection

The boot mode of the i.MX 8M Plus microcontroller is determined by the configuration of four boot mode inputs BOOT_MODE[3:0] during the reset cycle of the operational system. These inputs are brought out at the phyCORE processor pins X_BOOT_MODE[3:0] (X1-AA7, X1-AA6, X1-AA5, X1-AA4). phyCORE-i.MX 8M Plus FPSC Boot Modes shows the possible settings of pins X_BOOT_MODE[3:0] and the resulting boot configuration of the i.MX 8M Plus.

The X_BOOT_MODE[3,2,0] lines have 100 kΩ pull-down resistors populated (and unpopulated pull-up resistors) while X_BOOT_MODE[1] has a 4,7 kΩ pull-up resistor on the module in parallel to the internal pull-down resistors of the i.MX8 M Plus. Leaving the four pins unconnected sets the controller to boot mode 1, boot from on-board eMMC U4 memory device. The boot configuration settings can be changed by changing the populated resistors configuration on the module or by connecting configuration resistors (e.g. 4,7 kΩ pull-up) to the X_BOOT_MODE configuration signals. The pull-up resistors must be supplied by the right VDD_IO voltage level of 1.8 V (default according FPSC Specificaiton) or 3.3 V depending on the VDD_IO configuration (see section External Logic IO Supply Voltage).

The BOOT_MODE is initialized by sampling the BOOT_MODE inputs on the rising edge of the POR_B. After these inputs are sampled, their subsequent state does not affect the contents of the BOOT_MODE internal register and the pins can be used for GPIO operation.

System Memory

The phyCORE‑i.MX 8M Plus FPSC provides three types of on-board memory:

^*Factory EEPROM should not be used by the application. It contains module specific information to identify the module during factory handling and testing.

LPDDR4-RAM (U1)

The RAM memory interface of the phyCORE‑i.MX 8M Plus FPSC supports one 32-bit LPDDR4-RAM chip (U1). The LPDDR4 memory is accessible starting at addresses 0x4000 0000 and 1 0000 0000.

Typically, the LPDDR4-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 8M Plus controller. Refer to the NXP Semiconductor i.MX 8M Plus Reference Manual to access and configure these registers.

eMMC Flash Memory (U4)

The main flash memory of the phyCORE‑i.MX 8M Plus FPSC is eMMC and is populated at U4. The eMMC Flash memory is connected to the SD3 interface of the i.MX 8M Plus.

For more information about the eMMC Flash interface, please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual.

I²C Factory EEPROM (U10)

The phyCORE‑i.MX 8M Plus FPSC is populated with a non-volatile 4 kB I²C EEPROM at U10. This memory is used to store configuration data and should not be used for different purposes. This device is accessed through I²C port 1 on the i.MX 8M Plus. The control registers for I²C port 1 are mapped between addresses 0x30A2 0000 and 0x30A3 0000. Please see the NXP Semiconductor i.MX 8M Plus Reference Manual for detailed information on the registers.

The three lower address bits are fixed to 0x1 which means that the EEPROM can be accessed at I²C address 0x51. The EEPROM has a second address on 0x59, which is called Identification Page.

The device is write proteced per default. Write protection can be deactivated by driving the signal X_EEPROM1_WC (X1-DE21) to GND. The signal has a 10k pull-up resistor to VDD_IO (default 1.8 V).

I²C User EEPROM (U18)

The phyCORE‑i.MX 8M Plus FPSC is populated with a non-volatile 4 kB I²C EEPROM at U18. This memory is free of use. This device is accessed through I²C port 1 on the i.MX 8M Plus. The control registers for I²C port 1 are mapped between addresses 0x30A2 0000 and 0x30A3 0000. Please see the NXP Semiconductor i.MX 8M Plus Reference Manual for detailed information on the registers.

The three lower address bits are fixed to 0x1 which means that the EEPROM can be accessed at I²C address 0x50. The EEPROM has a second address on 0x58, which is called Identification Page.

The device is not write proctected per default. Write protection can be established by driving the signal X_EEPROM2_WC (X1-DF20) to VDD_IO (default 1.8 V). The signal has a 10k pull-down resistor.

Serial Interfaces

The phyCORE‑i.MX 8M Plus FPSC provides numerous dedicated serial interfaces, some of which are equipped with a transceiver to enable direct connection to external devices:

1. 1x 4-bit SDIO interface (SD2) with controlled IO voltage
   
2. 1x 4-bit SDIO interface (SD1)
   
3. 1x QSPI interface
4. 3x high-speed UARTs
5. 2x CAN-FD interfaces
6. 2x USB 3.0/2.0 Dual-Role interfaces with PHY
7. 2x 1Gbit Ethernet interfaces with TSN support (ENET1 with Ethernet transceiver on the phyCORE-i.MX 8 M Plus FPSC enabling a direct connection to an existing Ethernet network; ENET0 as RGMII Signals at logic-level at the signal pins instead)
8. 5x I²C interfaces
9. 2x Serial Peripheral Interfaces (SPI)
10. 1x SAI audio interface
11. 1x PCI Express with x1 interface
12. 2x MIPI CSI-2 camera interfaces
13. 1x MIPI DSI-2 display interface

Details for each of these serial interfaces and any applicable jumper configurations are below.

SDIO Interface

The SDIO interface can be used to connect external SD cards, eMMC, or any other device requiring an SDIO interface (i.e WiFI, I/O expansion, etc.) The phyCORE bus features one SDIO interface. On the phyCORE‑i.MX 8M Plus FPSC, the interface signals extend from the first and second Ultra Secured Digital (SD1 and SD2) Host controller to the phyCORE-Connector. 

The tables below show the location of the different interface signals on the phyCORE-Connector. The MMC/SD/SDIO Host Controller is fully compatible with the SD Memory Card Specification 3.0. The interface supports SD cards with 1.8 V and 3.3 V I/O signals.

SDIO SD2 (4-bit)

SDIO SD2 is a 4-bit wide interface with controlled I/O voltage to support high-speed modes that require 1.8 V I/O voltage. During runtime, the I/O voltage can be switched from 3.3 V (default) to 1.8 V by the processor via GPIO signal X_PMIC_SD_VSEL/GPIO1_IO04 which controls the PMIC integrated voltage regulator. X_VDDSW_SD2 will be used exclusively to supply an external SD or MicroSD memory card. X_VDDSW_SD2 is monitored by the PMIC load switch circuit for overcurrent and short circuits. For more details, please refer to the PMIC data sheet provided by NXP.

SDIO SD1 (4-bit)

SDIO SD1 is an 8-bit wide interface. The I/O voltage is determined by VDD_IO which is statically configured for the system to 1.8 V or 3.3 V (refer to External Logic IO Supply Voltage).

Universal Asynchronous Interfaces (UARTs)

The phyCORE‑i.MX 8M Plus FPSC provides three high-speed universal asynchronous interfaces. The following table shows the location of the signals on the phyCORE-Connector.

CAN Interfaces

The CAN-FD interfaces of the phyCORE‑i.MX 8M Plus FPSC is connected to the FLEXCAN modules (FLEXCAN1/FLEXCAN2) of the i.MX 8M Plus which is a full implementation of the CAN FD protocol specification version 2.0B. It supports a flexible message payload, ranging from 0, 8, 12, 16, 20, 24, 32, 48, and 64 bytes. It supports also standard and extended message frames and programmable bit rates of 2, 5, and 8 Mb/s.

The following table shows the position of the signals on the phyCORE‑Connector.

USB Interfaces

The phyCORE‑i.MX 8M Plus FPSC provides two USB 3.0/2.0 dual role interfaces, which support super-speed (5Bbit/s), high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) operation. The applicable interface signals can be found on the phyCORE‑Connector X1. If overcurrent and power enable signals are needed for the USB host interface, the functionality can be easily implemented with GPIOs.

Ethernet Interfaces ENET0 and ENET1

The phyCORE‑i.MX 8M Plus FPSC provides two Ethernet Interfaces ENET0 with TSN support and ENET1. Connection of the phyCORE‑i.MX 8M Plus FPSC to the world wide web or a local area network (LAN) is possible using the on-board GbE PHY at U6. It is connected to the RGMII interface of ENET1. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. Additionally, the RGMII interface of ENET0, which is available on the phyCORE‑Connector, can be used to connect an external PHY. (ENET0 RGMII Interface).

ENET1 Ethernet PHY (U6)

With an Ethernet PHY mounted at U6, the phyCORE‑i.MX 8M Plus FPSC has been designed for use in 10Base-T, 100Base-T, and 1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE‑Connector X1.In Linux environment, ENET1 interface is called eth0 as it is the port with on-board PHY.

Ethernet Signal Locations of ENET1

The on-board GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct-connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface ENET1 of the i.MX 8M Plus. Please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (ETH_A±, ETH_B±, ETH_C±, ETH_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals. 

Reset of the Ethernet Controller

The reset input of the Ethernet PHY at U6 is connected to the system reset POR_B.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 8M Plus FPSC is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

ENET0 RGMII Interface

In order to use an external Ethernet PHY, the RGMII interface (ENET0) of the i.MX 8M Plus FPSC is brought out at phyCORE‑Connector X1. ENET0 is primarily used for TSN network operation. For that use case, an external TSN-ready ethernet switch device is used.In a Linux environment, ENET0 interface is called eth1 as it is the port with external PHY.

SPI Interface

The Serial Peripheral Interface (SPI) is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI on the phyCORE‑Connector X1. The SPI provides one chip-select signal for each interface. The Enhanced Configurable SPI (eCSPI) of the i.MX 8M Plus FPSC has three separate modules (eCSPI1, eCSPI2, and eCSPI3) which support clock rates of up to 60 MHz. The interface signals of the first and second modules (eCSPI1, eCSPI2) are made available on the phyCORE-Connector. These modules are master/slave configurable. The following table lists the SPI signals on the phyCORE-Connector.

I²C Interface

The Inter-Integrated Circuit (I²C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 8M Plus contains five identical and independent Multimaster fast-mode I²C modules. The interface of 4 modules is available on the phyCORE-Connector X1. I2C1 is reserved for controlling on the SOM. 

The following table lists the I²C ports on the phyCORE-Connector:

Audio Interface

 The i.MX 8M Plus FPSC supports multiple audio interfaces. One of them is available per default as listed below:

I²S Audio Interface (SAI)

The phyCORE-i.MX 8M Plus FPSC features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces SAI1, SAI2, SAI3, and SAI5. SAI5 is are routed directly to the phyCORE-Connector X1 per default.

TThe tables below show the signal locations of the SAI5 interface.

FPSC SAI1 Interface

PCI Express Interface

The one 1-lane PCI Express interface of the phyCORE‑i.MX 8M Plus FPSC provides PCIe Gen. 3.0 functionality which supports up to 8 GT/s operations. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented with GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Pollux) for a circuit example.

The position of the PCIe signals on the phyCORE‑Connector X1 is shown below:

General Purpose I/Os / PWM

All pins not used by any of the other interfaces specifically described in this manual and can be used as GPIO without harming other features of the phyCORE‑i.MX 8M Plus FPSC. These pins are shown below:

Besides these pins, most of the i.MX 8M Plus FPSC signals which are connected directly to the module connector can be configured to act as GPIOs, due to the multiplexing functionality of most controller pins. Normally, pins with signal type I/O are able to work as a GPIO.

GPIO Changing I/O Voltage

I/O voltage can be configured to 3.3 V or 1.8 V. Please refer to the section External Logic IO Supply Voltage. Be aware that changing the I/O voltage alters all interfaces which are in reference to VDD_IO.

Debug Interface

The phyCORE‑i.MX 8M Plus FPSC is equipped with a JTAG interface to download program code into the external flash, internal controller RAM, or any debugging programs being executed. The location of the JTAG pins on the phyCORE-Connector X1 are below:

UART Debug

The default debug UART Interfaces is FPSC UART3 (i.MX 8M Plus UART4) for Cortex-A53 Cores and FPSC UART2 (i.MX 8M Plus UART2) for Cortex-M7 Core. FPSC UART3 is accessible on connector X1 pins AB15 (RXD) and AC14 (TXD) and FPSC UART2 on pins DA6 (RXD) and DA7 (TXD).

For more information also refer to Universal Asynchronous Interfaces (UARTs).

Display Interfaces

High Definition Multimedia Interface (HDMI)

The High Definition Multimedia Interface (HDMI) of the phyCORE-i.MX 8M Plus FPSC is compliant with HDMI 2.0a for up to 1920x1080 at 60 Hz display resolutions. Please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual for more information.

The location of the HDMI signals on the phyCORE-Connector X1 are shown below:

Low Voltage Differential Signal Display Interface (LVDS)

The phyCORE-i.MX 8M Plus FPSC offers one LVDS display interface which supports two output channels.

The locations of the LVDS signals are shown below:

MIPI-DSI Display Interface (DSI)

The phyCORE-i.MX 8M Plus FPSC offers one MIPI-DSI display interface. MIPI-DSI has 4 channels, supporting one display with a resolution of up to 1920 x 1080 at 60Hz.

The locations of the MIPI-DSI signals are shown below:

Camera Connections

The phyCORE-i.MX 8M Plus FPSC offers 2 MIPI-CSI interfaces to connect digital cameras with a resolution of up to 12MP. The two MIPI/CSI‑2 camera interfaces of the i.MX 8M Plus extends to the phyCORE‑Connector X1 with 4 data lanes and one clock lane.

The locations of the MIPI-CSI signals are shown below:

FPSC Reserved Target specific Proprietary Signals

The following signals are not defined according FPSC Specification Featureset 24.0 (LAN-118e.Ax). These signals are processor specific and should only be used in application, if no direct compatibility betwenn differned SOM's is requiered.

RTC

The i.MX 8M Plus has an on-board, externally mounted RTC. The RV-3028-C7 is the newest generation of RTC from Micro Crystal with an extremely low backup current of typically 40nA at 25 degrees. PHYTEC uses the most optimal implementation in each phyCORE design to give the most optimal usage for all customers.

The RTC is accessible over I2C1 on Address 0x52. In a normal operation state, the RTC power is supplied from the SOM voltage VDD_3V3. If the SOM is not powered and RTC backup is needed, the VBACKUP Pin of the RTC can be supplied over the X_RTC_VBACKUP pin X1-AC7.

The RTC provides an interrupt output signal (X_RTC_INT) which is fed to the module connector X1-AC5. This signal is an open drain (OD). The on-board pull-up resistor R12 is, by default, not mounted. To use the X_RTC_INT signal, add an external pull-up resistor (e.g. 10k) to an appropriate I/O voltage level (e.g. X_RTC_VBACKUP).

Furthermore, the RTC is able to supply a programmable clock output signal (push-pull) RTC_CLKOUT. Frequencies of 1/32/64/1024/8192 Hz and 32.768 Hz (default) are programmable. The RTC_CLKOUT signal is fed to the module connector at X1-AC6. For a detailed description of the programming capabilities of the RTC, refer to the Micro Crystal RV-3028-C7 App-Manual.

The RTC supports an external event input signal (X_RTC_EVI at X1-DD20), which can be used e.g. interrupt genration or timestamp function. A 100k pull-down resistor is connected to this signal. For a detailed description of the programming capabilities of the RTC, refer to the Micro Crystal RV-3028-C7 App-Manual.

Temperature Sensors

The phyCORE-i.MX 8M Plus FPSC supports two internally sensored thermal zones in the i.MX 8M Plus CPU as well as 4 externally sensored thermal zones for monitoring board-level temperatures. The presence of the sensors depends on the delivery variant of the module.

The external temperature sensors are located at the positions U11, U12, U13 and U14.

The TMP102 temperature sensor devices used are connected to I2C1 bus. TMP102 measures temperatures from -40 °C to +125 °C. For a more detailed description of TMP102, refer to the Texas Instruments TMP102 Datasheet.

CPU Core Frequency Scaling

The phyCORE-i.MX 8M Plus FPSC is able to scale the clock frequency and voltage. This is used to save power and reduce heat dissipation when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as 'Dynamic Voltage and Frequency Scaling' (DVFS).

The phyCORE-i.MX 8M Plus FPSC BSP supports the DVFS feature. The Linux kernel provides a DVFS framework that allows each CPU core to have a min/max frequency as well as the applicable voltage and a governor that governs these values depending on the system load. Depending on the i.MX 8M Plus variant used, several different frequencies are supported. Further details on how to configure this governor can be found in the phyCORE-i.MX 8M Plus FPSC BSP Manual.

Technical Specifications

Additional specifications:

These specifications describe the standard configuration of the phyCORE‑i.MX 8M Plus FPSC as of the printing of this manual.

phyCORE-i.MX 8M Plus FPSC Power Consumption

The values listed in the table below are a guideline to determine the required dimensions of the power supply circuitry on a carrier board. They do not take application-specific load situations into account. These values have been generated by looking at the maximum power consumption measured using different load scenarios and adding a voltage source of 3.3 V.  These values are based on internal PHYTEC testing. Customers need to consider their application power requirements to ensure they do not generate a load greater than the values listed here. 

For power measurement, a SOM (PCL-078) with 2 GB RAM, 8GB eMMC, ETH0, HDMI, and an IMX8ML8DVNLZAA was used together with PD23.1.0.

Additionally, some values cannot be tested. Situations such as suspending to RAM, suspend freeze, and standby mode must be tested on a case-by-case basis to ensure the application's power consumption stays within the guidelines stated above.

Product Temperature Grades

Product Temperature Grades

The feasible operating temperature of the SoM is highly dependent on the use case of your software application. Modern high-performance microcontrollers and other active components, such as those described in this manual, are usually rated by qualifications based on tolerable junction or package temperatures. It is therefore not possible to make a general statement about minimum or maximum ambient temperature ratings for the SOM described.

However, the above components are available from the manufacturers with different temperature qualification levels. We offer our SOMs in different configurations using these temperature qualifications. To indicate which level of temperature qualification is used for the active and passive parts of a SOM configuration, we have categorized our SOMs into three temperature grades.

The table below describes these grades in detail. This table describes a set of components that, when combined, provide a useful set of product options with different temperature ratings. This allows us to take advantage of cost optimizations depending on the temperature range required.

In order to determine the correct temperature grade and whether the minimum or maximum qualification levels are met within an application, the following conditions must be defined by considering the use case:

• Determine the processing load for the given software use case
• Maximum component temperature ranges (table below)
• Power consumption resulting from a base load and the required computing power (taking into account peak loads and system cool-down periods)
• Ambient temperatures and airflow if the system is mounted in an enclosure
• Heat dissipation paths within the system, together with consideration of the use of a heat spreader or heat sink to optimize heat dissipation.

FPSC Footprint on the phyCORE-i.MX 8M Plus FPSC

For information on the footprint, mating baseboard footprint, numbering schema, etc. please refer to the corresponding FPSC Specification Featureset 24.0 (LAN-118e.Ax)

Pin numbering schema:

https://wiki.phytec.com/pages/viewpage.action?pageId=866713808#Featureset24.0Specifications(LAN118e.Ax)Head-PinNumbering

Mating FPSC Baseboard Footprint;

https://wiki.phytec.com/pages/viewpage.action?pageId=866713808#Featureset24.0Specifications(LAN118e.Ax)Head-Baseboard

Interface Signal Trace Length Table

PHYTEC recommends a control delay and trace length of the high-speed interface signals. Signal delay and trace length of the high-speed interface signals routed on the for of the phyCORE‑i.MX 8M Plus FPSC are listed in the following table. Take these values into consideration for the calculation of the overall delay and trace length budgets.

Hints for Integrating and Handling the phyCORE‑i.MX 8M Plus FPSC

Integrating the phyCORE-i.MX 8M Plus FPSC

Besides this hardware manual, more information is available to facilitate the integration of the phyCORE‑i.MX 8M Plus FPSC into customer applications.

1. The design of the phyBOARD‑Pollux can be used as a reference for any customer application.
2. Many answers to common questions can be found at: https://www.phytec.de/produkte/system-on-modules/phycore-imx-8m-plus-fpsc/#downloads/
3. The link “Carrier Board” within the category Dimensional Drawing leads to the layout data phyCORE-i.MX 8M Plus FPSC Footprint. It is available in different file formats. The use of this data allows the user to integrate the phyCORE-i.MX 8M Plus FPSC SoM as a single component in their design.
4. Different support packages are available for support in all stages of embedded development. Please visit https://www.phytec.de/support/support-pakete/ or https://www.phytec.eu/support/support-packages/ or contact our sales team for more details.

Handling the phyCORE-i.MX 8M Plus FPSC

phyCORE Module Modifications

The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station, or other desoldering methods is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Integrating the phyCORE into a Target Application

Successful integration in user target circuitry greatly depends on adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane.

Ordering Information

The part numbering of the phyCORE PCL-078 has the following structure:

Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html