LAN-105e.A0 phyCAM-L Data Rates

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LAN-105e.A0 phyCAM-L Data Rates
Document TitleLAN-105e.A0 phyCAM-L Data Rates
Document TypeHardware Guide
Article NumberLAN-105e.A0
Release Date12.11.2021
Is Branch ofLAN-105d.Ax phyCAM-L Data Rates Head

phyCAM-L Data Rates


This guide is intended to provide an overview of the data rates determined to date on the MIPI CSI-2 bus and FPD-Link III.

Calculation Based on Data Sheets and Laboratory Tests

The data rates that can be generated are derived from the reference clock of the oscillator connected to the DS90UB954. This may operate with a frequency fg between 23 and 26 MHz. In the standard configuration, (e.g. on the VZ-018) a 24 MHz oscillator is installed.

The frequency fFPD on the FPD link is calculated as follows:[1] (mathjax-inline(f_{FPD}=80*f_g=80*24 MHz = 1920 MHz)mathjax-inline)

(mathjax-inline(f_{FPD}=80*f_g=80*24 MHz = 1920 MHz)mathjax-inline)

The data rate is: [2]
(mathjax-inline(FPD_{DBR}= 160 * f_g = 160 * 24 MHz = 3840 Mbps )mathjax-inline)

The following applies to the permissible MIPI-CSI2 data transfer on the DS90UB953 according to TI: [3] (mathjax-inline(HSTX_{DBR}= \frac{32}{40} * FPD_{BDR}= \frac{32}{40} *3840 Mbps = 3072 Mbps)mathjax-inline)

This results in the following data rate per lane: [4] (mathjax-inline(HSTX_{DBR_LANE}=\frac{HSTX_{DBR}}{4}=\frac{3072 Mbps}{4}=768 Mbps)mathjax-inline)

To ensure that the camera data can also be transmitted at this maximum permissible data rate, the image data, the MIPI timing, and the blankings must also be taken into account. It should be noted that the blankings within the MIPI CSI-2 data stream are a component of the HS-LP-HS change.

For example, if 10% blankings are added to the lines, at least 10% must be subtracted from the available data rate. However, the MIPI timing settings can have a significant impact. The timings of TI's DS90UB954 are relatively generous or long. Measurement-wise, a minimum duration for the HS-LP-HS change of approx. 1.95 µs has resulted at 768 Mbps. This showed about 22.4% net data consumption when using the VM-017-L, at full resolution and 768 Mbps.

Therefore, there is a loss of the maximum amount of data available here. The maximum net transfer rate of the DS90UB954 should be generously undercut. Approx. 25% is recommended here. If a higher data rate is required, this must be discussed with TI. This should be possible, in principle, via the MIPI timing registers of the DS90UB954. As a rule, the HS-LP-HS requirement is approx. 13 - 16%.

(mathjax-inline(HSTX_{NETTO_DBR_LANE_CAM}=HSTX_{DBR_LANE}*0.75=768 Mbps*0,75=576 Mbps)mathjax-inline)

With a VM-017-L with 2592x1944 pixels, 8 bit data width results in the following FPS (blankings not included):

(mathjax-inline(FPS_{CAM}=\frac{4*HSTX_{NETTO_DBR_LANE_VAM}}{Res_X*Res_Y*Bit}=\frac{4*576 Mbps}{2592*1944*8}=57,1 fps)mathjax-inline)

This FPS should not be exceeded during operation. However, the Mbps (the operating frequency of the camera) can be increased up to the maximum frequency of the DS90UB953 (HSTXDBR_LANE). However, the maximum FPS must be maintained by means of blankings or the LLP. For snapshot recordings, the frame duration must be observed accordingly:

(mathjax-inline(t_{FRAME}=\frac{1}{FPS_{CAM}}=\frac{1}{57,1 fps}=17,5 ms)mathjax-inline)

By increasing the Frame Lenght Lines (FLL), a correction is not possible as a buffer overflow on the FPD link occurs if the line duration per line falls below this limit.   

As written in the TI e2e forum, the CSI-2 clock of the DS90UB953 is independent of the FPD link frequency. Higher frequencies than the frequency derived from the data rate may be used. However, no maximum is known. If a higher frequency must be used, this should be coordinated with TI. [5]


Texas Instruments, DS90UB953, SNLS552B, September 2018


Texas Instruments, How to Design a FPD-Link III System, SNLA267A, June 2019


Texas Instruments, How to Design a FPD-Link III System, SNLA267A, June 2019


Texas Instruments, How to Design a FPD-Link III System, SNLA267A, June 2019