Preface

As a member of PHYTEC's phyCORE^® product family, the phyCORE‑STM32MP15x is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers and, therefore, offers various functions and configurations. PHYTEC supports a variety of 8/16/32/64 bit controllers in two ways:

(1)     As the basis for Rapid Development Kits which serve as a reference and evaluation platform
(2)     As insert-ready, fully functional phyCORE^® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "re-invent" microcontroller circuitry. Furthermore, much of the value of the phyCORE^® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative full system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html

or

http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Ordering Information

The part numbering of the phyCORE has the following structure:

Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
https://www.phytec.de/produkte/system-on-modules/phycore-stm32mp15x/ 
or
https://www.phytec.eu/en/produkte/system-on-modules/phycore-stm32mp15x

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE^®‑STM32MP15x 

PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity only in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly with respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Implementation of PHYTEC products into target devices, as well as user modifications and extensions of PHYTEC products, is subject to renewed establishment of conformity to, and certification of, Electro Magnetic Directives. Users should ensure conformance following any modifications to the products as well as the implementation of the products into target systems.

Product Change Management and Information Regarding Parts Populated on the SOM / Carrier Board

With the purchase of a PHYTEC SOM / Carrier Board, you will, in addition to our HW and SW offerings, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) Team of developers, is continuously processing, all incoming PCNs (Product Change Notifications) from vendors and distributors concerning parts that are used in our products.

Possible impacts on the functionality of our products, due to changes in functionality or obsolesce of a certain part, are constantly being evaluated in order to take the right measures in purchasing or within our hardware/software design.

Our general philosophy here is: We never discontinue a product as long as there is a demand for it.

Therefore, we have established a set of methods to fulfill our philosophy:

Avoiding strategies:

• Avoid changes by evaluating the longevity of parts during the design-in phase.
• Ensure the availability of equivalent second source parts.
• Stay in close contact with part vendors to be aware of roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

• Ensure long-term availability by stocking parts through last-time buy management according to product forecasts.
• Offer long-term frame contracts to customers.

Change management in case of functional changes:

• Avoid impacts on product functionality by choosing equivalent replacement parts.
• Avoid impacts on product functionality by compensating changes through HW redesign or backward-compatible SW maintenance.
• Provide early change notifications concerning functional relevant changes to our products.

Therefore, we refrain from providing detailed part-specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

• QS Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a BSP, the device tree, and accessing peripherals.
• Hardware Manual:  A detailed description of the System on Module and accompanying carrier board. 
• Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; an introduction, installing and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
• BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
• Development Environment Guide:  This guide shows how to work with the pre-programmed programs Eclipse and Qt Creator. It includes instructions for running demo projects for these programs on a phyCORE product. Information on how to set up a Linux host PC is also included.
• Pin Muxing Table:  Starting in 2019, all phyCORE SOMs will have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case-by-case basis. All documentation can be found on the applicable download page of our products.

Conventions, Abbreviations, and Acronyms

This hardware manual describes the PCM-068 System on Module, referred to as phyCORE‑STM32MP15x, and the corresponding single-board computer PCM-939, the phyBOARD-Sargas STM32MP15x. The manual specifies phyCORE‑STM32MP15x and phyBOARD-Sargas's design and function. Precise specifications for the STMicroelectronics^®  STM32MP15x microcontrollers can be found in the enclosed Microcontroller Data Sheet/User's Manual.

Conventions

The conventions used in this manual are as follows:

• Signals that are preceded by an "n", "/", or “#” character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name are designated as active low signals. That is, their active state is when they are driven low or are driving low.
• A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
• The hex numbers given for addresses of I²C devices always represent the 7 MSB of the address byte. The correct value of the LSB which depends on the desired command (read (1), or write (0)) must be added to get the complete address byte. E.g.  given address in this manual 0x41 => complete address byte = 0x83 to read from the device and 0x82 to write to the device
• Tables that describe jumper settings show the default position in bold,bluetext.
• Text in blue italic indicates a hyperlink within, or external to the document. Click these links to quickly jump to the applicable URL, part, chapter, table, or figure.
• References made to the phyCORE-Connector always refer to the high-density Samtec connector on the undersides of the phyCORE‑STM32MP15x System on Module.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of signal.

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use this table to navigate unfamiliar terms used in this document.

phyCORE‑STM32MP15x Introduction

The phyCORE‑STM32MP15x belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of the PHYTEC System on Module technology. Like its mini-, micro-, and nano MODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a sub-miniature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all EMI (Electro-Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which provides for the dedication of approximately 20 % of all connector pinson the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high-noise environments.

phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In accordance with the complexity of the module, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.

The phyCORE‑STM32MP15x is a sub-miniature (40 mm x 44 mm) insert-ready System on Module populated with the STMicroelectronics^®  STM32MP15x microcontroller. Its universal design enables its insertion in a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch, or surface mount technology (SMT) connectors (all pitch 0.5 mm) aligning two sides of the board, allowing it to be plugged or soldered into any target application like a "big chip". 

The descriptions in this manual are based on the STMicroelectronics STM32MP157C. No description of compatible microcontroller derivative functions is included as such functions are not relevant for the basic functioning of the phyCORE‑STM32MP15x. Precise specifications for the controller populating the board can be found in the applicable controller technical reference manual or datasheet.

phyCORE‑STM32MP15x Features

The phyCORE‑STM32MP15x offers the following features:

• Insert-ready, sub-miniature (44 mm x 40 mm) System on Module (SOM) sub-assembly in low EMI design, achieved through advanced SMT technology

• Populated with the STMicroelectronics^® STM32MP157C^[1]microcontroller (TFBGA361 packaging)

• Up to 2 ARM-Cortex-A7 cores (clock frequency up to 800 MHz) + ARM-Cortex-M4 core up to 209 MHz
  
• Boot from different memory devices (SD card, QSPI NOR-Flash, NAND-Flash, eMMC)
• Controller signals and ports extend to two high-density pitch (0.5 mm) Samtec connectors aligning two sides of the board, enabling the phyCORE‑STM32MP15x to be plugged into any target applications like a "big chip"
• Single supply voltage of +5.0 V with on-board power management
• All controller-required supplies are generated on-board
• Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins

• 256 MB (up to 1 GB^[2]) 32-bit wide DDR3L RAM

• 4 GB (up to 32 GB^[2]) onboard eMMC, or 128 MB (up to 1 GB^[2]) onboard SLC NAND flash
• 4 MB (up to 16 MB^[2])Quad SPI NOR flash (bootable)
• 4 kB (up to 32 kB^[2]) I²C EEPROM
• 4x UART interfaces
• 2x High-speed USB 2.0 interfaces (1 x USB host and 1 x USB OTG)
• 1x 10/100/1000 Mbit/s Ethernet interface. Either with Ethernet transceiver on the phyCORE‑STM32MP15x, allowing for direct connection to an existing Ethernet network, or without an onboard transceiver and provision of the RGMII signals at TTL-level (10/100/1000 Mbit/s) at the phyCORE‑Connector instead^[1]
• 2x I²C interfaces
• 2x SPI interfaces (NAND/QSPI)
• 1x CAN FD interface
• 1x MIPI DSI interface
• 1x Parallel 18-bit RGB display interface with HDMI-CEC
• 1x 10-bit parallel camera interface
• 1x SAI Audio interface
• 1x MDIO interface

• 3x Secure Digital I/O MultiMediaCard interfaces (SDMMC) up to 8-bit (SD / eMMC / SDIO)

• Several dedicated GPIOs^[3]

• Several AD conversion and filter inputs digital (DFSDM)
• 2x 12-bit DAC outputs
• 1x JTAG/Serial-wire debug interface with trace ports and debug trigger I/Os
• I²C Real-Time Clock^[1] with a very low-power operation, independent from CPU-supply
• Power Management IC (PMIC)
• Available for different temperature grades (Product Temperature Grades)

phyCORE‑STM32MP15x Block Diagram

phyCORE‑STM32MP15x Component Placement

phyCORE‑STM32MP15x Minimum Operating Requirements

Pin Description

As the imagePinout of the phyCORE-Connector indicates, all controller signals selected extend to surface mount technology (SMT) connectors (0.5 mm). These connectors line two sides of the module (referred to as phyCORE-Connectors). This enables the phyCORE‑STM32MP15x to be plugged into any target application like a "big chip".

The numbered scheme for the phyCORE‑Connector is based on a two-dimensional matrix in which column positions are identified by a letter and row positions by a number. The pin numbering values increase as you move across the board from left to right. The numbered matrix can be aligned with the phyCORE‑STM32MP15x (viewed from above; phyCORE‑Connector pointing down) or with the socket of the corresponding phyCORE carrier board/user target circuitry. The upper left-hand corner of the numbered matrix (pin X1A1) is covered by the corner of the phyCORE‑STM32MP15x. The numbering scheme is always in relation to the PCB as viewed from above, even if all connector contacts extend to the bottom of the module.

The numbering scheme is consistent for both the module's phyCORE‑Connector as well as the mating connector on the phyCORE carrier board or target application. This reduces the risk of pin identification errors considerably.

Since the pins are precisely defined according to the numbered matrix described above, the phyCORE‑Connector is usually assigned a single designator for its position (X1 for example). This way, the phyCORE‑Connector comprises a single, logical unit regardless of the fact that it could consist of more than one physically socketed connector.

The following figure illustrates the numbered matrix system. It shows a phyCORE‑STM32MP15x with SMT phyCORE‑Connectors on its underside (defined with dotted lines) as it would be mounted on a carrier board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a cross-view of the phyCORE module showing these phyCORE‑Connectors mounted on the underside of the module’s PCB.

The Pinout table below provides an overview of the pinout of the phyCORE‑Connector X1 with signal names and descriptions specific to the phyCORE‑STM32MP15x.  It also provides the appropriate signal level interface voltages listed in the (Signal) Level column, (Signal) Type, as well as information regarding the controller pin. The signal type includes also information about the signal direction.^[4]A description of the signal types can be found in the table Signal Types.

In addition to the table in this manual PHYTEC provides a complete pinout table for the phyCORE‑STM32MP15x and PHYTEC carrier board as a downloadable Excel sheet (phyCORE-STM32MP1_Pinout_Table.A0_public.xls). This table includes signal names, pin muxing paths, and descriptions specific to the phyCORE‑STM32MP15x and the phyBOARD‑Sargas. It also provides the appropriate signal type and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found on a second tab sheet in the Excel file.

Jumpers

For configuration purposes, the phyCORE‑STM32MP15x has several solder jumpers, some of which have been installed prior to delivery. The figure below, Typical Jumper Pad Numbering Scheme, illustrates the numbering scheme for the various solder jumper pads.Jumper Locations (Top View)and  Jumper Locations (Bottom View) indicate the location and the default configuration of the solder jumpers on the board.

Table Jumper Settings provides a functional summary of the solder jumpers which can be changed to adapt the phyCORE‑STM32MP15x to specific design needs. It shows their default positions, and possible alternative positions and functions. A detailed description of each solder jumper can be found in the applicable chapter listed in the table.

If manual jumper modification is required, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable.  If soldered jumpers need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station, or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Pay special attention to the “TYPE” column to ensure you are using the correct type of jumper (0 Ohms, 10k Ohms, etc…). The jumpers are 0402 packages with a 1/8 W or better power rating. The jumpers (J = solder jumper) have the following functions.

Power

The phyCORE‑STM32MP15x operates off of a single power supply voltage. The following sections discuss the primary power pins on the phyCORE‑Connector X1 in detail.

Primary System Power (VCC5V_IN)

The phyCORE‑STM32MP15x is powered by a primary voltage supply with a nominal value of +5 V. On-board switching regulators generate the voltage supplies required by the STM32MP15x MCU and on-board components from the primary 5 V supplied to the SOM. For proper operation, the phyCORE‑STM32MP15x must be supplied with a voltage source of 5 V ±5 % with 3 A load at the VCC5V_IN pins on the phyCORE-Connector X1.

                VCC5V_IN:     X1 →  C58, C59, C60, D59, D60

Connect all +5 V VCC input pins to your power supply and all available GND pins. Please refer to section Pin Description for information on additional GND Pins located at the phyCORE‑Connector X1.

Power Management IC (PMIC) (U7)

The phyCORE‑STM32MP15x provides an onboard Power Management IC (PMIC) at position U7 to generate different voltages required by the microcontroller and the onboard components. The PMIC supports many functions such as different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the STM32MP15x via the onboard I²C bus (I2C4). The I²C address of the PMIC is 0x33.

External voltages:

• VCC5V_IN 5 V main supply voltage
• VBAT 3 V Backup Supply for RTC and STM32MP15x backup domain V_sw (optionally)
• VDD I/O supply voltage output
• VDD_BUCK4 PMIC BUCK4 converter output
• VDD_LDO1 PMIC LDO1 output

Supply Voltage for External Logic

The voltage level of the phyCORE’s logic circuitry is VDD (3.3 V), which is derived from the SOM main input voltage VDD5V_IN. In order to follow the power-up and power-down sequencing mandatory for the STM32MP15x, external devices have to be supplied by the I/O supply voltage VDD or VDD_BUCK4 (3.3 V) which is brought out at pin X1D56 (VDD) and pins X1C55 + X1C56 (VDD_BUCK4) of the phyCORE-Connector. The use of VDD ensures that external components are only supplied when the supply voltages of the STM32MP15x are stable.

VDD_BUCK4 (3.3 V / max. 1 A) output at pins X1C55 and X1C56 can be used also to supply external circuits connected to the phyCORE‑STM32MP15x.

Backup Power (VBAT)

To back up the RTC at U13 and, optionally, the STM32MP15x's backup domain V_sw, an external voltage source of 1.8 V to 3.6 V can be connected to VBAT pin D57.

If jumper J5 is closed at 1+2 (default setting), only the RTC at U13, which has an extremely low backup current consumption of typ. 40 nA  @3 V (max. 500 nA), is supplied by the backup source.

Additionally, it is possible to supply the STM32MP15x's internal RTC,  some registers, and SRAM  via backup domain V_swby the VBAT voltage if jumper J5 is set to 2+3.

Power Supply Supervisor

The STM32MP15x has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry coupled with a Brownout reset (BOR) circuitry. Two jumpers (J1 and J2) allow the configuration of the power supply supervisor.

• J1 connects PDR_ON either to VDD or to GND, enabling or disabling the power-down reset (PDR). If PDR is enabled the PDR supervisor monitors the VDD power supply. A reset is generated when VDD drops below a fixed threshold.
• J2 connects PDR_ON_CORE either to VDD or to GND, enabling or disabling the power-down reset VDDCORE (PDR_VDDCORE). If PDR_VDDCORE is enabled the PDR_VDDCORE supervisor monitors the VDDCORE power supply. A VDDCORE domain reset is generated when VDDCORE drops below a fixed threshold. 

The following configurations are possible:

CPU Core Frequency Scaling

The STM32MP15x on the phyCORE‑STM32MP15x is able to scale the clock frequency and voltage. This is used to save power when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as 'Dynamic Voltage and Frequency Scaling' (DVFS).

The phyCORE‑STM32MP15x BSP supports the DVFS feature. The Linux kernel provides a DVFS framework that allows each CPU core to have a min/max frequency as well as the applicable voltage and a governor that governs these values depending on the system load. Depending on the STM32MP15x variant used, several different frequencies are supported. Further details on how to configure this governor can be found in the phyCORE‑STM32MP15x BSP Manual.

Reset

The X_nRESET signal (Pin X1D61) on the phyCORE-Connector is designated as the reset input/output. Holding this pin low triggers a hard reset of the module. X_nRESET can be used to prevent the boot-up of the STM32MP15x. This can be used as a startup as described in the sectionPower Management IC. 

System Boot Configuration

Most features of the STM32MP15x microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

• Boot mode selection
• Boot device selection
• Boot device configuration

The internal ROM code is the first code executed during the initialization process of the STM32MP15x after POR. The ROM code detects the boot mode and configuration by using the boot mode pins (BOOT[2:0]).

Boot Mode Selection

The boot mode of the STM32MP15x microcontroller is determined by the configuration of three boot mode inputs BOOT[2:0] of the STM32MP15x during the reset cycle of the operational system.

Configuration circuitry (10 kΩ pull-up and pull-down resistors on jumpers J17 to J19 connected to BOOT[2:0]) is located on the phyCORE‑STM32MP15x so no further settings are necessary. The boot configuration of pins BOOT[2:0] on the standard phyCORE‑STM32MP15x module is 0b010. Consequently, the system will try to boot from eMMC first.

Additionally, the boot mode inputs are brought out at the phyCORE‑Connector pins X_BOOT[2:0] (X1C21, X1C20, X1C19). Hence, the specific boot configuration settings, which are set by the on-board configuration resistors, can be changed by modifying jumpers J17 to J19 on the module or by connecting a configuration resistor (e.g. <1 kΩ pull-up) to the BOOT signal pins at the phyCORE-Connector.

The table phyCORE-STM32MP15x Boot Modes shows the possible settings and the resulting boot configuration of the STM32MP15x.

System Memory

The phyCORE‑STM32MP15x provides five types of on-board memory:

• 1x bank of 32-bit DDR3L RAM: 256 MB (up to 1 GB)
• eMMC: 4 GB (up to 128 GB)
  or
  SLC NAND flash: 128 MB (up to 1 GB)
  
• Quad SPI NOR flash: 4 MB (up to 16 MB)
• I²C-EEPROM: 4 kB (up to 32 kB)

Details for each memory type used on the phyCORE‑STM32MP15x are below.

DDR3L-SDRAM (U8, U9)

The RAM memory of the phyCORE‑STM32MP15x is comprised of two 16-bit wide DDR3L-SDRAM chips (U8, U9). The memory devices are connected to the dedicated DDRPHYC SDRAM interface of the STM32MP15x microcontroller.

The DDR3-SDRAM memory is accessed starting at address 0xC000 0000.

The DDR memory subsystem of the STM32MP15x is composed of the  DDRCTRL and the DDRPHYC and provides a complete memory interface. Typically, the DDR3-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the DDRPHYC SDRAM interface and the DDRCTRL must be initialized by accessing the appropriate configuration registers on the STM32MP15x controller. Refer to the STM32MP15x Reference Manual to access and configure these registers.

Flash Memory (U1, U10)

Use of Flash as non-volatile memory on the phyCORE-SM32MP1 provides an easily reprogrammable means of code storage. The phyCORE‑STM32MP15x can be equipped with either an eMMC (U1) memory device or a NAND flash (U10) as non-volatile memory.

eMMC Memory (U1)

The main flash memory of the STM32MP15x is a managed NAND (eMMC) flash device populated at U1. The eMMC device is programmable with 3.3 V. No dedicated programming voltage is required. The eMMC Flash memory is connected to the second Secure digital input/output MultiMediaCard interface (SDMMC2) of the STM32MP15x. For more information about the SDMMC interfaces, please refer to the STM32MP15x Reference Manual.

If the phyCORE‑STM32MP15x is equipped with a NAND flash at U10 instead of the eMMC device (see next section), SDMMC2 is available at the phyCORE-Connector X1.

NAND Flash Memory (U10)

Alternatively to the eMMC memory at U1, a NAND flash can be populated at U10. The NAND Flash memory is connected to the STM32MP15x's Flexible Memory Controller (FMC) interface with a bus width of 8-bits. NCE1 (FMC_NCE/PG9) of the FMC interface selects the NAND Flash at U10. The FMC interface is also available at the phyCORE-Connector and can be used if no NAND flash is mounted on U10. These signals are available without changing the pin multiplexing of the phyCORE‑STM32MP15x.

The flash devices are programmable with 3.3 V. No dedicated programming voltage is required.

As of the printing of this manual, these NAND flash devices generally have a life expectancy of at least 100,000 erase/program cycles and a data retention rate of 10 years.

Any parts that are footprint (TSOP48) and functionally compatible may be used with the phyCORE‑STM32MP15x. 

NAND Flash Write Protection Control (J13)

Jumper J13 controls the write protection feature of the NAND flash at U10. Setting this jumper to position 1+2 protects the flash against write access during a power-on reset cycle. Setting this jumper to 2+3 protects the NAND flash permanently against write cycles.

The following configurations are possible:

Quad SPI NOR Flash (U11)

The QSPI NOR flash memory of the phyCORE‑STM32MP15x at U11 is available on most standard configurations of the SOM and can be used to store configuration data or any other general-purpose data. Besides this, it can also be used as a boot device and recovery boot device and is, therefore, suitable for applications that require a small code footprint or small RTOSes.

The device is connected to bank 1 of the STM32MP15x's Quad-SPI interface (QUAD SPI) and can be accessed through QUADSPI_BK1_NCS. The control registers for QSPI are mapped between addresses 0x58003000 and 0x58003FFF. Please see the STM32MP15x Reference Manual for detailed information on the registers.

In order to allow connecting an external Quad SPI flash if the phyCORE‑STM32MP15x comes without an onboard Quad SPI flash, the QSPI signals are available at phyCORE-Connector X1.

As of the printing of this manual, these SPI Flash devices generally have a life expectancy of at least 100,000+ erase/program cycles and a data retention rate of 20 years. This makes the OSPI NOR flash a reliable and secure solution to store the first and second-level bootloaders.

I²C EEPROM (U12)

The standard configuration of the phyCORE‑STM32MP15x is populated with a non-volatile 4 kB I²C EEPROM at U12. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I²C port 4 on the STM32MP15x. The control registers for I²C port 4 are mapped between addresses 0x5C002000 and 0x5C0023FF. Please see the STM32MP15x Reference Manual for detailed information on the registers.

The I²C EEPROM populating the phyCORE‑STM32MP15x has the ability to configure the address for the memory area and the additional ID page using chip-enabled signals E0 to E2. The four upper address bits of the device are fixed at ‘1010’ (see M24C32 datasheet). Chip-enable signals E0 to E2 are fixed and connected to GND. Thus the resulting addresses are 0x50 for the memory array and 0x58 for the additional ID page.

EEPROM Write Protection Control (R23)

Mounting a 10 kΩ resistor at R23 will cause the EEPROM to enter write-protect mode, thereby disabling write access to the device. In the default configuration resistor, R23 is not mounted which means write access to the device is allowed.

The following configurations are possible:

Serial Interfaces

The phyCORE‑STM32MP15x provides numerous dedicated serial interfaces, some of which are equipped with a transceiver/PHY to allow direct connection to external devices, others can be muxed to other pins. The STM32MP15x has some more interfaces that can be used by individual pin muxing. This chapter only describes the predefined interfaces.

1. 1x High-speed USB OTG interface (extended directly from the second port of the STM32MP15x's USB high-speed PHY)
2. 1x High-speed USB host interface (extended directly from the first port of the STM32MP15x's USB high-speed PHY)
3. 1x Gbit Ethernet interface
4. 2x I²C interfaces
5. 1x Serial Peripheral Interfaces (SPI)
6. 3x UART interfaces
7. 2x CAN FD interfaces
8. 3x SDIO interfaces
9. 1x SAI interface

The following sections of this chapter detail each of these serial interfaces and any applicable configuration jumpers.

USB OTG Interface

The phyCORE‑STM32MP15x provides a high-speed USB OTG interface that uses the STM32MP15x's embedded high-speed USB OTG IP-Core connected to the second port of the embedded USB high-speed PHY. The USB OTG IP-Core supports both device and host functions and is fully compliant with the On-The-Go Supplement to the USB 2.0 specification. It can also be configured as a host-only or device-only controller. An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for USB OTG) connector is all that is needed to interface the phyCORE‑STM32MP15x USB OTG functionality. The applicable interface signals can be found on the phyCORE-Connector X1 as shown in the following table.

USB host Interface

The phyCORE‑STM32MP15x provides a high-speed USB OTG interface that uses the STM32MP15x's embedded high-speed USB OTG IP-Core connected to the second port of the embedded USB high-speed PHY. The USB OTG IP-Core supports both device and host functions and is fully compliant with the On-The-Go Supplement to the USB 2.0 specification. It can also be configured as a host-only or device-only controller. An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for USB OTG) connector is all that is needed to interface the phyCORE‑STM32MP15x USB OTG functionality. The applicable interface signals can be found on the phyCORE-Connector X1 as shown in the following table.

Ethernet Interface

Connection of the phyCORE‑STM32MP15x to the World Wide Web or a local area network (LAN) is possible using the onboard GbE PHY at U3. It is connected to the RGMII interface (ETH1) of the STM32MP15x. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. Alternatively, the RGMII (ETH1) interface which is available on the phyCORE-Connector can be used to connect an external PHY. In this case, the onboard GbE PHY (U3) must not be populated (section RGMII Interface).

Ethernet PHY (U3)

With an Ethernet PHY mounted at U3, the phyCORE‑STM32MP15x has been designed for use in 10Base-T, 100Base-T, and 1000Base‑T networks. The 10/100/1000Base‑T interface with its LED signals extends to phyCORE‑Connector X1.

The onboard GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface (ETH1) of the STM32MP15x. Please refer to the STMicroelectronics STM32MP15x Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (X_ETH_A±, X_ETH_B±, X_ETH_C±, X_ETH_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.

Ethernet PHY GPIOs

The Ethernet PHY mounted on the phyCORE‑STM32MP15x provides two additional GPIOs. These are available at pins D45 (X_ETH_GPIO0) and D46 (X_ETH_GPIO1) of the phyCORE‑Connector X1. They can be configured by the appropriate registers of the Ethernet PHY.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑STM32MP15x can be found on a  sticker (with 2D matrix code) attached to the module. This number is a 12-digit HEX value. 

The MAC address of the module is also programmed in the appropriate OTP (STM32MP15x's on-chip one-time programmable memory). Assigned OTP registers in the STM32MP15x:
OTP_57[31:0] = MAC_ADDR[31:0]
OTP_58[15:0] = MAC_ADDR[47:32]

RGMII Interface

In order to use an external Ethernet PHY instead of the on-board GbE PHY at U3, the RGMII interface (ETH1) of the STM32MP15x is brought out at phyCORE‑Connector X1.

I2C Interface

The Inter-Integrated Circuit (I2C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The STM32MP15x contains several identical and independent multi-master fast-mode plus I2C modules. They are multiplexed with other signals. Please check the STMicroelectronics STM32MP15x Reference Manual for further information. One of these I2C modules (I2C4) is used on the phyCORE STM32MP15x and is available at phyCORE-Connector X1. A second one (I2C1) is predefined for external usage. The following table lists the I2C ports on the phyCORE-Connector:

I2C4 is used for SOM internal PMIC communication and should not be used for external devices.

SDIO Interface

The SDIO interfaces can be used to connect external SD cards, eMMC, or any other device requiring an SDIO interface (i.e Wi‑Fi, I/O expansion, etc.) The phyCORE bus features three SDIO interfaces. One of the phyCORE‑STM32MP15x SD interfaces (SDMMC2) supports 8-bit bus width and is internally used for eMMC.

The tables below show the location of the different interface signals on the phyCORE-Connector. 

Universal Asynchronous Interface

The phyCORE‑STM32MP15x provides several high-speed universal asynchronous interfaces. Only three are described here as U(S)ARTs. Please refer to the STMicroelectronics STM32MP15x Reference Manual or Pin Muxing Tool if you need more U(S)ARTs. The following tables show the location of the signals on the phyCORE-Connector.

CAN FD Interface

The STM32MP15x provides two CAN FD interfaces (FDCAN1 and FDCAN2). These CAN FD interfaces are available on the phyCORE-STM32MP15x connector X1.

SPI Interface

The STM32MP15x provides one dual-mode Quad-SPI interface (QSPI) and up to six SPI interfaces. The Quad interface (QSPI-BK1) is directly connected to an optional on-board OSPI Flash (U11) see chapter 9.4.  One SPI interface (SPI1) is predefined on the connector X1.

Audio Interface (SAI)

The Synchronous Audio Interface (SAI) on the phyCORE-STM32MP15x is a full-duplex, serial interface that enables communication with a variety of serial devices such as standard codecs signal digital processors (SDPs), microprocessors peripherals, and popular industry audio codecs that implement the inter-IC sound bus standard (I2S), PDM and SPDIF standard. The STM32MP15x provides different possibilities of using the SAI modules.

The main purpose of this interface is to connect to an external codec, such as I2S. The SAI is intended to be used in synchronous mode. The tables below show the locations of the SAI2 sources:

General Purpose I/Os

All STM32MP15x port pins not used by any of the other interfaces can be muxed and used as GPIO without harming other features of the phyCORE‑STM32MP15x:

Besides these pins, most of the STM32MP15x signals which are connected directly to the module connector can be configured to act as GPIOs, due to the multiplexing functionality of most controller pins. Normally, pins with signal type I/O are able to work as a GPIO.

ADC, DAC, and Filter Inputs

The STM32MP15x provides analog-to-digital conversation and vice versa as well as digital filters for sigma-delta modulators (DFSDM). The pin muxing and the pin assignment of the phyCORE-Connector allow these features to be used.

Analog-to-Digital Conversion Inputs

The Analog-to-Digital conversion inputs provide 4 analog input signals. The table below lists the location of the analog input signals and possible functions assigned to them.^[3]

Jumper J14 allows the voltage source for the analog inputs' reference voltage (VREF) at X1C15 to be connected directly on the SOM to the analog supply (VDDA).  VDDA can be supplied by VDD (J16=default) or via VDDA from PMIC-LDO5 (J15). see Jumper J14, J15, and J16 in Jumpers.

DFSDM Interface

The STM32MP15x provides a filter for the sigma-delta modulator (DFSDM) with up to 8 channels/6 filters. On the phyCORE-STM32MP15x are 3 data inputs with a clock signal to use the DFSDM interface at X1.

Debug Interface

The phyCORE‑STM32MP15x is equipped with a JTAG/Serial-wire debug interface to control the STM32MP15x's debug features with industry-standard debugging tools. It allows downloading program code into the external flash, internal controller RAM, or debugging programs currently being executed.

A trace port allows data to be captured for logging and analysis. Additionally, trigger pins and two LEDs facilitate debugging.

JTAG/Serial-Wire Debug Interface

The location of the JTAG and Serial-wire debug interface pins on the phyCORE-Connector X1 are shown in the table below:

Debug Trigger / Status LEDs

The phyCORE‑STM32MP15x features two debug trigger pins and two status LEDs. 

The two LEDs D1 (green) and D2 (red) are connected to PA14 and PA13, respectively. 

D1 indicates the following statuses:

• During the boot phase, in case of boot failure, the PA13 pin is set to low open-drain and LED D2 lights bright.
• During UART/USB boot, the PA13 pin toggles open-drain at a rate of about 5 Hz until a connection is started and LED D2 blinks fast.
• With BOOT[2:0] = 0b100 (no boot, used for specific debug), PA13 toggles open-drain at a rate of about 5 kHz, LED D2 lights weak.
• In all other cases, the PA13 is kept in its reset value, that is high-z until the software setting, LED D2 is off.

The behavior of the green LED D1 at the external trigger input PA14 depends on the type of signal applied to this port.

Please refer to application note AN5031 from ST for more information regarding the use of the debug trigger ports.

UART Virtual Com Port

The phyCORE‑STM32MP15x uses UART4 to support debugging if a virtual com port is needed as an addition to the JTAG interface. UART4 also works as a standard console in the Linux BSP.

Hardware Debug Port (HDP)

The Hardware Debug Port allows the observation of internal signals. By using multiplexers, up to 16 signals for each 8-bit output can be observed. All STM32MP15x hardware debug port signals are available at the phyCORE‑Connector as an alternate function. Please make sure that a port is not mandatory for the function of the phyCORE-STM32MP15x before changing the muxing to use the Hardware Debug Port feature. More information about the Hardware Debug Port can be found in the STM32MP15x Reference Manual.

Display Interfaces

The phyCORE‑STM32MP15x provides an 18-bit parallel digital RGB (Red, Green, Blue) and a MIPI DSI interface to connect appropriate displays to the module.

Parallel Display Interface

The STM32MP15x provides a 24-bit parallel digital RGB (Red, Green, Blue) display interface and delivers signals up to WXGA (1366×768) @60 fps resolution. All signals are available at different controller ports as alternate functions. As some of the controller ports are needed for other functions, the parallel display interface of the phyCORE‑STM32MP15x is specified as an 18-bit interface only. The table below shows the location of the specified display interface signals on the phyCORE-Connector.

Supplementary Signals

In addition, signal X_LCD_BL_PWM/PI0 can be used as PWM output to control the display backlight.

The STM32MP15x embeds an HDMI-CEC controller that provides hardware support for the consumer electronics control (CEC) protocol. The HDMI-CEC signal is available at the phyCORE‑Connector and can be used together with the parallel RGB display signals to build an HDMI interface with the CEC feature. 

The table below shows the location of the two supplementary signals on the phyCORE‑Connector.

MIPI DSI (Display Serial Interface)

If the phyCORE‑STM32MP15x is equipped with an STM32MP157x  microprocessor a MIPI DSI interface with 2 data lanes up to 1 GHz each is also available to connect a display to the module. The table below shows the location of the MIPI display interface signals on the phyCORE‑Connector.

Parallel Camera Interface (DCMI)

The STM32MP15x offers one synchronous parallel camera interface (DCMI) that can receive high-speed data flows with up to 14 data lines (D13-D0) and a pixel clock line (DCMI_PIXCLK) with a programmable polarity so that data can be captured on either the rising or the falling edge of the pixel clock.

On the phyCORE‑STM32MP15x  the camera interface is brought out as parallel interfaces with 10 data bits, HSYNC, VSYNC, and PIXCLK. The upper DCMI data bits D13... D10 are used for other features of the phyCORE‑STM32MP15x.

The locations of the parallel camera interface signals are shown below:

Real-Time Clocks (RTCs)

For real-time or time-driven applications, the phyCORE‑STM32MP15x provides two RTCs. Besides the internal RTC of the STM32MP15x, the phyCORE-STM32MP15x has an external RTC mounted at U13.

The RTCs are supplied by the main system power if available. When the main system power is off they can also be powered by a secondary voltage source of 1.8 V to 3.6 V (typ. 3 V) connected to VBAT (D57). The VBACKUP input of the external RTC is permanently connected to VBAT while jumper J5 must be closed at 2+3 to connect the STM32MP15x's VBAT input, too. 

RTC of the STM32MP15x

The signals of the STM32MP15x's on-chip RTC are available at phyCORE-Connector X1. 

The following table lists the signals of the RTC  on the phyCORE-Connector: