FPSC Gamma Feature Set Specifications (LAN-118e.A7)
Document Title	FPSC Gamma (Lite) Feature Set Specifications (LAN-118e.A7)
Document Type	Hardware Application Note
Article Number	LAN-118e.A7
Release Date	26.05.2026
Is Branch of	FPSC Gamma Feature Set Specifications (LAN-118e.Ax) Head

FPSC Gamma (Lite) Feature Set Introduction

The FPSC (Future Proof Solder Core) Gamma and Gamma Lite feature set specification provides a concise and versatile system on module (SOM) definition. It allows for easy swapping between FPSC Gamma (Lite) SOMs while minimizing the amount of redesign needed for your hardware solution. The FPSC definition details a set of mandatory and optional interfaces commonly found in numerous processors. As many of these interfaces as possible are brought out to a consistent pinout to maximize compatibility between FPSC modules. The specification also defines a set of specialized pins that allow non-standard, processor-specific functionality to be brought out. Following the FPSC specification allows you to enjoy flexibility and reliability in future projects. The FPSC module footprint is optimized for size and price and provides a high production yield thanks to its stable solder joints. The FPSC footprint is divided into several zones. Core functionalities are in the center zones. Optional or future processor features can be routed to the outer zone pins. The pin-compatible design of the FPSC enables product variants and upgrades across processor boundaries without impairing functionality.

This specification directs the design of an FPSC Gamma (Lite) Feature Set System on Module (SOM) by providing detailed information on its functionality, pinout, and physical and electrical definitions. For information about soldering down an FPSC unit, refer to the soldering guide.

Soldering Guide - FPSC-Based Products Fused Tin Grid Array (FTGA) Information (LAN-128e.A4)

FPSC Physical Advantages

Solder joint geometry ensures maximum ruggedness and force distribution
Vibration and shock tests according to the EN 60068-2 series of standards confirm robustness
Fused Tin Grid Array (FTGA) soldering technology compensates for coplanar deviations between the module and baseboard
Bilateral solder reservoirs minimize the risk of faulty solder joints

FPSC Feature Set Module Universal Pinout

The FPSC Gamma (Lite) universal pinout ensures all mandatory and optional interfaces are brought out at the same pins
Modules designed with the gamma lite feature set are pin-compatible, and mandatory features are fully interchangeable
The mandatory features are centralized in the core area, which allows you to maintain a smaller footprint while maintaining full compatibility

Documentation and Standard References

CAN Specification: ISO 11898-1:2015 Road vehicles - Part 1: Data link layer and physical signaling, (iso.org)
MIPI CSI-2 Specification: The MIPI CSI-2 standard is owned and maintained by the MIPI Alliance (mipi.org)
MIPI DSI Specification: The DSI standard is owned and maintained by the MIPI Alliance (mipi.org)
eMMC Specification: The eMMC electrical standard is defined by JEDEC JESD84-B51A and the mechanical standard by JESD84-C44 (jedec.org)
ETH Specification: IEEE1588 - 2008. IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (standards.ieee.org)
HDMI Specification: Version 2.0a, November 28, 2017 (hdmi.org)
I2C Specification: Version 6.0, April 4th 2014, Philips Semiconductor (now NXP) (nxp.com)
I2S Bus Specification: Feb. 1986 and Revised June 5, 1996, Philips Semiconductor (now NXP) (www.nxp.com)
JTAG Specification: This is defined by IEEE 1149.1-2001 - IEEE Standard Test Access Port and Boundary Scan Architecture (ieeexplore.ieee.org)
PCIe Specification: (pci-sig.org)
SD Specification: Part 1 Physical Layer Simplified Specification 00, SD Group and SD Card Association (“Secure Digital”) (www.sdcard.org)
USB Specification: (www.usb.org)

FPSC Definition Overview

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this specification. Use the table below to navigate unfamiliar terms used in this document.

Abbreviation/Acronym	Definitions
CAN	Controller Area Network
CSI	Camera Serial Interface
DSI	Display Serial Interface
eMMC	Embedded Multimedia Card
EEPROM	Electrically Erasable Programmable Read-only Memory
Ethernet-PHY	Ethernet Physical Layer
FPSC	Future Proof Solder Core
FTGA	Fused Tin Grid Array
GPIO	General-Purpose Input/Output
HDMI	High Definition Multimedia Interface
HMI	Human-Machine Interface
I2C	Inter-Integrated Circuit
JTAG	Joint Test Action Group (a serial bus protocol usually used for test purposes)
LPDDR	Low Power Double Data Rate
LVDS	Low Voltage Differential Signaling
OTG	On The Go
PCB	Printed circuit board
PCI	Peripheral Component Interconnect
PCIe	PCI express
PMIC	Power management IC
POR	Power-on reset
PWM	Pulse-width Modulation
RGMII	Reduced Gigabit Memory Independent Interface
RTC	Real-time clock
SDIO	Secure Digital Input Output
SOM	System on Module
SPI	Serial Peripheral Interface
TOF	Time of Flight
TSN	Time Sensitive Networking
UART	Universal Asynchronous Receiver/Transmitter
USB	Universal Serial Bus

FPSC Abbreviations/Acronyms

FPSC Interface Summary

The full list of SOM functionality and interfaces defined by the FPSC Gamma (Lite) Feature Set is listed below. Please note that some of the interfaces are optional. Both the availability and the total number of available optional interfaces depend on the specific SOM being used. A full breakdown of how interfaces are defined can be found in Requirement Parameters.

Functionality

Mass Storage (e.g., eMMC or NAND)

Each SOM has integrated, non-volatile mass storage. The specific technology (such as eMMC or NAND) depends on the SOM, while the storage size and speed are variable via configuration options.

Ethernet-PHY

An Ethernet-PHY is fully integrated into the SOM. To implement an Ethernet interface on the baseboard, all that is needed is a transformer (magnetics) and a suitable socket (typically an RJ-45).

EEPROM

An EEPROM for storing SOM-specific information, e.g., for the bootloader and customer-specific project data, is always available.

RTC

Each SOM has an integrated RTC and allows, among other things, the system time to be maintained when the system is switched off.

Watchdog

All SOMs feature a hardware watchdog with a dedicated signal output that triggers a hard reset of the module if not regularly serviced by the software.

Interfaces

System and Power Management

Reset in and out signals
4x boot mode pins
Primary power in
Carrier board power out
Power control in and out
1x JTAG interface

General Purpose I/O

7x GPIO signals
4x PWMs

Audio Interface

1x Serial Audio Interface

Quad SPI Interface

1x Quad SPI Interface

SDIO Interfaces

1x SDIO interface configured for SD card boot
1x 4-bit SDIO interface for general use

CAN Interfaces

3x CAN Interfaces

I2C/I3C Interfaces

1x I2C for internal use
4x I2C interfaces for general use
1x I3C interface
If present, it overrides one of the I2C interfaces

SPI Interfaces

3x SPI interfaces

UART Interfaces

1x Primary Debug UART
Standardized serial interface for outputting boot messages and communicating with the bootloader or kernel console on UART3.
1x General Purpose UART
1x Special Debug UART
Debug interface, e.g., for integrated co-processors on UART2.

PCIe Interfaces

2x PCIe interfaces

Display Interfaces

2x LVDS interfaces
1x HDMI Interface
1x DSI Interface

Camera Interfaces

2x CSI Interfaces

RGMII Interfaces

1x RGMII interface

USB Interfaces

2x USB Interfaces
- May support either USB 2.0 or USB 3.0

Gamma vs. Gamma Lite

The FPSC Gamma Feature Set defines a comprehensive set of mandatory interfaces that maximize pin-level compatibility between modules. This feature set is one of the central ways in which the FPSC standard differs from competing SOM specifications. To maintain this high level of compatibility while accommodating modern processor portfolios, the specification introduces a second, fully aligned variant: Gamma Lite.

Gamma Lite has an identical universal pinout, mechanical footprint, and electrical definition to Gamma. The mandatory interfaces of Gamma Lite are a strict subset of those of Gamma, and all signals are routed to the same pin locations. In practice, only one or two interfaces relaxed by Gamma Lite are typically absent from a given processor; the remaining interfaces are implemented on the module and connected to their defined pins. Therefore, a baseboard designed for Gamma Lite is compatible with every Gamma module. A baseboard that does not rely on the reduced interfaces can freely mix and match modules from both feature sets.

The Gamma Lite variant relaxes the mandatory requirement for the following interfaces, none of which are universally supported across the targeted processor landscape:

CAN (CAN1, CAN2) — Mandatory in Gamma, Optional in Gamma Lite
MIPI CSI (CSI1 2-lane) — Mandatory in Gamma, Optional in Gamma Lite
RGMII (RGMII2, second Ethernet) — Mandatory in Gamma, Optional in Gamma Lite
LVDS (LVDS1) — Mandatory in Gamma, Optional in Gamma Lite
USB 2.0 (USB2) — Mandatory in Gamma, Optional in Gamma Lite

A complete, signal-level comparison is provided in the Gamma/Gamma Lite columns of Table 2 (see Section 2.1).

Rationale: While some application processors are highly attractive, including current and emerging SoCs in the ARM Cortex and i.MX families, they do not implement the entire Gamma mandatory feature set. Instead of excluding these processors from the FPSC ecosystem, Gamma Lite provides them to customers under a clearly defined, fully pin-compatible specification. The full Gamma mandatory feature set remains unchanged to preserve the strong, predictable compatibility between Gamma modules, which is a key value proposition of the FPSC standard and a central differentiator from alternative SOM standards, such as OSM.

Selecting Between Gamma and Gamma Lite.

Choose Gamma if the application requires the full mandatory interface guarantee, including dual CAN, MIPI CSI camera input, a second Gigabit Ethernet RGMII2, LVDS1, and a second USB 2.0, as well as the broadest possible interchangeability across the Gamma module portfolio.
Choose Gamma Lite when the application does not depend on one or more of the relaxed interfaces, and when access to the wider pool of processors covered by Gamma Lite is more important than the strict Gamma mandatory guarantee. Gamma Lite baseboards are fully compatible with all Gamma modules.

The universal pinout ensures that today's design decisions do not preclude tomorrow's upgrade paths. Customers can move between Gamma and Gamma Lite modules, as well as between processor generations, with minimal or no baseboard redesign..

FPSC Feature Set Requirements

FPSC Interface/Signal Types

The FPSC Gamma (Lite) Feature Set Specification uses the terms Mandatory, Optional, and Specialized to define requirement parameters for interfaces in the FPSC Gamma (Lite) Feature Set Specification. How these definitions are applied to interfaces is described below:

Mandatory

This interface is considered core functionality, is supported on all FPSC Gamma (Lite) SOMs, and must be brought out to its defined pins.

Optional

This interface is not strictly necessary, but it is commonly supported by many processors and will be brought out to its defined pins if possible.

Specialized

This interface is not defined by the FPSC Gamma (Lite) Feature Set specification and allows the use of new, special, and/or unique processor features not subject to standardization. This opens up a potential incompatibility with other FPSC Gamma (Lite) SOMs.

Please note that sometimes a signal may not share the same requirements as its interface. This primarily occurs with some Mandatory interfaces containing Optional signals. The lack of these signals may alter the functionality of the interface, but the high level requirement of the interface will be maintained across FPSC SOMs.

The Mandatory, Optional, and Specialized interfaces for an FPSC Gamma (Lite) SOM are summarized in the table below.

Feature	Sub-Feature	Gamma Requirement	Gamma Lite Requirement	Notes
PWR/CTRL	Boot mode	Mandatory	Mandatory
	JTAG	Mandatory	Mandatory	TRST and MOD signals are Optional/Specialized
	Power Rails	Mandatory	Mandatory
	Reset/Control Signals	Mandatory/Optional	Mandatory/Optional	A mix of Mandatory and Optional signals.
GPIO/PWM	GPIO1-4	Mandatory	Mandatory
	GPIO5-7	Optional	Optional
	PWM1-2	Mandatory	Mandatory
	PWM3-4	Optional	Optional
SAI	SAI1	Mandatory	Mandatory	MCLK is Optional
QSPI		Mandatory	Mandatory	DQS is Optional
ADC		Optional	Optional
SD Card/SDIO	SD Card	Mandatory	Mandatory	WE is Optional
SD Card/SDIO	SDIO	Optional	Optional
CAN	CAN1	Mandatory	Optional
	CAN2	Mandatory	Optional
	CAN3	Optional	Optional
I2C	I2C1	Mandatory	Mandatory	Do not use! Used internally by SoM
	I2C2	Mandatory	Mandatory
	I2C3	Mandatory	Mandatory
	I2C4	Optional	Optional
	I2C5	Optional	Optional
SPI	SPI1	Mandatory	Mandatory
	SPI2	Mandatory	Mandatory
	SPI3	Optional	Optional
UART	UART1	Mandatory	Mandatory
	UART2	Mandatory	Mandatory	Special Debug Interface
	UART3	Mandatory	Mandatory	Primary Debug Interface
PCIe	PCIE1	Optional	Optional
PCIe	PCIE2	Optional	Optional
LVDS	LVDS1	Mandatory	Optional
	LVDS2	Optional	Optional
HDMI		Optional	Optional
DSI	DSI	Optional	Optional	Supports two or four data lanes
CSI	CSI1 - 2-lane	Mandatory	Optional	Supports two data lanes
	CSI1 - 4-lane	Optional	Optional	Supports four data lanes
	CSI2	Optional	Optional	Supports two or four data lanes
Ethernet	ETH1	Mandatory	Mandatory	Gigabit Phy on SoM
RGMII	RGMII2	Mandatory	Optional	Event pins are Optional
USB	USB1 2.0	Mandatory	Mandatory	USB1_ID is Optional
	USB1 3.0	Optional	Optional
	USB2 2.0	Mandatory	Optional	USB2_ID is Optional
	USB2 3.0	Optional	Optional
Ground		Mandatory	Mandatory

Requirement Parameters

Pinout

The following tables and sections define the pinout of the FPSC Gamma (Lite) specification. Two or more instances of an interface are numbered starting from 1, and the ordering is determined by:

Bootability: If the SOM supports booting through this interface, the boot-capable interface is listed first.
After any bootable interfaces, the remaining interfaces are listed by the maximum achievable data rate of the interface, starting with the fastest.

The signal voltage level, direction, and presence of pull-ups are defined from the SOM’s perspective. Any additional external circuitry required for a signal is noted..

PWR/CTRL

Boot Source Selection

The FPSC Gamma (Lite) feature set provides four signals for selecting the boot source: BOOT_MODE1, BOOT_MODE2, BOOT_MODE3, and BOOT_MODE4. The processor evaluates the boot mode in relation to the value of these boot mode pins on the rising edge of nRESET_OUT. If the boot source selection signals on the baseboard are not connected, an internal mass storage device, as determined by the on-board pull-ups, is set as the default boot source for the user-stage bootloader.

The following list includes the possible boot sources for the user-stage boot loader. Note that not all SoMs support all boot sources; refer to the individual SoM documentation for specifics on capabilities and voltage selection.

(SOM) internal NOR-Flash
(SOM) internal eMMC
(SOM) internal Bootfuses (referring to another boot source)
SD-Card
Ethernet
USB-Serial
USB-Mass Storage
UART

If there are multiple instances of an interface and one of them is boot capable, the first listed interface will be the boot-capable interface. The user-stage bootloader may provide additional options for loading the operating system (e.g., kernel and file system).

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	PU	Signal Descriptions	Notes
P25	BOOT_MODE1	Mandatory	Mandatory	IN	1.8V		Boot mode control pin 1	Use <=1kOhm PU (1.8 V) or PD resistors on the baseboard to select the boot source. Check the HW Manual for the SOM for valid boot modes.
R24	BOOT_MODE2	Mandatory	Mandatory	IN	1.8V		Boot mode control pin 2
T25	BOOT_MODE3	Mandatory	Mandatory	IN	1.8V		Boot mode control pin 3
U24	BOOT_MODE4	Mandatory	Mandatory	IN	1.8V		Boot mode control pin 4
AC20	JTAG_TCK	Mandatory	Mandatory	IN	1.8V		JTAG Test Clock
AC22	JTAG_TDI	Mandatory	Mandatory	IN	1.8V		JTAG Test Data Input
AD25	JTAG_TDO	Mandatory	Mandatory	OUT	1.8V		JTAG Test Data Output
AC24	JTAG_TMS	Mandatory	Mandatory	IN	1.8V		JTAG Test Mode Select
AE24	JTAG_TRST	Optional	Optional	IN	1.8V		JTAG Reset
U22	nPWRREADY_OUT	Mandatory	Mandatory	OD_OUT	<=12V		nPWRREADY_OUT is driven low when all power rails on the SOM are properly brought up. Once asserted, use nPWRREADY_OUT to control the power sequencing of your CB. See Power Sequencing on page 48 for details.	Active-Low signal. Requires an external pull-up resistor. It is recommended to connect this pullup to the SOM input voltage, but it can support voltages as high as 12V.
Y21	nRESET_IN	Mandatory	Mandatory	OD_IN	1.8V to VCC_IN	10K	When nRESET_IN is asserted low, the SOM performs a cold reset/power cycle. See Power Sequencing on page 48 for details.	Active-Low signal.
R22	nRESET_OUT	Mandatory	Mandatory	OD_OUT	1.8V	10K	nRESET_OUT is internally connected to the processor and the PMIC and is the primary reset output of the SOM. When nRESET_OUT is asserted high, the processor will latch the boot mode pins and begin booting. See Power Sequencing on page 48 for details.	Active-Low signal.
R20	ON/OFF	Optional	Optional	OD_IN	1.8V	100K	Wake up and power off pin of the processor. Refer to the processor's datasheet for further information.
U20	RTC_CLKOUT	Optional	Optional	OUT	1.8V		Clock output of the SOM RTC
T21	RTC_nINT	Mandatory	Mandatory	OD_OUT	1.8V		Interrupt the output of the SOM RTC.	Active-Low signal. Requires an external pull-up resistor.
AA20	VCC_1V8_OUT1	Mandatory	Mandatory	PWR_OUT	1.8V		1.8V Voltage output for general use	Combined current draw of at least 200 mA across pins
AB21	VCC_1V8_OUT2	Mandatory	Mandatory	PWR_OUT	1.8V		1.8V Voltage output for general use	Combined current draw of at least 200 mA across pins
AA24	VCC_3V3_OUT1	Mandatory	Mandatory	PWR_OUT	3.3V		3.3V Voltage output for general use	Combined current draw of at least 200 mA across pins
AB25	VCC_3V3_OUT2	Mandatory	Mandatory	PWR_OUT	3.3V		3.3V Voltage output for general use	Combined current draw of at least 200 mA across pins
L24	VCC_IN1	Mandatory	Mandatory	PWR_IN	5.0V		5V-DC Input Voltage	Some SOMs are capable of 3.3V. However, powering the board via 3.3V will cause your design to be considered out of the FPSC spec.
M25	VCC_IN2	Mandatory	Mandatory	PWR_IN	5.0V
N24	VCC_IN3	Mandatory	Mandatory	PWR_IN	5.0V
L22	VCC_IN4	Mandatory	Mandatory	PWR_IN	5.0V
N22	VCC_IN5	Mandatory	Mandatory	PWR_IN	5.0V
M21	VCC_IN6	Mandatory	Mandatory	PWR_IN	5.0V
N20	VCC_IN7	Mandatory	Mandatory	PWR_IN	5.0V
P21	VCC_IN8	Mandatory	Mandatory	PWR_IN	5.0V
AA22	VCC_RTC	Mandatory	Mandatory	PWR_IN	3.0V		RTC Input Voltage	Connect a gold cap or a battery to the CB. The RTC is functional between 1.1V and 5.5V. If a battery is used, make sure that the RTC trickle charger is deactivated.

FPSC PWR/CTRL Signal Locations

GPIO/PWM

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions
N40	GPIO1	Mandatory	Mandatory	I/O	1.8V	GPIO Pin 1
L40	GPIO2	Mandatory	Mandatory	I/O	1.8V	GPIO Pin 2
AL32	GPIO3	Mandatory	Mandatory	I/O	1.8V	GPIO Pin 3
AL34	GPIO4	Mandatory	Mandatory	I/O	1.8V	GPIO Pin 4
AN30	GPIO5	Optional	Optional	I/O	1.8V	GPIO Pin 5
AN32	GPIO6	Optional	Optional	I/O	1.8V	GPIO Pin 6
AN34	GPIO7	Optional	Optional	I/O	1.8V	GPIO Pin 7
N48	PWM1	Mandatory	Mandatory	OUT	1.8V	General PWM 1
N58	PWM2	Mandatory	Mandatory	OUT	1.8V	General PWM 2
AL42	PWM3	Optional	Optional	OUT	1.8V	General PWM 3
AN52	PWM4	Optional	Optional	OUT	1.8V	General PWM 4

FPSC GPIO/PWM Signal Locations

SAI/I2S

The FPSC Gamma Feature Set defines one Mandatory SAI that supports full-duplex serial interfaces with frame synchronization across various audio formats, including I2S, AC97, and TDM.
The FPSC Gamma Light defines oneMandatory I2S interface that supports full-duplex serial audio communication with shared clock and frame synchronization signals.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions
AJ32	SAI1_MCLK	Optional	Optional	OUT	1.8V	SAI1 Master Clock
AG32	SAI1_RX_SYNC	Mandatory	Optional	IN	1.8V	SAI1 Receive Frame Sync
AG28	SAI1_RX_BCLK	Mandatory	Optional	IN	1.8V	SAI1 Receive Bit Clock
AG30	SAI1_RX_DATA	Mandatory	Mandatory	IN	1.8V	SAI1 Receive Data
AJ30	SAI1_TX_SYNC	Mandatory	Mandatory	OUT	1.8V	SAI1 Transmit Frame Sync
AH29	SAI1_TX_BCLK	Mandatory	Mandatory	OUT	1.8V	SAI1 Transmit Bit Clock
AJ28	SAI1_TX_DATA	Mandatory	Mandatory	OUT	1.8V	SAI1 Transmit Data

FPSC SAI Signal Locations

QSPI

The FPSC Gamma (Lite) Feature Set defines one Mandatory QSPI that acts as a bidirectional serial bus with up to 4 data lanes for simple and efficient data exchange between devices. The QSPI supports single, dual, and quad data mode.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions	Notes
AJ24	QSPI_nCE	Mandatory	Mandatory	OUT	1.8V	QSPI Chip Enable	Active-Low signal.
AG24	QSPI_CLK	Mandatory	Mandatory	OUT	1.8V	QSPI Clock
AF21	QSPI_DATA_0	Mandatory	Mandatory	I/O	1.8V	QSPI Data 0
AG20	QSPI_DATA_1	Mandatory	Mandatory	I/O	1.8V	QSPI Data 1
AG22	QSPI_DATA_2	Mandatory	Mandatory	I/O	1.8V	QSPI Data 2
AH21	QSPI_DATA_3	Mandatory	Mandatory	I/O	1.8V	QSPI Data 3
AJ22	QSPI_DQS	Optional	Optional	OUT	1.8V	QSPI Data Strobe

FPSC QSPI Signal Locations

When routing the QSPI signals on the FPSC SOM, the following constraints must be met.

Signal Name	Match Group	Required TOF Matching
QSPI_nCE	QSPI	50ps
QSPI_CLK
QSPI_DATA_0
QSPI_DATA_1
QSPI_DATA_2
QSPI_DATA_3

FPSC QSPI Routing Constraints

ADC

The FPSC Gamma (Lite) Feature Set defines eight Optional ADCs that can be used to measure carrier board voltages and currents. The maximum input voltage of 1.8V should not be exceeded.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions	Notes
R16	ADC1	Optional	Optional	A_IN	<=1.8V	Analog to Digital Converter 1	Do not exceed 1.8V on CB
T15	ADC2	Optional	Optional	A_IN	<=1.8V	Analog to Digital Converter 2
U16	ADC3	Optional	Optional	A_IN	<=1.8V	Analog to Digital Converter 3
U14	ADC4	Optional	Optional	A_IN	<=1.8V	Analog to Digital Converter 4
V15	ADC5	Optional	Optional	A_IN	<=1.8V	Analog to Digital Converter 5
W16	ADC6	Optional	Optional	A_IN	<=1.8V	Analog to Digital Converter 6
W14	ADC7	Optional	Optional	A_IN	<=1.8V	Analog to Digital Converter 7
Y15	ADC8	Optional	Optional	A_IN	<=1.8V	Analog to Digital Converter 8

FPSC ADC Signal Locations

SDIO

The FPSC Gamma (Lite) Feature Set defines one Mandatory and one Optional SDIO interface. Both SDIO interfaces support a 4-bit wide data bus that complies with the SDIO Specification v3.00.

SD Card Interface

The SD card interface is intended for SD card boot. It provides the necessary power supply for the card via the SDCARD_VCC_OUT signal and allows various "bus speed modes" to be negotiated with the host processor. Depending on the SD card used, the logic voltage can be either 3.3 V or 1.8 V. No additional circuitry is required on the baseboard except for capacitors for VCC, as the SOM implements the logic for this voltage transition.

SDIO Interface

The SDIO interface is intended for general use, such as for Wi-Fi, and is not supported for SD-card boot. The 4-bit-wide SDIO interface can also provide additional nWP and CD control signals. Additionally, the IO reference voltage of the interface is accessible at pin J56.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	PU	Signal Descriptions	Notes
V57	SDCARD_nCD	Mandatory	Mandatory	OD_IN	1.8V/3.3V	4.7K	SD Card Card Detect	Active-Low signal.
W60	SDCARD_CLK	Mandatory	Mandatory	OUT	1.8V/3.3V		SD Card Clock
W58	SDCARD_CMD	Mandatory	Mandatory	I/O	1.8V/3.3V	49.9K	SD Card Command
W62	SDCARD_DATA0	Mandatory	Mandatory	I/O	1.8V/3.3V	49.9K	SD Card Data 0
Y61	SDCARD_DATA1	Mandatory	Mandatory	I/O	1.8V/3.3V	49.9K	SD Card Data 1
U60	SDCARD_DATA2	Mandatory	Mandatory	I/O	1.8V/3.3V	49.9K	SD Card Data 2
V61	SDCARD_DATA3	Mandatory	Mandatory	I/O	1.8V/3.3V	49.9K	SD Card Data 3
Y57	SDCARD_VCC_OUT	Mandatory	Mandatory	PWR_OUT	3.3V		SD Card Power Supply	Internal power supply on SOM (max. 800 mA)
V67	SDCARD_nWP	Optional	Optional	OD_IN	1.8V	4.7K	SD Card Write Protect	Active-Low signal
J58	SDIO_nCD	Optional	Optional	OD_IN	1.8V		SDIO Card Detect	If this pin is used, connect a pull-up resistor to SDIO_VIO_OUT
H57	SDIO_CLK	Optional	Optional	OUT	1.8V		SDIO Clock	The signal voltage is always referenced to SDIO_VIO_OUT
G56	SDIO_CMD	Optional	Optional	I/O	1.8V		SDIO Command
G62	SDIO_DATA0	Optional	Optional	I/O	1.8V		SDIO Data 0
H61	SDIO_DATA1	Optional	Optional	I/O	1.8V		SDIO Data 1
G60	SDIO_DATA2	Optional	Optional	I/O	1.8V		SDIO Data 2
G58	SDIO_DATA3	Optional	Optional	I/O	1.8V		SDIO Data 3
J56	SDIO_VIO_OUT	Optional	Optional	PWR_OUT	1.8V		SDIO IO Reference Voltage	Internal power supply on SOM (max. 20 mA)
G54	SDIO_nWP	Optional	Optional	OD_IN	1.8V		SDIO Write Protect	If this pin is used, connect it to a pull-up resistor to SDIO_VIO_OUT

FPSC SD Card/SDIO Signal Locations

When routing the SDIO signals on the FPSC SOM, the following constraints must be met.

Signal Name	Match Group	Required TOF Matching
SDCARD_CLK	SDCARD	35ps
SDCARD_CMD
SDCARD_DATA0
SDCARD_DATA1
SDCARD_DATA2
SDCARD_DATA3
SDIO_CLK	SDIO	35ps
SDIO_CMD
SDIO_DATA0
SDIO_DATA1
SDIO_DATA2
SDIO_DATA3

FPSC SDIO Routing Constraints

CAN

The FPSC Gamma Feature Set defines two Mandatory and one Optional (three Optional for Gamma Light) CAN interfaces that comply with CAN protocol 2.0 B and ISO 11898-1. These interfaces support flexible message payloads ranging from 0 to 64 bytes. While CAN support is the default, CAN-FD is commonly supported on our SOMs. If a SOM supports CAN-FD, it can be used with a CB and an appropriate transceiver. Due to its backward compatibility, CAN-FD will also work with a CAN system.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions
N38	CAN1_RX	Mandatory	Optional	IN	1.8V	CAN1 Receive
N36	CAN1_TX	Mandatory	Optional	OUT	1.8V	CAN1 Transmit
L38	CAN2_RX	Mandatory	Optional	IN	1.8V	CAN2 Receive
M37	CAN2_TX	Mandatory	Optional	OUT	1.8V	CAN2 Transmit
G20	CAN3_RX	Optional	Optional	IN	1.8V	CAN3 Receive
H21	CAN3_TX	Optional	Optional	OUT	1.8V	CAN3 Transmit

FPSC CAN Signal Locations

I2C/I3C

The FPSC Gamma (Lite) Feature Set defines three Mandatory and two Optional I2C interfaces, as well as one Optional I3C interface. These are two-wire, bidirectional serial buses that enable simple and efficient data exchange between devices. Since I2C is an open-drain interface, external pull resistors must be added to ensure proper functionality.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	PU	Signal Descriptions	Notes
L26	I2C1_SCL_DNU	Mandatory	Mandatory	OD_IO	1.8V	2.2K	I2C1 Clock	Active-Low signal. SOM I2C - Do not connect to prevent malfunction.
L28	I2C1_SDA_DNU	Mandatory	Mandatory	OD_IO	1.8V	2.2K	I2C1 Data
L60	I2C2_SCL	Mandatory	Mandatory	OD_IO	1.8V		I2C2 Clock	Active-Low signal. Requires an external pull-up resistor.
L58	I2C2_SDA	Mandatory	Mandatory	OD_IO	1.8V		I2C2 Data
M61	I2C3_SCL	Mandatory	Mandatory	OD_IO	1.8V		I2C3 Clock
N60	I2C3_SDA	Mandatory	Mandatory	OD_IO	1.8V		I2C3 Data
AN36	I2C4_SCL	Optional	Optional	OD_IO	1.8V		I2C4 Clock
AN38	I2C4_SDA	Optional	Optional	OD_IO	1.8V		I2C4 Data
AN40	I2C5_SCL/I3C_SCL	Optional	Optional	OD_IO/IO	1.8V		I2C5/I3C5 Clock	Active-Low signal. Requires an external pull-up resistor. Brings out I3C if supported by the processor.
AN42	I2C5_SDA/I3C_SDA	Optional	Optional	OD_IO/IO	1.8V		I2C5/I3C5 Data

FPSC I2C/I3C Signal Locations

SPI

The FPSC Gamma (Lite) feature set defines two Mandatory and one Optional serial peripheral interface (SPI) interface. These interfaces are four-wire, bidirectional serial buses that provide master/slave configurability.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions	Notes
L34	SPI1_nCS	Mandatory	Mandatory	OUT	1.8V	SPI1 Chip Select	Active-Low signal.
N34	SPI1_MISO	Mandatory	Mandatory	IN	1.8V	SPI1 Master in, Slave out
N32	SPI1_MOSI	Mandatory	Mandatory	OUT	1.8V	SPI1 Master out, Slave in
M33	SPI1_SCLK	Mandatory	Mandatory	OUT	1.8V	SPI1 Clock
N30	SPI2_nCS	Mandatory	Mandatory	OUT	1.8V	SPI2 Chip Select	Active-Low signal.
L32	SPI2_MISO	Mandatory	Mandatory	IN	1.8V	SPI2 Master in, Slave out
L30	SPI2_MOSI	Mandatory	Mandatory	OUT	1.8V	SPI2 Master out, Slave in
M29	SPI2_SCLK	Mandatory	Mandatory	OUT	1.8V	SPI2 Clock
AM41	SPI3_nCS	Optional	Optional	OUT	1.8V	SPI3 Chip Select	Active-Low signal.
AL36	SPI3_MISO	Optional	Optional	IN	1.8V	SPI3 Master in, Slave out
AL38	SPI3_MOSI	Optional	Optional	OUT	1.8V	SPI3 Master out, Slave in
AL40	SPI3_SCLK	Optional	Optional	OUT	1.8V	SPI3 Clock

FPSC I2C/I3C Signal Locations

UART

The FPSC Gamma (Lite) Specification defines three Mandatory UART interfaces with different prioritizations.

Primary Debug Interface for debug outputs of the main CPU
Special Debug Interface for debug outputs of the support CPU (if available)
A normal UART interface with no special function for the baseboard unless the SOM is boot capable

All UARTs operate as a DTE, with TxD and RTS as outputs and RxD and CTS as inputs. Under certain circumstances, the signal direction can be reversed within the CPU. More information on this can be found in the processor data sheet.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions	Notes
M41	UART1_CTS	Mandatory	Mandatory	IN	1.8V	UART1 Clear to Send
N42	UART1_RTS	Mandatory	Mandatory	OUT	1.8V	UART1 Request to Send
L44	UART1_RXD	Mandatory	Mandatory	IN	1.8V	UART1 Receive
L42	UART1_TXD	Mandatory	Mandatory	OUT	1.8V	UART1 Transmit
L46	UART2_CTS	Mandatory	Mandatory	IN	1.8V	UART2 Clear to Send	Special Debug Interface
M45	UART2_RTS	Mandatory	Mandatory	OUT	1.8V	UART2 Request to Send
N46	UART2_RXD	Mandatory	Mandatory	IN	1.8V	UART2 Receive
N44	UART2_TXD	Mandatory	Mandatory	OUT	1.8V	UART2 Transmit
AE22	UART3_RXD	Mandatory	Mandatory	IN	1.8V	UART3 Receive	Primary Debug Interface

FPSC UART Signal Locations

PCIe

The FPSC Gamma (Lite) specification defines two Optional PCIe interfaces. The specific PCIe generation used depends on the SOM, but most FPSC SOMs support PCIe Gen 3.0, which operates at speeds of up to 8 GT/s.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions	Notes
AA14	PCIE1_CLK_N	Optional	Optional	OUT	Differential	PCIe1 Reference Clock Negative	The coupling capacitor is located on the module.
AB15	PCIE1_CLK_P	Optional	Optional	OUT	Differential	PCIe1 Reference Clock Positive	The coupling capacitor is located on the module.
AC16	PCIE1_nCLKREQ	Optional	Optional	IN	1.8V	PCIe1 Clock Request	Active-Low signal.
AC14	PCIE1_nPERST	Optional	Optional	OUT	1.8V	PCIe1 Reset	Active-Low signal.
AB11	PCIE1_RXN_N	Optional	Optional	IN	Differential	PCIe1 Receive Data Negative
AC12	PCIE1_RXN_P	Optional	Optional	IN	Differential	PCIe1 Receive Data Positive
Y11	PCIE1_TXN_N	Optional	Optional	OUT	Differential	PCIe1 Transmit Data Negative	The coupling capacitor is located on the module.
AA12	PCIE1_TXN_P	Optional	Optional	OUT	Differential	PCIe1 Transmit Data Positive	The coupling capacitor is located on the module.
AL24	PCIE2_CLK_N	Optional	Optional	I/O	Differential	PCIe2 Reference Clock Negative	The coupling capacitor is located on the module. If supported by the SOM, this signal is an output. Please refer to the SOM manual for further details. For full functionality, provide a clock generator on your baseboard.
AL26	PCIE2_CLK_P	Optional	Optional	I/O	Differential	PCIe2 Reference Clock Positive
AM21	PCIE2_nCLKREQ	Optional	Optional	IN	1.8V	PCIe2 Clock Request	Active-Low signal.
AM25	PCIE2_nPERST	Optional	Optional	OUT	1.8V	PCIe2 Reset	Active-Low signal.
AN26	PCIE2_RXN_N	Optional	Optional	IN	Differential	PCIe2 Receive Data Negative
AN28	PCIE2_RXN_P	Optional	Optional	IN	Differential	PCIe2 Receive Data Positive
AN22	PCIE2_TXN_N	Optional	Optional	OUT	Differential	PCIe2 Transmit Data Negative	The coupling capacitor is located on the module.
AN24	PCIE2_TXN_P	Optional	Optional	OUT	Differential	PCIe2 Transmit Data Positive	The coupling capacitor is located on the module.

FPSC PCIe Signal Locations

When routing the PCIe signals on the FPSC SOM, the following constraints must be met.

Signal Name	Intra-Pair Required TOF Matching
PCIE1_CLK_N	0.125 ps
PCIE1_CLK_P	0.125 ps
PCIE1_RXN_N	0.125 ps
PCIE1_RXN_P	0.125 ps
PCIE1_TXN_N	0.125 ps
PCIE1_TXN_P	0.125 ps
PCIE2_CLK_N	0.125 ps
PCIE2_CLK_P	0.125 ps
PCIE2_RXN_N	0.125 ps
PCIE2_RXN_P	0.125 ps
PCIE2_TXN_N	0.125 ps
PCIE2_TXN_P	0.125 ps

FPSC SDIO Routing Constraints

LVDS

The FPSC Gamma Feature Set defines one Mandatory and one Optional (two optional for Gamma Lite) LVDS display port. Single-channel, dual-channel, and two single-channel LVDS displays can be Optionally supported.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions
N52	LVDS1_CLK_N	Mandatory	Optional	OUT	Differential	LVDS1 Clock Negative
N50	LVDS1_CLK_P	Mandatory	Optional	OUT	Differential	LVDS1 Clock Positive
L52	LVDS1_DATA0_N	Mandatory	Optional	OUT	Differential	LVDS1 Data 0 Negative
L50	LVDS1_DATA0_P	Mandatory	Optional	OUT	Differential	LVDS1 Data 0 Positive
L54	LVDS1_DATA1_N	Mandatory	Optional	OUT	Differential	LVDS1 Data 1 Negative
M53	LVDS1_DATA1_P	Mandatory	Optional	OUT	Differential	LVDS1 Data 1 Positive
N56	LVDS1_DATA2_N	Mandatory	Optional	OUT	Differential	LVDS1 Data 2 Negative
N54	LVDS1_DATA2_P	Mandatory	Optional	OUT	Differential	LVDS1 Data 2 Positive
M57	LVDS1_DATA3_N	Mandatory	Optional	OUT	Differential	LVDS1 Data 3 Negative
L56	LVDS1_DATA3_P	Mandatory	Optional	OUT	Differential	LVDS1 Data 3 Positive
AN54	LVDS2_CLK_N	Optional	Optional	OUT	Differential	LVDS2 Clock Negative
AN56	LVDS2_CLK_P	Optional	Optional	OUT	Differential	LVDS2 Clock Positive
AN60	LVDS2_DATA0_N	Optional	Optional	OUT	Differential	LVDS2 Data 0 Negative
AM61	LVDS2_DATA0_P	Optional	Optional	OUT	Differential	LVDS2 Data 0 Positive
AL56	LVDS2_DATA1_N	Optional	Optional	OUT	Differential	LVDS2 Data 1 Negative
AL58	LVDS2_DATA1_P	Optional	Optional	OUT	Differential	LVDS2 Data 1 Positive
AM57	LVDS2_DATA2_N	Optional	Optional	OUT	Differential	LVDS2 Data 2 Negative
AN58	LVDS2_DATA2_P	Optional	Optional	OUT	Differential	LVDS2 Data 2 Positive
AL52	LVDS2_DATA3_N	Optional	Optional	OUT	Differential	LVDS2 Data 3 Negative
AL54	LVDS2_DATA3_P	Optional	Optional	OUT	Differential	LVDS2 Data 3 Positive

FPSC LVDS Signal Locations

When routing the LVDS signals on the FPSC SOM, the following constraints must be met.

Signal Name	Intra-Pair Required TOF Matching	Match Group	Required TOF Matching
LVDS1_CLK_N	6 ps	LVDS1	50 ps
LVDS1_CLK_P	6 ps
LVDS1_DATA0_N	6 ps
LVDS1_DATA0_P	6 ps
LVDS1_DATA1_N	6 ps
LVDS1_DATA1_P	6 ps
LVDS1_DATA2_N	6 ps
LVDS1_DATA2_P	6 ps
LVDS1_DATA3_N	6 ps
LVDS1_DATA3_P	6 ps
LVDS2_CLK_N	6 ps	LVDS2	50 ps
LVDS2_CLK_P	6 ps
LVDS2_DATA0_N	6 ps
LVDS2_DATA0_P	6 ps
LVDS2_DATA1_N	6 ps
LVDS2_DATA1_P	6 ps
LVDS2_DATA2_N	6 ps
LVDS2_DATA2_P	6 ps
LVDS2_DATA3_N	6 ps
LVDS2_DATA3_P	6 ps

FPSC SDIO Routing Constraints

HDMI

The FPSC Gamma (Lite) feature set defines one Optional HDMI interface that complies with the HDMI 2.0a standard. The HDMI interface supports a maximum resolution of 3840 x 2160 pixels at 60 Hz.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions	Notes
AJ14	EARC_N/HDMI_HPD	Optional	Optional	OUT	1.8V	HDMI Enhanced Audio Return Channel Negative / HDMI Hot Plug Detect
AH15	EARC_P/HDMI_UTIL	Optional	Optional	OUT	1.8V	HDMI Enhanced Audio Return Channel Positive / HDMI Utility Pin
AH11	HDMI_CEC	Optional	Optional	I/O	1.8V	HDMI Consumer Electronic Control
AJ12	HDMI_HPD	Optional	Optional	IN	1.8V	HDMI Hot Plug Detect
AE14	HDMI_SCL	Optional	Optional	OD_IO	1.8V	HDMI I2C Data	Requires an external pull-up resistor
AG14	HDMI_SDA	Optional	Optional	OD_IO	1.8V	HDMI I2C Clock	Requires an external pull-up resistor
AD15	HDMI_TX0_N	Optional	Optional	OUT	Differential	HDMI Transmit 0 Negative
AE16	HDMI_TX0_P	Optional	Optional	OUT	Differential	HDMI Transmit 0 Positive
AF11	HDMI_TX1_N	Optional	Optional	OUT	Differential	HDMI Transmit 1 Negative
AG12	HDMI_TX1_P	Optional	Optional	OUT	Differential	HDMI Transmit 1 Positive
AF15	HDMI_TX2_N	Optional	Optional	OUT	Differential	HDMI Transmit 2 Negative
AG16	HDMI_TX2_P	Optional	Optional	OUT	Differential	HDMI Transmit 2 Positive
AD11	HDMI_TXC_N	Optional	Optional	OUT	Differential	HDMI Transmit Clock Negative
AE12	HDMI_TXC_P	Optional	Optional	OUT	Differential	HDMI Transmit Clock Positive

FPSC HDMI Signal Locations

When routing the HDMI signals on the FPSC SOM, the following constraints must be met.

Signal Name	Intra-Pair Required TOF Matching
HDMI_TX0_N	0.15 ps
HDMI_TX0_P	0.15 ps
HDMI_TX1_N	0.15 ps
HDMI_TX1_P	0.15 ps
HDMI_TX2_N	0.15 ps
HDMI_TX2_P	0.15 ps
HDMI_TXC_N	0.15 ps
HDMI_TXC_P	0.15 ps

FPSC HDMI Routing Constraints

DSI

The FPSC Gamma (Lite) feature set defines one Optional DSI display interface. This interface can support up to four channels with a resolution of up to 1920 x 1080 pixels at 60 Hz.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions
AN46	DSI1_CLK_N	Optional	Optional	OUT	Differential	DSI1 Clock Negative
AN48	DSI1_CLK_P	Optional	Optional	OUT	Differential	DSI1 Clock Positive
AL48	DSI1_D0_N	Optional	Optional	OUT	Differential	DSI1 Data 0 Negative
AL50	DSI1_D0_P	Optional	Optional	OUT	Differential	DSI1 Data 0 Positive
AM49	DSI1_D1_N	Optional	Optional	OUT	Differential	DSI1 Data 1 Negative
AN50	DSI1_D1_P	Optional	Optional	OUT	Differential	DSI1 Data 1 Positive
AN44	DSI1_D2_N	Optional	Optional	OUT	Differential	DSI1 Data 2 Negative
AM45	DSI1_D2_P	Optional	Optional	OUT	Differential	DSI1 Data 2 Positive
AL44	DSI1_D3_N	Optional	Optional	OUT	Differential	DSI1 Data 3 Negative
AL46	DSI1_D3_P	Optional	Optional	OUT	Differential	DSI1 Data 3 Positive

FPSC DSI Signal Locations

When routing the DSI signals on the FPSC SOM, the following constraints must be met.

Signal Name	Intra-Pair Required TOF Matching	Match Group	Required TOF Matching
DSI1_CLK_N	6 ps	DSI1	50 ps
DSI1_CLK_P	6 ps
DSI1_D0_N	6 ps
DSI1_D0_P	6 ps
DSI1_D1_N	6 ps
DSI1_D1_P	6 ps
DSI1_D2_N	6 ps
DSI1_D2_P	6 ps
DSI1_D3_N	6 ps
DSI1_D3_P	6 ps

FPSC DSI Routing Constraints

CSI

The FPSC Gamma (Lite) feature set defines two Optional 2- or 4-lane CSI interfaces. Any CSI interfaces brought out comply with the MIPI CSI-2 v1.3 standard.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions
R62	CSI1_CLK_N	Optional	Optional	IN	Differential	CSI1 Clock Negative
R60	CSI1_CLK_P	Optional	Optional	IN	Differential	CSI1 Clock Positive
T57	CSI1_D0_N	Optional	Optional	IN	Differential	CSI1 Data 0 Negative
U58	CSI1_D0_P	Optional	Optional	IN	Differential	CSI1 Data 0 Positive
T61	CSI1_D1_N	Optional	Optional	IN	Differential	CSI1 Data 1 Negative
U62	CSI1_D1_P	Optional	Optional	IN	Differential	CSI1 Data 1 Positive
P57	CSI1_D2_N	Optional	Optional	IN	Differential	CSI1 Data 2 Negative
R58	CSI1_D2_P	Optional	Optional	IN	Differential	CSI1 Data 2 Positive
N62	CSI1_D3_N	Optional	Optional	IN	Differential	CSI1 Data 3 Negative
P61	CSI1_D3_P	Optional	Optional	IN	Differential	CSI1 Data 3 Positive
H41	CSI2_CLK_N	Optional	Optional	IN	Differential	CSI2 Clock Negative
J42	CSI2_CLK_P	Optional	Optional	IN	Differential	CSI2 Clock Positive
G42	CSI2_D0_N	Optional	Optional	IN	Differential	CSI2 Data 0 Negative
G44	CSI2_D0_P	Optional	Optional	IN	Differential	CSI2 Data 0 Positive
J44	CSI2_D1_N	Optional	Optional	IN	Differential	CSI2 Data 1 Negative
H45	CSI2_D1_P	Optional	Optional	IN	Differential	CSI2 Data 1 Positive
J38	CSI2_D2_N	Optional	Optional	IN	Differential	CSI2 Data 2 Negative
J40	CSI2_D2_P	Optional	Optional	IN	Differential	CSI2 Data 2 Positive
G38	CSI2_D3_N	Optional	Optional	IN	Differential	CSI2 Data 3 Negative
G40	CSI2_D3_P	Optional	Optional	IN	Differential	CSI2 Data 3 Positive

FPSC CSI Signal Locations

When routing the CSI signals on the FPSC SOM, the following constraints must be met.

Signal Name	Intra-Pair Required TOF Matching	Match Group	Required TOF Matching
CSI1_CLK_N	0.5 ps	CSI1	20 ps
CSI1_CLK_P	0.5 ps
CSI1_D0_N	0.5 ps
CSI1_D0_P	0.5 ps
CSI1_D1_N	0.5 ps
CSI1_D1_P	0.5 ps
CSI1_D2_N	0.5 ps
CSI1_D2_P	0.5 ps
CSI1_D3_N	0.5 ps
CSI1_D3_P	0.5 ps
CSI2_CLK_N	0.5 ps	CSI2	20 ps
CSI2_CLK_P	0.5 ps
CSI2_D0_N	0.5 ps
CSI2_D0_P	0.5 ps
CSI2_D1_N	0.5 ps
CSI2_D1_P	0.5 ps
CSI2_D2_N	0.5 ps
CSI2_D2_P	0.5 ps
CSI2_D3_N	0.5 ps
CSI2_D3_P	0.5 ps

FPSC DSI Routing Constraints

Ethernet

The FPSC Gamma (Lite) feature set defines one Mandatory gigabit Ethernet interface. This interface is provided via an onboard Ethernet physical layer (PHY) transceiver capable of operating at data transmission speeds of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions	Notes
AH57	GB_ETH1_A_N	Mandatory	Mandatory	I/O	Differential	Ethernet Data A Negative	Needs a GB-Ethernet transformer on the CB if running at 1000 Mbit/s.
AJ58	GB_ETH1_A_P	Mandatory	Mandatory	I/O	Differential	Ethernet Data A Positive
AF57	GB_ETH1_B_N	Mandatory	Mandatory	I/O	Differential	Ethernet Data B Negative
AG58	GB_ETH1_B_P	Mandatory	Mandatory	I/O	Differential	Ethernet Data B Positive
AG62	GB_ETH1_C_N	Mandatory	Mandatory	I/O	Differential	Ethernet Data C Negative
AH61	GB_ETH1_C_P	Mandatory	Mandatory	I/O	Differential	Ethernet Data C Positive
AE62	GB_ETH1_D_N	Mandatory	Mandatory	I/O	Differential	Ethernet Data D Negative
AF61	GB_ETH1_D_P	Mandatory	Mandatory	I/O	Differential	Ethernet Data D Positive
AG60	GB_ETH1_LED_ACT	Mandatory	Mandatory	OD_OUT	<= 5V	Ethernet LED Activity Signal	Output to sink an LED. Max. Output Low Current: 30 mA. Max. Output High Voltage: 5V.
AJ60	GB_ETH1_LED_LINK	Mandatory	Mandatory	OD_OUT	<= 5V	Ethernet LED Link Signal

FPSC Ethernet Signal Locations

When routing the Ethernet signals on the FPSC SOM, the following constraints must be met.

Signal Name	Intra-Pair Required TOF Matching
GB_ETH1_A_N	2.5 ps
GB_ETH1_A_P	2.5 ps
GB_ETH1_B_N	2.5 ps
GB_ETH1_B_P	2.5 ps
GB_ETH1_C_N	2.5 ps
GB_ETH1_C_P	2.5 ps
GB_ETH1_D_N	2.5 ps
GB_ETH1_D_P	2.5 ps

FPSC Ethernet Routing Constraints

RGMII

The FPSC Gamma Feature Set defines one Mandatory and one Optional RGMII interface for use with an external Ethernet PHY. It also defines two Optional event signals intended for use in TSN.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	PU	Signal Descriptions	Notes
AH45	RGMII2_EVENT_IN	Optional	Optional	IN	1.8V		RGMII2 Event In	Intended for use in TSN.
AJ44	RGMII2_EVENT_OUT	Optional	Optional	OUT	1.8V		RGMII2 Event Out	Intended for use in TSN.
AG46	RGMII2_MDC	Mandatory	Optional	OUT	1.8V		RGMII2 Management Data Clock
AG44	RGMII2_MDIO	Mandatory	Optional	I/O	1.8V	2.2K	RGMII2 Management Data IO	May need external 2k2 PU-Resistor. Refer to the SOM hardware manual.
AG48	RGMII2_nINT	Mandatory	Optional	IN	1.8V		RGMII2 Interrupt	Active-Low signal. Connect to RGMII2 Ethernet-PHY Interrupt-Output.
AG54	RGMII2_RX_CTL	Mandatory	Optional	IN	1.8V		RGMII2 Receive Control
AJ56	RGMII2_RX_D0	Mandatory	Optional	IN	1.8V		RGMII1 Receive Data 0
AJ54	RGMII2_RX_D1	Mandatory	Optional	IN	1.8V		RGMII1 Receive Data 1
AJ52	RGMII2_RX_D2	Mandatory	Optional	IN	1.8V		RGMII1 Receive Data 2
AH53	RGMII2_RX_D3	Mandatory	Optional	IN	1.8V		RGMII1 Receive Data 3
AG56	RGMII2_RXC	Mandatory	Optional	IN	1.8V		RGMII1 Receive Clock
AG50	RGMII2_TX_CTL	Mandatory	Optional	OUT	1.8V		RGMII2 Transmit Control
AJ50	RGMII2_TX_D0	Mandatory	Optional	OUT	1.8V		RGMII1 Transmit Data 0
AJ48	RGMII2_TX_D1	Mandatory	Optional	OUT	1.8V		RGMII1 Transmit Data 1
AH49	RGMII2_TX_D2	Mandatory	Optional	OUT	1.8V		RGMII1 Transmit Data 2
AJ46	RGMII2_TX_D3	Mandatory	Optional	OUT	1.8V		RGMII1 Transmit Data 3
AG52	RGMII2_TXC	Mandatory	Optional	OUT	1.8V		RGMII1 Transmit Clock

FPSC RGMII Signal Locations

When routing the RGMII signals on the FPSC SOM, the following constraints must be met.

Signal Name	Match Group	Required TOF Matching
RGMII2_RX_CTL	RGMII Receive	60 ps
RGMII2_RX_D0
RGMII2_RX_D1
RGMII2_RX_D2
RGMII2_RX_D3
RGMII2_RXC
RGMII2_TX_CTL	RGMII Transmit	60 ps
RGMII2_TX_D0
RGMII2_TX_D1
RGMII2_TX_D2
RGMII2_TX_D3
RGMII2_TXC

FPSC Ethernet Routing Constraints

USB

The FPSC Gamma Feature Set defines two Mandatory USB 2.0 interfaces (Gamma Light and one Mandatory and one Optional) and two Optional USB 3.0 or higher interfaces. If the processor supports USB OTG, USB1 is the default interface to support USB OTG (host and device). If the processor does not support OTG, USB1 will behave in host mode.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions	Notes
AD61	USB1_D_N	Mandatory	Mandatory	I/O	Differential	USB1 2.0 Data Negative
AC62	USB1_D_P	Mandatory	Mandatory	I/O	Differential	USB1 2.0 Data Positive
AE60	USB1_ID	Optional	Optional	IN	1.8V	USB1 ID
AE58	USB1_nOC	Mandatory	Mandatory	IN	1.8V	USB1 Over Current	Active-Low signal.
AD57	USB1_PWR_EN	Mandatory	Mandatory	OUT	1.8V	USB1 Power Enable
AF67	USB1_RX0_N	Optional	Optional	IN	Differential	USB1 3.0 Receive Negative
AE66	USB1_RX0_P	Optional	Optional	IN	Differential	USB1 3.0 Receive Positive
AF71	USB1_TX0_N	Optional	Optional	OUT	Differential	USB1 3.0 Transmit Negative	The coupling capacitor is located on the module.
AE70	USB1_TX0_P	Optional	Optional	OUT	Differential	USB1 3.0 Transmit Positive	The coupling capacitor is located on the module.
AC60	USB1_VBUS	Mandatory	Mandatory	PWR_IN	5V	USB1 Voltage Bus	Must not exceed 5V
AB61	USB2_D_N	Mandatory	Optional	I/O	Differential	USB2 2.0 Data Negative
AA62	USB2_D_P	Mandatory	Optional	I/O	Differential	USB2 2.0 Data Positive
AA60	USB2_ID	Optional	Optional	IN	1.8V	USB2 ID
AC58	USB2_nOC	Mandatory	Optional	IN	1.8V	USB2 Over Current	Active-Low signal.
AB57	USB2_PWR_EN	Mandatory	Optional	OUT	1.8V	USB2 Power Enable
AC66	USB2_RX0_N	Optional	Optional	IN	Differential	USB2 3.0 Receive Negative
AB67	USB2_RX0_P	Optional	Optional	IN	Differential	USB2 3.0 Receive Positive
AC70	USB2_TX0_N	Optional	Optional	OUT	Differential	USB2 3.0 Transmit Negative	The coupling capacitor is located on the module.
AB71	USB2_TX0_P	Optional	Optional	OUT	Differential	USB2 3.0 Transmit Positive	The coupling capacitor is located on the module.
AA58	USB2_VBUS	Optional	Optional	PWR_IN	5V	USB2 Voltage Bus	Must not exceed 5V

FPSC USB Signal Locations

When routing the USB signals on the FPSC SOM, the following constraints must be met.

Signal Name	Intra-Pair Required TOF Matching
USB1_D_N	2 ps
USB1_D_P	2 ps
USB2_D_N	2 ps
USB2_D_P	2 ps
USB1_RX0_N	0.2 ps
USB1_RX0_P	0.2 ps
USB1_TX0_N	0.2 ps
USB1_TX0_P	0.2 ps
USB2_RX0_N	0.2 ps
USB2_RX0_P	0.2 ps
USB2_TX0_N	0.2 ps
USB2_TX0_P	0.2 ps

FPSC USB Routing Constraints

GND

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Signal Descriptions
A10	0V GND	Mandatory	Mandatory	-	-	Ground
A14	0V GND	Mandatory	Mandatory	-	-	Ground
A18	0V GND	Mandatory	Mandatory	-	-	Ground
A22	0V GND	Mandatory	Mandatory	-	-	Ground
A26	0V GND	Mandatory	Mandatory	-	-	Ground
A30	0V GND	Mandatory	Mandatory	-	-	Ground
A34	0V GND	Mandatory	Mandatory	-	-	Ground
A38	0V GND	Mandatory	Mandatory	-	-	Ground
A44	0V GND	Mandatory	Mandatory	-	-	Ground
A48	0V GND	Mandatory	Mandatory	-	-	Ground
A52	0V GND	Mandatory	Mandatory	-	-	Ground
A56	0V GND	Mandatory	Mandatory	-	-	Ground
A60	0V GND	Mandatory	Mandatory	-	-	Ground
A64	0V GND	Mandatory	Mandatory	-	-	Ground
A68	0V GND	Mandatory	Mandatory	-	-	Ground
A72	0V GND	Mandatory	Mandatory	-	-	Ground
D81	0V GND	Mandatory	Mandatory	-	-	Ground
F81	0V GND	Mandatory	Mandatory	-	-	Ground
H81	0V GND	Mandatory	Mandatory	-	-	Ground
K81	0V GND	Mandatory	Mandatory	-	-	Ground
M81	0V GND	Mandatory	Mandatory	-	-	Ground
P81	0V GND	Mandatory	Mandatory	-	-	Ground
T81	0V GND	Mandatory	Mandatory	-	-	Ground
V81	0V GND	Mandatory	Mandatory	-	-	Ground
Y81	0V GND	Mandatory	Mandatory	-	-	Ground
AB81	0V GND	Mandatory	Mandatory	-	-	Ground
AD81	0V GND	Mandatory	Mandatory	-	-	Ground
AF81	0V GND	Mandatory	Mandatory	-	-	Ground
AH81	0V GND	Mandatory	Mandatory	-	-	Ground
AK81	0V GND	Mandatory	Mandatory	-	-	Ground
AM81	0V GND	Mandatory	Mandatory	-	-	Ground
AP81	0V GND	Mandatory	Mandatory	-	-	Ground
AT81	0V GND	Mandatory	Mandatory	-	-	Ground
C26	0V GND	Mandatory	Mandatory	-	-	Ground
C30	0V GND	Mandatory	Mandatory	-	-	Ground
C34	0V GND	Mandatory	Mandatory	-	-	Ground
C38	0V GND	Mandatory	Mandatory	-	-	Ground
C44	0V GND	Mandatory	Mandatory	-	-	Ground
C48	0V GND	Mandatory	Mandatory	-	-	Ground
C52	0V GND	Mandatory	Mandatory	-	-	Ground
C56	0V GND	Mandatory	Mandatory	-	-	Ground
P79	0V GND	Mandatory	Mandatory	-	-	Ground
T79	0V GND	Mandatory	Mandatory	-	-	Ground
V79	0V GND	Mandatory	Mandatory	-	-	Ground
Y79	0V GND	Mandatory	Mandatory	-	-	Ground
AB79	0V GND	Mandatory	Mandatory	-	-	Ground
AD79	0V GND	Mandatory	Mandatory	-	-	Ground
AF79	0V GND	Mandatory	Mandatory	-	-	Ground
E30	0V GND	Mandatory	Mandatory	-	-	Ground
E36	0V GND	Mandatory	Mandatory	-	-	Ground
E46	0V GND	Mandatory	Mandatory	-	-	Ground
E52	0V GND	Mandatory	Mandatory	-	-	Ground
K75	0V GND	Mandatory	Mandatory	-	-	Ground
N74	0V GND	Mandatory	Mandatory	-	-	Ground
T75	0V GND	Mandatory	Mandatory	-	-	Ground
W74	0V GND	Mandatory	Mandatory	-	-	Ground
AA74	0V GND	Mandatory	Mandatory	-	-	Ground
AD75	0V GND	Mandatory	Mandatory	-	-	Ground
AG74	0V GND	Mandatory	Mandatory	-	-	Ground
AK75	0V GND	Mandatory	Mandatory	-	-	Ground
H23	0V GND	Mandatory	Mandatory	-	-	Ground
H27	0V GND	Mandatory	Mandatory	-	-	Ground
H31	0V GND	Mandatory	Mandatory	-	-	Ground
H35	0V GND	Mandatory	Mandatory	-	-	Ground
H39	0V GND	Mandatory	Mandatory	-	-	Ground
H43	0V GND	Mandatory	Mandatory	-	-	Ground
H47	0V GND	Mandatory	Mandatory	-	-	Ground
H51	0V GND	Mandatory	Mandatory	-	-	Ground
H55	0V GND	Mandatory	Mandatory	-	-	Ground
H59	0V GND	Mandatory	Mandatory	-	-	Ground
M69	0V GND	Mandatory	Mandatory	-	-	Ground
P69	0V GND	Mandatory	Mandatory	-	-	Ground
T69	0V GND	Mandatory	Mandatory	-	-	Ground
V69	0V GND	Mandatory	Mandatory	-	-	Ground
Y69	0V GND	Mandatory	Mandatory	-	-	Ground
AB69	0V GND	Mandatory	Mandatory	-	-	Ground
AD69	0V GND	Mandatory	Mandatory	-	-	Ground
AF69	0V GND	Mandatory	Mandatory	-	-	Ground
AH69	0V GND	Mandatory	Mandatory	-	-	Ground
M27	0V GND	Mandatory	Mandatory	-	-	Ground
M31	0V GND	Mandatory	Mandatory	-	-	Ground
M35	0V GND	Mandatory	Mandatory	-	-	Ground
M39	0V GND	Mandatory	Mandatory	-	-	Ground
M43	0V GND	Mandatory	Mandatory	-	-	Ground
M47	0V GND	Mandatory	Mandatory	-	-	Ground
M51	0V GND	Mandatory	Mandatory	-	-	Ground
M55	0V GND	Mandatory	Mandatory	-	-	Ground
M59	0V GND	Mandatory	Mandatory	-	-	Ground
P59	0V GND	Mandatory	Mandatory	-	-	Ground
T59	0V GND	Mandatory	Mandatory	-	-	Ground
V59	0V GND	Mandatory	Mandatory	-	-	Ground
Y59	0V GND	Mandatory	Mandatory	-	-	Ground
AB59	0V GND	Mandatory	Mandatory	-	-	Ground
AD59	0V GND	Mandatory	Mandatory	-	-	Ground
AF59	0V GND	Mandatory	Mandatory	-	-	Ground
AH59	0V GND	Mandatory	Mandatory	-	-	Ground
AW72	0V GND	Mandatory	Mandatory	-	-	Ground
AW68	0V GND	Mandatory	Mandatory	-	-	Ground
AW64	0V GND	Mandatory	Mandatory	-	-	Ground
AW60	0V GND	Mandatory	Mandatory	-	-	Ground
AW56	0V GND	Mandatory	Mandatory	-	-	Ground
AW52	0V GND	Mandatory	Mandatory	-	-	Ground
AW48	0V GND	Mandatory	Mandatory	-	-	Ground
AW44	0V GND	Mandatory	Mandatory	-	-	Ground
AW38	0V GND	Mandatory	Mandatory	-	-	Ground
AW34	0V GND	Mandatory	Mandatory	-	-	Ground
AW30	0V GND	Mandatory	Mandatory	-	-	Ground
AW26	0V GND	Mandatory	Mandatory	-	-	Ground
AW22	0V GND	Mandatory	Mandatory	-	-	Ground
AW18	0V GND	Mandatory	Mandatory	-	-	Ground
AW14	0V GND	Mandatory	Mandatory	-	-	Ground
AW10	0V GND	Mandatory	Mandatory	-	-	Ground
AT1	0V GND	Mandatory	Mandatory	-	-	Ground
AP1	0V GND	Mandatory	Mandatory	-	-	Ground
AM1	0V GND	Mandatory	Mandatory	-	-	Ground
AK1	0V GND	Mandatory	Mandatory	-	-	Ground
AH1	0V GND	Mandatory	Mandatory	-	-	Ground
AF1	0V GND	Mandatory	Mandatory	-	-	Ground
AD1	0V GND	Mandatory	Mandatory	-	-	Ground
AB1	0V GND	Mandatory	Mandatory	-	-	Ground
Y1	0V GND	Mandatory	Mandatory	-	-	Ground
V1	0V GND	Mandatory	Mandatory	-	-	Ground
T1	0V GND	Mandatory	Mandatory	-	-	Ground
P1	0V GND	Mandatory	Mandatory	-	-	Ground
M1	0V GND	Mandatory	Mandatory	-	-	Ground
K1	0V GND	Mandatory	Mandatory	-	-	Ground
H1	0V GND	Mandatory	Mandatory	-	-	Ground
F1	0V GND	Mandatory	Mandatory	-	-	Ground
D1	0V GND	Mandatory	Mandatory	-	-	Ground
AU56	0V GND	Mandatory	Mandatory	-	-	Ground
AU52	0V GND	Mandatory	Mandatory	-	-	Ground
AU48	0V GND	Mandatory	Mandatory	-	-	Ground
AU44	0V GND	Mandatory	Mandatory	-	-	Ground
AU38	0V GND	Mandatory	Mandatory	-	-	Ground
AU34	0V GND	Mandatory	Mandatory	-	-	Ground
AU30	0V GND	Mandatory	Mandatory	-	-	Ground
AU26	0V GND	Mandatory	Mandatory	-	-	Ground
AF3	0V GND	Mandatory	Mandatory	-	-	Ground
AD3	0V GND	Mandatory	Mandatory	-	-	Ground
AB3	0V GND	Mandatory	Mandatory	-	-	Ground
Y3	0V GND	Mandatory	Mandatory	-	-	Ground
V3	0V GND	Mandatory	Mandatory	-	-	Ground
T3	0V GND	Mandatory	Mandatory	-	-	Ground
P3	0V GND	Mandatory	Mandatory	-	-	Ground
AR52	0V GND	Mandatory	Mandatory	-	-	Ground
AR46	0V GND	Mandatory	Mandatory	-	-	Ground
AR36	0V GND	Mandatory	Mandatory	-	-	Ground
AR30	0V GND	Mandatory	Mandatory	-	-	Ground
AK7	0V GND	Mandatory	Mandatory	-	-	Ground
AG8	0V GND	Mandatory	Mandatory	-	-	Ground
AD7	0V GND	Mandatory	Mandatory	-	-	Ground
AA8	0V GND	Mandatory	Mandatory	-	-	Ground
W8	0V GND	Mandatory	Mandatory	-	-	Ground
T7	0V GND	Mandatory	Mandatory	-	-	Ground
N8	0V GND	Mandatory	Mandatory	-	-	Ground
K7	0V GND	Mandatory	Mandatory	-	-	Ground
AM59	0V GND	Mandatory	Mandatory	-	-	Ground
AM55	0V GND	Mandatory	Mandatory	-	-	Ground
AM51	0V GND	Mandatory	Mandatory	-	-	Ground
AM47	0V GND	Mandatory	Mandatory	-	-	Ground
AM43	0V GND	Mandatory	Mandatory	-	-	Ground
AM39	0V GND	Mandatory	Mandatory	-	-	Ground
AM35	0V GND	Mandatory	Mandatory	-	-	Ground
AM31	0V GND	Mandatory	Mandatory	-	-	Ground
AM27	0V GND	Mandatory	Mandatory	-	-	Ground
AM23	0V GND	Mandatory	Mandatory	-	-	Ground
AH13	0V GND	Mandatory	Mandatory	-	-	Ground
AF13	0V GND	Mandatory	Mandatory	-	-	Ground
AD13	0V GND	Mandatory	Mandatory	-	-	Ground
AB13	0V GND	Mandatory	Mandatory	-	-	Ground
Y13	0V GND	Mandatory	Mandatory	-	-	Ground
V13	0V GND	Mandatory	Mandatory	-	-	Ground
T13	0V GND	Mandatory	Mandatory	-	-	Ground
P13	0V GND	Mandatory	Mandatory	-	-	Ground
M13	0V GND	Mandatory	Mandatory	-	-	Ground
AH55	0V GND	Mandatory	Mandatory	-	-	Ground
AH51	0V GND	Mandatory	Mandatory	-	-	Ground
AH47	0V GND	Mandatory	Mandatory	-	-	Ground
AH43	0V GND	Mandatory	Mandatory	-	-	Ground
AH39	0V GND	Mandatory	Mandatory	-	-	Ground
AH35	0V GND	Mandatory	Mandatory	-	-	Ground
AH31	0V GND	Mandatory	Mandatory	-	-	Ground
AH27	0V GND	Mandatory	Mandatory	-	-	Ground
AH23	0V GND	Mandatory	Mandatory	-	-	Ground
AF23	0V GND	Mandatory	Mandatory	-	-	Ground
AD23	0V GND	Mandatory	Mandatory	-	-	Ground
AB23	0V GND	Mandatory	Mandatory	-	-	Ground
Y23	0V GND	Mandatory	Mandatory	-	-	Ground
V23	0V GND	Mandatory	Mandatory	-	-	Ground
T23	0V GND	Mandatory	Mandatory	-	-	Ground
P23	0V GND	Mandatory	Mandatory	-	-	Ground
M23	0V GND	Mandatory	Mandatory	-	-	Ground
12 (HOLE)	0V GND	Mandatory	Mandatory	-	-	Ground
11 (HOLE)	0V GND	Mandatory	Mandatory	-	-	Ground
10 (HOLE)	0V GND	Mandatory	Mandatory	-	-	Ground
9 (HOLE)	0V GND	Mandatory	Mandatory	-	-	Ground
8 (HOLE)	0V GND	Mandatory	Mandatory	-	-	Ground
7 (HOLE)	0V GND	Mandatory	Mandatory	-	-	Ground
6 (HOLE)	0V GND	Mandatory	Mandatory	-	-	Ground
5 (HOLE)	0V GND	Mandatory	Mandatory	-	-	Ground
4 (Anker-Joint)	0V GND	Mandatory	Mandatory	-	-	Ground
3 (Anker-Joint)	0V GND	Mandatory	Mandatory	-	-	Ground
2 (Anker-Joint)	0V GND	Mandatory	Mandatory	-	-	Ground
1 (Anker-Joint)	0V GND	Mandatory	Mandatory	-	-	Ground

FPSC GND Signal Locations

Specialized Pins

Specialized pins are reserved for unique processor or SOM interfaces that are not standardized within the FPSC Gamma (Lite) pinout. These pins are routed to module pins so that all processor features can be accessed and utilized without restrictions, even if they are not part of the standardized pinout. Using these signals makes cross-module compatibility unlikely and cannot be guaranteed. However, using specialized pins alongside FPSC-compliant pins does not affect the compatibility of the compliant pins. Some pins may be reserved for future use in case new, unforeseen interfaces are introduced through revisions of the FPSC standard. For more information about these interfaces and signals, refer to the hardware manual specific to your SOM. The manual details signal names, types, voltage domains, and recommended configurations.

Pin Number	Signal Name	Signal Requirement Gamma	Signal Requirement Gamma Lite	I/O Type	I/O Level	Notes
E26	Reserved	Specialized	Specialized	-	-	Non FPSC Compatible. For FPSC Compatibility, leave open. See the Hardware manual for functional details if desired.
E28	Reserved	Specialized	Specialized	-	-
E32	Reserved	Specialized	Specialized	-	-
E34	Reserved	Specialized	Specialized	-	-
E38	Reserved	Specialized	Specialized	-	-
E40	Reserved	Specialized	Specialized	-	-
E42	Reserved	Specialized	Specialized	-	-
E44	Reserved	Specialized	Specialized	-	-
E48	Reserved	Specialized	Specialized	-	-
E50	Reserved	Specialized	Specialized	-	-
E54	Reserved	Specialized	Specialized	-	-
E56	Reserved	Specialized	Specialized	-	-
H75	Reserved	Specialized	Specialized	-	-
J74	Reserved	Specialized	Specialized	-	-
L74	Reserved	Specialized	Specialized	-	-
M75	Reserved	Specialized	Specialized	-	-
P75	Reserved	Specialized	Specialized	-	-
R74	Reserved	Specialized	Specialized	-	-
U74	Reserved	Specialized	Specialized	-	-	Non FPSC Compatible. For FPSC Compatibility, leave open. See the Hardware manual for functional details if desired.
V75	Reserved	Specialized	Specialized	-	-
Y75	Reserved	Specialized	Specialized	-	-
AB75	Reserved	Specialized	Specialized	-	-
AC74	Reserved	Specialized	Specialized	-	-
AE74	Reserved	Specialized	Specialized	-	-
AF75	Reserved	Specialized	Specialized	-	-
AH75	Reserved	Specialized	Specialized	-	-
AJ74	Reserved	Specialized	Specialized	-	-
AL74	Reserved	Specialized	Specialized	-	-
H7	Reserved	Specialized	Specialized	-	-
G22	Reserved	Specialized	Specialized	-	-
G24	Reserved	Specialized	Specialized	-	-
G26	Reserved	Specialized	Specialized	-	-
G28	Reserved	Specialized	Specialized	-	-
G30	Reserved	Specialized	Specialized	-	-
G32	Reserved	Specialized	Specialized	-	-
G34	Reserved	Specialized	Specialized	-	-
G36	Reserved	Specialized	Specialized	-	-
G46	Reserved	Specialized	Specialized	-	-
G48	Reserved	Specialized	Specialized	-	-
G50	Reserved	Specialized	Specialized	-	-
G52	Reserved	Specialized	Specialized	-	-
L70	Reserved	Specialized	Specialized	-	-
M71	Reserved	Specialized	Specialized	-	-
H25	Reserved	Specialized	Specialized	-	-
H29	Reserved	Specialized	Specialized	-	-
H33	Reserved	Specialized	Specialized	-	-
H37	Reserved	Specialized	Specialized	-	-
H49	Reserved	Specialized	Specialized	-	-
H53	Reserved	Specialized	Specialized	-	-
L68	Reserved	Specialized	Specialized	-	-
N68	Reserved	Specialized	Specialized	-	-
R68	Reserved	Specialized	Specialized	-	-
U68	Reserved	Specialized	Specialized	-	-
AA68	Reserved	Specialized	Specialized	-	-
AC68	Reserved	Specialized	Specialized	-	-
J28	Reserved	Specialized	Specialized	-	-
J30	Reserved	Specialized	Specialized	-	-
J32	Reserved	Specialized	Specialized	-	-
J34	Reserved	Specialized	Specialized	-	-	Non FPSC Compatible. For FPSC Compatibility, leave open. See the Hardware manual for functional details if desired.
J36	Reserved	Specialized	Specialized	-	-
J46	Reserved	Specialized	Specialized	-	-
J48	Reserved	Specialized	Specialized	-	-
J50	Reserved	Specialized	Specialized	-	-
J52	Reserved	Specialized	Specialized	-	-
J54	Reserved	Specialized	Specialized	-	-
M67	Reserved	Specialized	Specialized	-	-
N66	Reserved	Specialized	Specialized	-	-
P67	Reserved	Specialized	Specialized	-	-
AJ42	Reserved	Specialized	Specialized	-	-
AJ40	Reserved	Specialized	Specialized	-	-
AJ38	Reserved	Specialized	Specialized	-	-
AJ36	Reserved	Specialized	Specialized	-	-
AJ34	Reserved	Specialized	Specialized	-	-
AJ26	Reserved	Specialized	Specialized	-	-
M49	Reserved	Specialized	Specialized	-	-
AH41	Reserved	Specialized	Specialized	-	-
AH37	Reserved	Specialized	Specialized	-	-
AM75	Reserved	Specialized	Specialized	-	-
AR56	Reserved	Specialized	Specialized	-	-
AR54	Reserved	Specialized	Specialized	-	-
AR50	Reserved	Specialized	Specialized	-	-
AR48	Reserved	Specialized	Specialized	-	-
AR44	Reserved	Specialized	Specialized	-	-
AR42	Reserved	Specialized	Specialized	-	-
AR40	Reserved	Specialized	Specialized	-	-
AR38	Reserved	Specialized	Specialized	-	-
AR34	Reserved	Specialized	Specialized	-	-
AR32	Reserved	Specialized	Specialized	-	-
AR28	Reserved	Specialized	Specialized	-	-
AR26	Reserved	Specialized	Specialized	-	-
AM7	Reserved	Specialized	Specialized	-	-
AL8	Reserved	Specialized	Specialized	-	-
AJ8	Reserved	Specialized	Specialized	-	-
AH7	Reserved	Specialized	Specialized	-	-
AF7	Reserved	Specialized	Specialized	-	-
AE8	Reserved	Specialized	Specialized	-	-
AC8	Reserved	Specialized	Specialized	-	-
AB7	Reserved	Specialized	Specialized	-	-
Y7	Reserved	Specialized	Specialized	-	-	Non FPSC Compatible. For FPSC Compatibility, leave open. See the Hardware manual for functional details if desired.
V7	Reserved	Specialized	Specialized	-	-
U8	Reserved	Specialized	Specialized	-	-
R8	Reserved	Specialized	Specialized	-	-
P7	Reserved	Specialized	Specialized	-	-
M7	Reserved	Specialized	Specialized	-	-
L8	Reserved	Specialized	Specialized	-	-
J8	Reserved	Specialized	Specialized	-	-
N70	Reserved	Specialized	Specialized	-	-
P71	Reserved	Specialized	Specialized	-	-
R70	Reserved	Specialized	Specialized	-	-
AJ70	Reserved	Specialized	Specialized	-	-
AN62	Reserved	Specialized	Specialized	-	-
AN20	Reserved	Specialized	Specialized	-	-
W12	Reserved	Specialized	Specialized	-	-
V11	Reserved	Specialized	Specialized	-	-
U12	Reserved	Specialized	Specialized	-	-
T11	Reserved	Specialized	Specialized	-	-
R12	Reserved	Specialized	Specialized	-	-
P11	Reserved	Specialized	Specialized	-	-
N12	Reserved	Specialized	Specialized	-	-
M11	Reserved	Specialized	Specialized	-	-
L12	Reserved	Specialized	Specialized	-	-
AE68	Reserved	Specialized	Specialized	-	-
AG68	Reserved	Specialized	Specialized	-	-
AJ68	Reserved	Specialized	Specialized	-	-
AM53	Reserved	Specialized	Specialized	-	-
AM37	Reserved	Specialized	Specialized	-	-
AM33	Reserved	Specialized	Specialized	-	-
AM29	Reserved	Specialized	Specialized	-	-
R14	Reserved	Specialized	Specialized	-	-
N14	Reserved	Specialized	Specialized	-	-
L14	Reserved	Specialized	Specialized	-	-
J24	Reserved	Specialized	Specialized	-	-
J26	Reserved	Specialized	Specialized	-	-
R66	Reserved	Specialized	Specialized	-	-
T67	Reserved	Specialized	Specialized	-	-
U66	Reserved	Specialized	Specialized	-	-
AL30	Reserved	Specialized	Specialized	-	-
AL28	Reserved	Specialized	Specialized	-	-
AA16	Reserved	Specialized	Specialized	-	-	Non FPSC Compatible. For FPSC Compatibility, leave open. See the Hardware manual for functional details if desired.
N16	Reserved	Specialized	Specialized	-	-
M15	Reserved	Specialized	Specialized	-	-
L36	Reserved	Specialized	Specialized	-	-
L48	Reserved	Specialized	Specialized	-	-
AH33	Reserved	Specialized	Specialized	-	-
AH25	Reserved	Specialized	Specialized	-	-
AG42	Reserved	Specialized	Specialized	-	-
AG40	Reserved	Specialized	Specialized	-	-
AG38	Reserved	Specialized	Specialized	-	-
AG36	Reserved	Specialized	Specialized	-	-
AG34	Reserved	Specialized	Specialized	-	-
AG26	Reserved	Specialized	Specialized	-	-
AF25	Reserved	Specialized	Specialized	-	-
W70	Reserved	Specialized	Specialized	-	-
V71	Reserved	Specialized	Specialized	-	-
U70	Reserved	Specialized	Specialized	-	-
T71	Reserved	Specialized	Specialized	-	-
AH67	Reserved	Specialized	Specialized	-	-
AG66	Reserved	Specialized	Specialized	-	-
AH71	Reserved	Specialized	Specialized	-	-
AG70	Reserved	Specialized	Specialized	-	-
AD67	Reserved	Specialized	Specialized	-	-
AD71	Reserved	Specialized	Specialized	-	-
AA66	Reserved	Specialized	Specialized	-	-
Y67	Reserved	Specialized	Specialized	-	-
AA70	Reserved	Specialized	Specialized	-	-
Y71	Reserved	Specialized	Specialized	-	-
W66	Reserved	Specialized	Specialized	-	-
W68	Reserved	Specialized	Specialized	-	-
V21	Reserved	Specialized	Specialized	-	-
W20	Reserved	Specialized	Specialized	-	-
V25	Reserved	Specialized	Specialized	-	-
W22	Reserved	Specialized	Specialized	-	-
W24	Reserved	Specialized	Specialized	-	-
N28	Reserved	Specialized	Specialized	-	-
P15	Reserved	Specialized	Specialized	-	-
Y25	Reserved	Specialized	Specialized	-	-
AD21	Reserved	Specialized	Specialized	-	-

FPSC Reserved Signals

Mechanical Layer

Module

To offer an optimal balance between compatibility and board space efficiency, PHYTEC defines three footprint sizes within the FPSC specification. Smaller modules are fully compatible with larger footprints, allowing for flexible upgrades without the need to modify the carrier board.

Footprint sizes:

Size S is the most compact option and supports most FPSC modules. It includes all mandatory and optional pins, making it suitable for most typical applications.
Size M extends the footprint to include additional specialized signals. It offers increased flexibility while maintaining reasonable compactness, making it a safe choice for customers who want to accommodate current and potential future modules without occupying excessive space.
Size L provides the maximum possible footprint and ensures full forward compatibility with any future FPSC modules. Although it is rarely necessary today, it offers the highest level of design security for long-term upgradability.

When developing new FPSC module designs, PHYTEC aims to achieve the smallest possible footprint. In most cases, the S or M footprint meets design requirements, and the L footprint is an option for customers who prioritize maximum future compatibility.

Features	Size S (40 x 45 mm)	Size M (48 x 45 mm)	Size L (53 x 50 mm)
Pins Included	Mandatory, Optional, and select Specialized pins	All Mandatory, Optional, and Specialized pins	All pins and additional ground pins
Board Space	Minimal (most compact)	Moderate	Largest
Module Compatibility	Majority of current modules	Majority of current and future modules	All current and future modules

Differences Among Footprint Sizes

Baseboard

Footprint

The following image is the suggested footprint for baseboard designs.

Footprint for Baseboard

Anchor Joints

In addition to the functional signal pins, solder connections in the form of anchor joints are required to connect the assembly, which includes the baseboard and SOM. While these anchor joints are connected to ground, their primary purpose is to mechanically stabilize the connection. They are designed to evenly distribute forces acting on the circuit boards and relieve the signal pins. Further details on soldering can be found in Soldering Guide - FPSC-Based Products Fused Tin Grid Array (FTGA) Information (LAN-128e.A4) - Solder Paste Optimization.

Desoldering

PHYTEC provides a desoldering tool designed specifically for removing FPSC modules from soldered carrier boards. This tool supports replacing modules or exchanging carrier boards during prototyping and small-batch production. Contact your PHYTEC representative for detailed instructions and specifications.

Pin Numbering

The following image shows pin numbering schematic.

FPSC Baseboard Pin Numbering - Top View

Thermal Management/Drill Holes

Surface enlargements, i.e., heat sinks, are custom-built for each FPSC SOM. As shown in the figure above, the FPSC footprint defines the contact surfaces and metal-reinforced holes for fastening the surface enlargement to the SOM. The holes on the baseboard can be omitted if the PHYTEC heat solution is not used, such as for a device-specific heat dissipation concept affixed to an SOM.

Design Considerations for Single-Sided SOMs (No Baseboard Cutout Required)

Standard SOMs are populated on both sides, requiring a cutout in the baseboard. This results in lost routing and component placement area beneath the module. Alternatively, single-sided, populated SOMs can be used to eliminate the need for a cutout and preserve the full baseboard area for routing and assembly. However, this design decision must be made early in the development phase because a baseboard without a cutout is exclusively compatible with single-sided SOMs. Refer to the relevant SOM manual to determine the population variant and evaluate whether the gained layout area justifies limiting the design to single-sided modules.

Electrical Layer

Operating Ground/GND

Operating Ground Pins

Operating ground pins are marked black in the picture above. In addition to the retaining pads, ground consists of the following pins:

Zone	Pin Numbers
1	M23, P23, T23, V23, Y23, AB23, AD23, AF23, AH23, AH27, AH31, AH35, AH39, AH43, AH47, AH51, AH55, AH59, AF59, AD59, AB59, Y59, V59, T59, P59, M59, M55, M51, M47, M43, M39, M35, M31, M27
2	M13, P13, T13, V13, Y13, AB13, AD13, AF13, AH13, AM23, AM27, AM31, AM35, AM39, AM43, AM47, AM51, AM55, AM59, AH69, AF69, AD69, AB69, Y69, V69, T69, P69, M69, H59, H55, H51, H47, H43, H39, H35, H31, H27, H23
3	K7, N8, T7, W8, AA8, AD7, AG8, AK7, AR30, AR36, AR46, AR52, AK75, AG74, AD75, AA74, W74, T75, N74, K75, E52, E46, E36, E30, AU26, AU30, AU34, AU38, AU44, AU48, AU52, AU56, C56, C52, C48, C44, C38, C34, C30, C26
4	P3, T3, V3, Y3, AB3, AD3, AF3, D1, F1, H1, K1, M1, P1, T1, V1, Y1, AB1, AD1, AF1, AH1, AK1, AM1, AP1, AT1, AW10, AW14, AW18, AW22, AW26, AW30, AW34, AW38, AW44, AW48, AW52, AW56, AW60, AW64, AW68, AW72, AF79, AD79, AB79, Y79, V79, T79, P79, AT81, AP81, AM81, AK81, AH81, AF81, AD81, AB81, Y81, V81, T81, P81, M81, K81, H81, F81, D81, A72, A68, A64, A60, A56, A52, A48, A44, A38, A34, A30, A26, A22, A18, A14, A10

FPSC Operating Ground Pins

Electrical Characteristics

Recommended Operation Conditions

Parameter		Min	Typ	Max	Unit	Notes
Supply Voltage	VCC	4.75	5	5.25	V
Supply Current	ICC	-	-	5	A
Open-Drain Logic High-level input voltage	VODIH	1.26	-	VCC	V
Open-Drain Logic Low-level input current	IODIL	5	-	-	mA	Required sink current capability of the open-drain output at the low level.
Logic High-level input voltage	VIH	1.27	1.8	1.98	V
Logic Low-level input voltage	VIL	-0.3	0	0.54	V
Logic High-level output voltage	VOH	1.44	1.8	2.1	V
Logic Low-level output voltage	VOL	-0.3	0	0.36	V

FPSC Recommended Operation Conditions

Power Sequencing

All PHYTEC FPSC SOMs have an internal power management system (PMIC), which controls individual processor voltages and control signals. If the power sequencing is incorrect, complex processors can go into unpredictable states. Therefore, it is imperative that the specified power sequencing is not affected by the user's custom design.

Power-up

All PHYTEC modules start power-up sequencing automatically after the input supply voltage is applied. To simplify the design-in, the power-up in PHYTEC SOMs is designed around three control lines:

nPWRREADY_OUT (Pin U22)
nRESET_OUT (Pin R22)
nRESET_IN (Pin Y21)

nPWRREADY_OUT

The open-drain output on the SOM requires an external pull-up resistor. While it is recommended to connect the pull-up resistor to the SOM input voltage, the signal is rated for voltages up to 12V. During initial power-up of the SOM, the nPWRREADY_OUT pin floats high until all processor voltages are properly brought up. At this point, the nPWRREADY_OUT pin is pulled to ground (GND). Once this occurs, voltages can be safely applied to the SOM I/O pins. It is Mandatory that nPWRREADY_OUT be used to control the power to the peripherals connected to the SOM in your custom CB.

nRESET_OUT

This is an open-drain output on the SOM with an internal pull-up resistor to 1.8 V. nRESET is held to GND during the initial power sequencing. After nPWRREADY_OUT is pulled to ground, nRESET_OUT remains held to ground until the SOM processor has finished its internal reset procedure and latched the boot mode pins. At this point, nRESET_OUT switches to high impedance. All baseboard peripheral voltages must ramp up during this time. The length of time between nPWRREADY_OUT going low and nRESET_OUT going high depends on the SOM. If your CB voltages require more time to ramp up, you can hold nRESET_IN at GND on the baseboard for as long as necessary to keep nRESET_OUT low and the processor in its reset state.
It is recommended that you connect nRESET_OUT to the reset inputs of your CB peripherals.

nRESET_IN

This is an open-drain input to the SOM with an internal pull-up resistor (1.8 V to VCC_IN). The nRESET_IN pin is used to perform a CPU reset. When the signal changes from high to low, the SOM cycles the internal power rails necessary to fully reset the SOM, driving nRESET_OUT low and switching nPWRREADY_OUT to a high-impedance state while the power rails reinitialize. As previously mentioned, nRESET_IN can be used to keep the processor in the reset state by holding it low after nPWRREADY_OUT goes low. In this scenario, the rising edge of nRESET_IN will trigger the processor to finish its reset sequence and begin booting.

Reset and Power Timing Chart

VCC_5V_SOM: SOM Supply Voltage
nPWRREADY_OUT: SOM Open-Drain Output. An external Pull-up is needed. See above.
nRESET_OUT: Open-Drain Output, Reset Output for Basboard devices
nRESET_IN: Open-Drain Input, CPU Reset (State-Controlled) / PWR Reset (on falling edge), minimum low time 100µs
VCC_#: Any peripheral power supply of the baseboard.

When designing the power sequencing for your baseboard, consider what would happen in the event of a momentary loss of external power. You may be using peripherals that operate with a power-on reset. To ensure these peripherals always remain in a defined state, discharging the voltages switched via nPWRREADY_OUT may be useful.

Power-cycle/Reset

The nRESET_IN pin (Y21) is an open-drain input with an internal pull-up resistor. Use nRESET_IN to trigger a reset or power cycle the module. You can connect nRESET_IN to a push-button or an open-drain output. When the nRESET_IN pin goes low, the module will start the reset sequence and the nPRWREADY (pin U22) pin will be set to a HIGH-Z state. When the nRESET_IN signal rises, the processor finishes its reset sequence and begins the boot process. This causes the nRESET_OUT signal to be set to a HIGH-Z state.

IO Voltage

The FPSC Gamma (Lite) specification sets the input/output (IO) voltage to 1.8 V for all interfaces, enabling optimal system integration. However, some SOMs offer the option of changing the I/O voltage of various signal groups to 3.3 V, should it be necessary for your application. Please note that this option is limited by the characteristics of the processor used and requires prior technical testing. Using this option will also cause your design to exceed the specifications of the FPSC Gamma (Lite) Feature Set.

Revision History

Version	Changes	Release Date
LAN-118e.A0	Preliminary Manual	02.12.2024
LAN-118e.A1	Updated Featureset Signal Table Updated information regarding Featureset Signals and Subclasses	24.04.2025
LAN-118e.A2	Updated information regarding Featureset Signals and Subclasses	23.05.2025
LAN-118e.A3	Added Anchor Joint Solder Paste Information	22.08.2025
LAN-118e.A4	Updated FPSC Pin Signal information	04.09.2025
LAN-118e.A5	Updated Pin Signal information Updated color coordination of FPSC Signals	15.09.2025
LAN-118e.A6	Updated Naming Convention: phyFLEX (previously phyCORE)	14.10.2025
LAN-118e.A7	Updated manual to include Lite information Format rework	28.05.2026

FPSC Gamma (Lite) Feature Set Specifications (LAN-118e.7)

Table of Contents

FPSC Gamma (Lite) Feature Set Introduction

FPSC Physical Advantages

FPSC Feature Set Module Universal Pinout

Documentation and Standard References

FPSC Definition Overview

Abbreviations and Acronyms

FPSC Interface Summary

Functionality

Interfaces

Gamma vs. Gamma Lite

FPSC Feature Set Requirements

FPSC Interface/Signal Types

Pinout

PWR/CTRL

Boot Source Selection

GPIO/PWM

SAI/I2S

QSPI

ADC

SDIO

SD Card Interface

SDIO Interface

CAN

I2C/I3C

SPI

UART

PCIe

LVDS

HDMI

DSI

CSI

Ethernet

RGMII

USB

GND

Specialized Pins

Mechanical Layer

Module

Baseboard

Footprint

Anchor Joints

Desoldering

Pin Numbering

Thermal Management/Drill Holes

Design Considerations for Single-Sided SOMs (No Baseboard Cutout Required)

Electrical Layer

Operating Ground/GND

Electrical Characteristics

Recommended Operation Conditions

Power Sequencing

Power-up

nPWRREADY_OUT

nRESET_OUT

nRESET_IN

Power-cycle/Reset

IO Voltage

Revision History

Contact Information