Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (™ or ®) and copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents and trademarks are similarly not expressly indicated in this manual.

The information in this document has been carefully checked and is considered to be entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result.

Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so.

@ Copyright 2022 PHYTEC Messtechnik GmbH, D-55129 Mainz.

Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH.

Information on this Manual

This hardware manual describes the PCL-066 System on Module, referred to as phyCORE®-i.MX 8M, and the PBA-CD-12, referred to as phyBOARD®-Polaris. This manual also specifies the phyCORE-i.MX 8M and phyBOARD-Polaris' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M microcontrollers can be found in the i.MX 8M Microcontroller Data Sheet/Reference Manual.

Design Considerations

The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and is known to work. The schematics have been re-formatted to fit better in this hardware manual.

Many hardware examples and suggestions are given in the following pages. Designing the phyCORE System on Module onto a Carrier Board is generally straightforward. However, before committing to a particular active component selection when designing a carrier board, it is wise to check out the software driver support for those components. A particular device may be supported in, say, for example, Linux but not in Windows Embedded Compact 7. Your overall project may go smoother if you pick components that are already supported in your target OS. The premade selections for our reference designs, for example our Single Board Computers, are typically focused on using components that are well supported under Linux.

Specific details may need to be considered when designing a customer-specific carrier board. For design information on carrier board components, please check the Design Considerations in each component section of phyCORE-i.MX 8M on the phyBOARD-Polaris. Be aware that not all components need to be considered when designing your own carrier board.

Preface

As a member of PHYTEC's phyCORE^® product family, the phyCORE‑i.MX 8M is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers, various types of memory (RAM, NAND flash, eMMC), and many other features. This, in turn, offers increased types of functions and configurations. PHYTEC supports a variety of 8/16/32/64 bit controllers in two ways:

1. As the basis for Rapid Development Kits which serve as a reference and evaluation platform
2. As insert-ready, fully functional phyCORE^® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "reinvent" microcontroller circuitry. Furthermore, much of the value of the phyCORE^® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative, full-system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Ordering Information

The part numbering of the phyCORE has the following structure:

Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
http://www.phytec.de/support/knowledge-database/soms-system-on-modules/phycore/phycore-imx-8m/ 
or
https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-download/

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE^®‑i.MX 8M 

PHYTEC System on Module (henceforth products) are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly with respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Product Change Management and Information Regarding Parts Populated on the SOM / SBC

With the purchase of a PHYTEC SOM / SBC, you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCNs (Product Change Notifications) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.

Our general philosophy here is: We will never discontinue a product as long as there is a demand for it.

To fulfill this, we have established a set of methods to fulfill our philosophy:

Avoidance strategies:

• Avoid changes by evaluating the longevity of parts during the design-in phase.
• Ensure the availability of equivalent second source parts.
• Stay in close contact with part vendors to keep up with roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

• Ensure long-term availability by stocking parts through last-time buy management according to product forecasts.
• Offer long-term frame contracts to customers.

Change management in cases of functional changes:

• Avoid impacts on product functionality by choosing equivalent replacement parts.
• Avoid impacts on product functionality by compensating for changes through hardware redesign or backward-compatible software maintenance.
• Provide early change notifications concerning functional, relevant changes to our products.

We refrain from providing detailed part-specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

• QS Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a BSP, the device tree, and accessing peripherals.
• Hardware Manual:  A detailed description of the System on Module and accompanying carrier board. 
• Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; introducing, installing, and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
• BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
• Development Environment Guide:  This guide shows how to work with the Virtual Machine (VM) Host PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running demo projects for these programs on a phyCORE product as well. Information on how to build a Linux host PC yourself is also a part of this guide.
• Pin Muxing Table:  phyCORE SOMs have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case-by-case basis. Most of the documentation can be found on the applicable download page of our products.

These manuals and more can be found in the download section of phyCORE-i.MX 8M Product page.

Conversions, Abbreviations, and Acronyms

This hardware manual describes the PCL-066 System on Module, referred to as phyCORE^®-i.MX 8M, and the PB-02419-xxxI.Ax, referred to as phyBOARD^®-Polaris. This manual also specifies the phyCORE-i.MX 8M and phyBOARD-Polaris' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M microcontrollers can be found in the i.MX 8M Microcontroller Data Sheet/Reference Manual.

Conventions

The conventions used in this manual are as follows:

• Signals that are preceded by an "n", "/", or “#” character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low or are driving low.
• A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
• The hex numbers are given for addresses of I²C devices always represent the 7 MSB of the address byte. The correct value of the LSB, which depends on the desired command (read (1), or write (0)), must be added to get the complete address byte. For example, if the given address in this manual is 0x41 =>, the complete address byte = 0x83 to read from the device and 0x82 to write to the device
• Tables that describe all settings show the default position in bold,bluetext.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of a signal.

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document.

phyCORE-i.MX 8M Introduction

The phyCORE‑i.MX 8M belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all EMI (Electro-Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 20 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high-noise environments.

phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting-edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 8M is a subminiature (40 mm x 55 mm) soldered System on Module populated with the NXP® Semiconductor i.MX 8M microcontroller. Its universal design enables it to be inserted into a wide range of embedded applications. All controller signals and ports extend from the controller to a 1,27mm Pitch BGA Ball. Each signal ball has an associated GND pin which ensures the GND reference for each signal. The ball packages are placed in lines. There is enough space between lines to ensure the possibility to easy routing out of the package. Signal balls for high-speed signals like HDMI are placed on the outer lines, making it easy to route to the top layer of the carrier board. The SOM is designed to support carrier boards with as few as 6 layers to reduce PCB costs. For proper EMC characteristics, it is necessary to place the processor caps directly under the SOM. This required a hole in the carrier board.

The descriptions in this manual are based on the NXP® Semiconductor i.MX 8M. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 8M.

phyCORE-i.MX 8M Features

The phyCORE‑i.MX 8M offers the following features:

• Insert-ready, sub-miniature (55 mm x 40 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology
• Mounted using BGA Technology
• Populated with the NXP® Semiconductor i.MX 8M microcontroller (BGA624 packaging)
• Up to 4 ARM-A53 cores (clock frequency up to 1.5 GHz)
• Boot from different memory devices (eMMC Flash standard)
• Single supply voltage of +3.3 V with onboard power management
• All controller-required supplies are generated on board
• Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins

• up to 8 GB^[1]LPDDR4 RAM

• up to 64 GB^[1] onboard eMMC in commercial temperature range (up to 32 GB for I-Temp)
• up to 64 MB^[1] Quad SPI Nor Flash
• 4kB^[1] I²C EEPROM
• 2x USB 3.0/2.0 OTG interfaces

• 10/100/1000 Mbit Ethernet interface (either with Ethernet transceiver on the phyCORE-i.MX 8M enabling a direct connection to an existing Ethernet network, or without onboard transceiver and using the RGMII signals at TTL-level at the signal pins instead.)^[2]

• 802.11 b/g/n WLAN/Bluetooth V4.2 (optional)
• 3x I²C interfaces (+1 used at SOM)
• 2x SPI interfaces (NAND/QSPI)
• 1x PCIe interface
• 4x UART interfaces
• 4x  PWM outputs
• 1x MIPI DSI interface
• 1x HDMI interface
• 2x  MIPI CSI camera interface
• 1x SDIO interface
• 1x SAI Audio interface
• Extreme Low Power RTC Module
• Available for different temperature grades (see Product Temperature Grades)

phyCORE-i.MX 8M Block Diagram

phyCORE-i.MX 8M Component Placement

phyCORE-i.MX 8M Minimum Operating Requirements 

Pin Description

All controller signals extend to BGA Signal Balls (1.27 mm) This allows the phyCORE‑i.MX 8M to be soldered into any target application like a "big chip".

PHYTEC provides a complete pinout table for the phyCORE-i.MX 8M Mini Connector (X31). This table contains a complete signal path for the phyCORE‑i.MX 8M and the carrier board phyBOARD-Polaris, including signal names, pin muxing paths, and descriptions specific to each pin. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found with the pinout table.

https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-download/#pin-description

Jumpers

For configuration purposes, the phyCORE‑i.MX 8M has several solder jumpers, some of which have been installed prior to delivery. Typical Jumper Pad Numbering Scheme illustrates the numbering scheme for the various solder jumper pads. Jumper Locations (Top View) and Jumper Locations (Bottom View) indicate the location and the default configuration of the solder jumpers on the board.

The Jumper Settings table provides a functional summary of the solder jumpers which can be changed to adapt the phyCORE‑i.MX 8M to specific design needs. It shows their default positions, and possible alternative positions and functions. A detailed description of each solder jumper can be found in the applicable chapter listed in the table.

If manual jumper modification is required, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable.  If soldered jumpers need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station, or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Pay special attention to the “TYPE” column to ensure you are using the correct type of jumper (0 Ohms, 10k Ohms, etc…). The jumpers are 0201 packages with a 1/8 W or better power rating.

The jumpers (J = solder jumper) have the following functions.

Power

The phyCORE‑i.MX 8M operates off of a single power supply voltage. The following section discusses the primary power pins on the phyCORE i.MX 8M Connector X1 in detail.

Primary System Power (VDD_IN_3V3)

The phyCORE‑i.MX 8M is powered by a primary voltage supply with a nominal value of +3.3 V. Onboard switching regulators generate the voltage supplies required by the i.MX 8M MCU and onboard components from the primary 3.3 V supplied to the SOM.

For proper operation, the phyCORE‑i.MX 8M must be supplied with a voltage source of 3.3 V ±5 % with a 3 A load at the VCC pins on the phyCORE.

                VDD_IN_3V3:                        X1 → A65, A66, A67, A68

Connect all +3.3 V VCC input pins to your power supply and, at minimum, the matching number of GND pins.

                Corresponding GND:           X1 → B33, B34

Please refer to the section Pin Description for information on additional GND Pins located at the phyCORE i.MX 8M Connector X1.

Power Management IC (PMIC) (U2)

The phyCORE-i.MX 8M provides an onboard Power Management IC (PMIC) at position U2 to generate different voltages required by the microcontroller and the onboard components. The PMIC supports many functions like different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 8M via the onboard I²C bus (I2C1). The I²C address of the PMIC is 0x08.

The PMIC Shutdown is controllable either by GPIO or by an external signal from the carrier board. If the signal is controlled by the carrier board, GPIO1_IO14 is available as a normal GPIO on the carrier board. The table below shows the different jumper options:

Power Domains

External voltages:

• VDD_IN_3V3 3.3 V main supply voltage
• USB0_VBUS USB0 bus voltage must be supplied with 5 V if USB0 is used (does not exceed 5.25V)
• USB1_VBUS USB1 bus voltage must be supplied with 5 V if USB1 is used (does not exceed 5.25V)
• VRTC  Backup Supply for RTC (40nA)

External Logic Supply Voltage

The voltage level of the phyCORE’s logic circuitry is VDD_3V3 (3.3 V) or VDD_1V8 (1.8 V) which is derived from the SOM main input voltage, VDD_IN_3V3. In order to follow the power-up and power-down sequencing mandatory for the i.MX 8M, external devices have to be supplied by the I/O supply voltage VDD_3V3 or VDD_1V8 which is brought out at pin A53/A54 (VDD_3V3) and A91/A92 (VDD_1V8) of the phyCORE-Connector. The use of VDD_3V3_LOGIC ensures that external components are only supplied when the supply voltages of the i.MX 8M is stable.

If used to control or supply bus switches on the phyCORE side, VDD_3V3 (VDD_1V8) also serves to strictly separate the supply voltages generated on the phyCORE‑i.MX 8M and the supply voltages used on the carrier board/custom application. That way, voltages at the IO pins of the phyCORE-i.MX 8M, which are sourced from the supply voltage of peripheral devices attached to the SOM, are avoided. These voltages can cause a current flow into the controller, especially if peripheral devices attached to the interfaces of the i.MX 8M are supposed to be powered while the phyCORE‑i.MX 8M is in suspend mode or turned off. The bus switches can either be supplied by VDD_3V3 (VDD_1V8) on the phyCORE side or the bus switches' output enabled to the SOM can be controlled by X_PGOOD_OD to prevent these voltages from occurring.

The use of level shifters supplied with VDD_3V3 (VDD_1V8) allows the signals to be converted according to the needs of the custom target hardware. Alternatively, signals can be connected to an open drain circuitry with a pull-up resistor attached to VDD_3V3 (VDD_1V8).

Backup Power (VRTC / NVCC_SNVS)

To back up the RTC (U27), an external voltage source can be added at Pin E36. The RTC has an extremely low backup current consumption of only 40nA (@3 V). It is also possible to supply the RTC and some critical registers of the i.MX 8M's low power domain (NVCC_SNVS). NVCC_NSNVS can be supplied over Pin E19 if VDD_IN_3V3 is not present. 

Reset

The X_nRESET_IN signal (Pin A62) on the phyCORE-Connector is designated as the reset input. Holding this pin low triggers a hard reset of the module. The external reset signal has a 10ms debouncing circuit. X_POR_B Signal (Pin A61) can be used to prevent bootup of the i.MX8M. This can be used as a startup as described in the section Power Management IC. 

System Boot Configuration

Most features of the i.MX 8 microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

• Boot mode selection
• Boot device selection
• Boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 8M after POR. The ROM code detects the boot mode by using the boot mode pins (BOOT_MODE[1:0]), while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO input pins (BOOT_CFGx[7:0]).

Boot Mode Selection

The boot mode of the i.MX 8M microcontroller is determined by the configuration of two boot mode inputs BOOT_MODE[1:0] during the reset cycle of the operational system. These inputs are brought out at the phyCORE processor pins X_BOOT_MODE[1:0] (D1, C1). The table phyCORE-i.MX 8M Boot Modes shows the possible settings of pins X_BOOT_MODE0 (C1) and X_ BOOT_MODE1 (D1) and the resulting boot configuration of the i.MX 8M.

The BOOT_MODE[1:0] lines have 10 kΩ pull-up and pull-down resistors populated on the module. Leaving the two pins unconnected sets the controller to boot mode 2, internal boot. For serial boot (boot mode = 1), the ROM code polls the communication interface selected, initiates the download of the code into the internal RAM, and triggers its execution from there. Please refer to the i.MX 8M Reference Manual for more information.

In boot modes 0 and 2, the ROM code finds the bootstrap in permanent memories such as NAND-Flash or SD-Cards and executes it. The selection of the boot device and the configuration of the interface required are accomplished with the help of the eFUSEs and/or the corresponding GPIO input pins.

Boot Device Selection and Configuration

In normal operation (boot mode 0, or 2), the boot ROM uses the state of BOOT_MODE and eFUSEs to determine the boot device.

During development, it is advisable to set the boot type to “Internal boot” (BOOT_MODE[1:0]=10⁴ so that choosing and configuring the boot device using GPIO pin inputs is available. The input pins are sampled at boot and, if the BT_FUSE_SEL fuse is not blown, override the values of the corresponding eFUSEs BOOT_CFGx[7:0]. The table phyCORE-Connector Boot Configuration Pins lists the eFUSEs BOOT_CFGx[7:0] and the corresponding input pins. On the phyCORE‑i.MX 8M, the GPIOs have 10 kΩ pull-up and pull-down resistors preinstalled to configure eFUSEs BOOT_CFGx[7:0] in accordance with the module features.

The specific boot configuration settings, which are set by the onboard configuration resistors, can be changed by modifying the resistors on the module or by connecting a configuration resistor (e.g. 10 kΩ) to the configuration signal. Please consider that any change of the default BCFG configuration can also influence other boot modes, which might result in faulty boot behavior.

System Memory

The phyCORE‑i.MX 8M provides three types of onboard memory:

Additionally, an I²C-EEPROM with 4 kB is mounted to every SOM. Details for each memory type used on the phyCORE‑i.MX 8M are below.

LPDDR4-RAM (U3)

The RAM memory interface of the phyCORE‑i.MX 8M supports one 32-bit LPDDR4-RAM chip (U3). The LPDDR4 memory is accessible starting at addresses 0x4000 0000 and 1 0000 0000.

Typically, the LPDDR4-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 8M controller. Refer to the i.MX 8M Reference Manual to access and configure these registers.

eMMC Flash Memory (U4)

The main flash memory of the i.MX 8M is eMMC and is populated at U4. The eMMC device is programmable with 1.8 V. No dedicated programming voltage is required. The eMMC Flash memory is connected to the SD1 interface of the i.MX 8M.

For more information about the eMMC Flash, please refer to the i.MX 8M Reference Manual.

I²C EEPROM (U6)

The phyCORE‑i.MX 8M is populated with a non-volatile 4 kB I²C EEPROM at U6. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I²C port 1 on the i.MX 8M. The control registers for I²C port 1 are mapped between addresses 0x30A2 0000 and 0x30A3 0000. Please see the i.MX 8M Reference Manual for detailed information on the registers.

The three lower address bits are fixed to zero which means that the EEPROM can be accessed at I²C address 0x52. The EEPROM has a second address on 0x5A, which is called Identification Page, and is reserved for internal PHYTEC uses only.

QSPI NOR Flash (U40)

The QSPI NOR Flash memory of the phyCORE-i.MX 8M at U40 can be used to store configuration data or any other general-purpose data. It can also be used as a boot device and recovery boot device. The device is accessed through QSPIA SS0 on the i.MX 8. The control registers for QSPI are mapped between addresses 0x30BB 0000 and 0x30BB FFFF. Please see the i.MX 8M Reference Manual for detailed information on the registers.

As of the printing of this manual, these SPI Flash devices generally have a life expectancy of at least 100,000+ erase/program cycles and a data retention rate of 20 years. This makes the QSPI Flash a reliable and secure solution to store the first and second-level bootloaders.

Serial Interfaces

The phyCORE‑i.MX 8M provides numerous dedicated serial interfaces, some of which are equipped with a transceiver to enable direct connection to external devices:

1. 1x 4-bit SDIO interface
2. 4x high-speed UARTs
3. 2x USB 3.0/2.0 OTG interfaces
4. 1x Gbit Ethernet interface
5. 3x I²C interfaces
6. 2x Serial Peripheral Interfaces (SPI)
7. 1x SAI audio interface
8. 2x PCI Express interfaces
9. 2x MIPI CSI interfaces
10. 1x MIPI DSI interface

The details for each of these serial interfaces and any applicable jumper configurations are below.

SDIO Interface

The SDIO interface can be used to connect external SD cards, eMMC, or any other device requiring an SDIO interface (i.e WiFI, I/O expansion, etc.) The phyCORE bus features one SDIO interface. On the phyCORE‑i.MX 8M, the interface signals extend from the second Ultra Secured Digital (SD2) Host controller to the phyCORE-Connector. 

The table below shows the location of the different interface signals on the phyCORE-Connector. The MMC/SD/SDIO Host Controller is fully compatible with the SD Memory Card Specification 3.0 The interface supports SD cards with 3.3 V and 1.8 V signals.

Universal Asynchronous Interface

The phyCORE‑i.MX 8M provides four high-speed universal asynchronous interfaces. The following table shows the location of the signals on the phyCORE-Connector.

USB Interfaces

The phyCORE‑i.MX 8M provides two super-speed USB host interfaces. An external USB Standard-A (for USB host) connector is all that is needed to interface the phyCORE‑i.MX 8M USB host functionality. The applicable interface signals can be found on the phyCORE‑Connector X31. If overcurrent and power enable signals are needed for the USB host interface, the functionality can be easily implemented with GPIOs.

Both interfaces can also operate as high-speed OTG interfaces. An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for USB OTG) connector is all that is needed to enable the phyCORE-i.MX 8M USB OTG functionality:

Ethernet Interface

Connection of the phyCORE‑i.MX 8M to the world wide web or a local area network (LAN) is possible using the onboard GbE PHY at U8. It is connected to the RGMII interface of the i.MX 8M. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. Alternatively, the RGMII (ENET) interface, which is available on the phyCORE‑Connector, can be used to connect an external PHY. In this case, the onboard GbE PHY (U8) must not be populated (RGMII Interface).

Ethernet PHY (U8)

With an Ethernet PHY mounted at U8, the phyCORE‑i.MX 8M has been designed for use in 10Base-T, 100Base-T, and 1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE‑Connector X31.

The onboard GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct-connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface of the i.MX 8M. Please refer to the i.MX 8M Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (ETH0_A±, ETH0_B±, ETH0_C±, ETH0_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.

Software Reset of the Ethernet Controller

The Ethernet PHY at U8 can be reset by software. The reset input of the Ethernet PHY is permanently connected to RESET_ETHPHY (GPIO1_IO06) of the i.MX 8M.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 8M is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

RGMII Interface

In order to use an external Ethernet PHY instead of the onboard GbE PHY at U8, the RGMII interface (ENET) of the i.MX 8M needs to be brought out at phyCORE‑Connector X31.

SPI Interface

The Serial Peripheral Interface (SPI) is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI on the phyCORE‑Connector X31. The SPI provides one chip select signals for each interface. The Enhanced Configurable SPI (eCSPI) of the i.MX 8M has three separate modules (eCSPI1, eCSPI2, eCSPI3) which support data rates of up to 52 Mbit/s. The interface signals of the first and second modules (eCSPI1, eCSPI2) are made available on the phyCORE-Connector. These modules are master/slave configurable. The following table lists the SPI signals on the phyCORE-Connector.

I²C Interface

The Inter-Integrated Circuit (I²C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 8M contains four identical and independent Multimaster fast-mode I²C modules. The interface of 3 modules is available on the phyCORE-Connector. I2C1 is reserved for controlling the SOM. 

The following table lists the I²C ports on the phyCORE-Connector:

Audio Interface

 The i.MX8M supports multiple audio interfaces as listed below:

I²S Audio Interface (SAI)

The phyCORE-i.MX 8M features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-Connector X31. 

SAI1 provides 8-bit transmit and 8-bit receive functionality with receive, transmit, and master clock output. Frame synchronization is available for receive and transmit operations. The tables below show the signal locations for each SAI and SPDIF interfaces.

PCI Express Interface

The two 1-lane PCI Express interfaces of the phyCORE‑i.MX 8M provide PCIe Gen. 2.0 functionality which supports 5 Gbit/s operations. Furthermore, the interfaces are fully backward compatible with the 2.5 Gbit/s Gen. 1.1 specifications. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented with GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Polaris) for a circuit example.

The positions of the PCIe signals on the phyCORE‑Connector X31 are shown below:

General Purpose I/Os

All pins not used by any of the other interfaces specifically described in this manual and can be used as GPIO without harming other features of the phyCORE‑i.MX 8M. These pins are shown below:

Besides these pins, most of the i.MX 8M signals which are connected directly to the module connector can be configured to act as GPIOs, due to the multiplexing functionality of most controller pins. Normally, pins with signal type I/O are able to work as a GPIO.

Debug Interface

The phyCORE‑i.MX 8M is equipped with a JTAG interface to download program code into the external flash, internal controller RAM, or any debugging programs being executed. The locations of the JTAG pins on the phyCORE-Connector X31 are below:

UART Debug

The default debug UART Interface (TTL) is UART1. It is accessible on connector X31 pins C39(RXD) and C40(TXD).

Display Interfaces

High Definition Multimedia Interface (HDMI)

The High Definition Multimedia Interface (HDMI) of the phyCORE-i.MX 8M is compliant with HDMI 2.0a as well as DP 1.3 and eDP 1.4. It supports a maximum pixel clock of up to 596 MHz for up to 2160p at 60 Hz UHDTV display resolutions and a graphic display resolution works up to 4096x2160 (QFHD). Please refer to the i.MX 8M Reference Manual for more information.

The location of the HDMI signals on the phyCORE-Connector are shown below:

The default HDMI setup comes from the SOM. The signals extend directly from the i.MX 8M’s dual-purpose PHY for HDMI and eDP. A standard HDMI connector can be used. A 5 V level shifter for the DDC and HPD signals is not needed, but the DDC Lanes require pullups (1.5k to 2k) to 5V and pulldown for the HPD Signal is recommended. The CEC Lane requires a 27k pullup to 3.3V. Diodes can be used at all pullups to prevent backsourcing. An optional ESD circuit protection can be used.

Camera Connections

The phyCORE-i.MX 8M offers 2 MIPI-CSI interfaces to connect digital cameras with a resolution of up to 4k at 30fps. The two MIPI/CSI‑2 camera interfaces of the i.MX 8M extend to the phyCORE‑Connector X31 with 4 data lanes and one clock lane.

The locations of the MIPI-CSI signals are shown below:

The phyCORE-i.MX 8M offers one MIPI-DSI display interface. MIPI-DSI has 4 channels, supporting one display with a resolution of up to 1920 x 1080 at 60Hz.

The locations of the MIPI-DSI signals are shown below:

WIFI/Bluetooth

WIFI

The i.MX8M is the first SOM in the PHYTEC phyCORE family with onboard Wifi/Bluetooth support. This feature is made possible with a Sterling-LWB module soldered onto the SOM. This module supports Wifi according to IEEE 802.11 b/g/n and Bluetooth v4.2 BR /DR/LE.

Wifi is controlled over the SD2 interface. It is also possible to use this interface on the carrier board. To achieve this, an SDIO switch has been added to the SOM.  This changes the signal depending on whether the signal is connected to WIFI or BGA Ball. There are two signals which are controlled by the SDIO switch.

1.  X_GPIO1_IO03/WIFI_SELECT is connected to the Enable Pin of the SDIO Switch. This is a low active signal and, as the name indicates, is controlled by GPIO1_03 (from the processor). This signal is also connected to the BGA ball connector and can be controlled from the carrier board. This signal is connected to a pull-up. By default, the switch is disabled.

2. X_WIFI_SELECT. This signal is only connected to the carrier board and determines if the SD2 interface is connected to WIFI or to the BGA balls. By default, SD2 is connected to WIFI. If you want to connect SD2 to the BGA balls, it is necessary to pull X_WIFI_SELECT to GND.

   X_WIFI_SELECT	Connection
   High	SD2 → WIFI
   Low	SD2 → Connector X31

   Display Interface MIPI / DSI Signal Locations

Bluetooth

Bluetooth is controlled over UART2. The handshake signals that are needed, RTS and CTS, come out on the UART4 TX and RX pins (if you order a SOM without mounted a WIFI Module) These pins are connected via jumpers to the phyCORE-Connector X31.

There are a few other control signals on the WIFI Module. They can be controlled using various jumper settings. By default, all signals are controlled by GPIOs from the i.MX 8M processor. It is also possible to connect each signal to the BGA connector, allowing them to be controlled with the carrier board.

The following tables show the possible jumpers settings:

RTC

The i.MX 8M has an onboard, externally mounted RTC. The RV-3028 is the newest generation of RTC from Micro Crystal with an extremely low backup current of typically 40nA at 25 degrees. PHYTEC uses the most optimal implementation in each phyCORE design to give the most optimal usage for all customers.

The RTC is accessible over I2C1 on Address 0x52. In a normal operation state, the RTC power is supplied from the SOM voltage. If the SOM is not powered and RTC backup is needed, the VBACKUP Pin of the RTC can be supplied over the VRTC BGA ball.  The clockout of the RTC is used for the WIFI Module and must be set to 32.768kHz.

Additional features like event input  X_RTC_EVI (X31E35) are also accessible as an RTC interrupt option. This option is, by default, connected to GPIO1_IO05 of the i.MX 8M processor but can be changed to a BGA ball connection by changing the settings on jumper J34. The settings are shown below:

CPU Core Frequency Scaling

The phyCORE-i.MX 8M on the phyBOARD‑Polaris is able to scale the clock frequency and voltage. This is used to save power when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as 'Dynamic Voltage and Frequency Scaling' (DVFS).

The phyCORE-i.MX 8M BSP supports the DVFS feature. The Linux kernel provides a DVFS framework that allows each CPU core to have a min/max frequency as well as the applicable voltage and a governor that governs these values depending on the system load. Depending on the i.MX 8M variant used, several different frequencies are supported. Further details on how to configure this governor can be found in the phyCORE-i.MX 8M BSP Manual.

Technical Specifications

Warning

Due to changes in functionality and design that are currently being developed, there are several values that cannot be determined in time for the release of this manual. All values with "TBD (To Be Determined)" are currently being evaluated. These values will be added to future manual editions.

The module’s profile is max. 4.8 mm thick, with a maximum component height of 1.0 mm on the bottom (connector) side of the PCB and approximately 2.18 mm on the top (microcontroller) side. The board itself is approximately 1.6 mm thick. The phyCORE-i.MX 8M Footprint can be seen below.

phyCORE-i.MX 8M Footprint

Additional specifications:

These specifications describe the standard configuration of the phyCORE‑i.MX 8M as of the printing of this manual.

phyCORE-i.MX 8M Power Consumption

The values listed in the table below are a guideline to determine the required dimensions of the power supply circuitry on a carrier board. They do not take application-specific load situations into account. These values have been generated by looking at the maximum power consumption measured using different load scenarios and adding a voltage source of 3.3 V ±5 %. These values are based on internal PHYTEC testing. Customers need to consider their application power requirements to ensure they do not generate a load greater than the values listed here. 

For the Power Measurement, a SOM with 2 GB RAM, 16GB eMMC, WIFI, ETH, and a MIMX8MQ6DVAJZAB was used together with PD19.1.0.

Additionally, there are some values that cannot be tested. Situations such as suspending to RAM, suspend freeze, and standby mode must be tested on a case-by-case basis to ensure the application's power consumption stays within the guideline stated above.

Product Temperature Grades

The feasible operating temperature of the SOM highly depends on the use case of your software application. Modern high-performance microcontrollers and other active parts such as the ones described within this manual are usually rated by qualifications based on tolerable junction or case temperatures. Therefore, making a general statement about minimum or maximum ambient temperature ratings for the described SOM is not possible.

However, the above-mentioned parts are available at different temperature qualification levels by the producers. We offer our SOMs in different configurations, making use of those temperature qualifications. To indicate which level of temperature qualification is used for active and passive parts of a SOM configuration, we have categorized our SOMs into three temperature grades.

Table Product Temperature Grades describes these grades in detail. This table describes a set of components that, in combination, add up to a useful set of product options with different temperature grades. This enables us to make use of cost optimizations depending on the required temperature range.

In order to determine the right temperature grade and whether the minimum or maximum qualification levels are met within an application, the following conditions must be defined by considering the use case:

• Determined the processing load for the given software use case
• Maximum temperature ranges of components (Product Temperature Grades)
• Power consumption resulting from a baseload and the calculating power required (in consideration of peak loads as well as time periods for system cooldown)
• Surrounding temperatures and existing airflow in case the system is mounted into a housing
• Heat resistance of the heat dissipation paths within the system along with the considered usage of a heat spreader or a heat sink to optimize heat dissipation

phyCORE-i.MX 8M BGA Mounting

The phyCORE i.MX 8M uses of Ball Grid Array (BGA) to mount to a carrier board (for example, phyBOARD-Polaris). BGA provides several advantages:

• An easy-to-produce design
• Permanent and robust mechanical connection to the carrier application
• Relaxed fit in regards to onboard circuitry
• Easy to design in any application
• Low profile
• Cost-efficient

For more information about BGA soldering, please refer to the PHYTEC BGA Soldering Guide (LAN-093e.A0 i.MX 8 BGA Soldering Information).

Hints for Integrating and Handling the phyCORE‑i.MX 8M

Integrating the phyCORE-i.MX 8M

Besides this hardware manual, more information is available to facilitate the integration of the phyCORE‑i.MX 8M into customer applications.

1. The design of the phyBOARD‑Polaris can be used as a reference for any customer application.
2. Many answers to common questions can be found at: https://www.phytec.de/produkt/system-on-modules/phycore-imx-8m-download/ or https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-download/
3. The link “Carrier Board” within the category Dimensional Drawing leads to the layout data phyCORE-i.MX 8M Footprint. It is available in different file formats. The use of this data allows the user to integrate the phyCORE-i.MX 8M SOM as a single component in their design.
4. Different support packages are available for support in all stages of embedded development. Please visithttp://www.phytec.de/de/support/support-pakete.html or https://www.phytec.eu/support/support-packages/ or contact our sales team for more details.
5. Many answers to common questions can be found at:

6. http://www.phytec.de/support/knowledge-database/soms-system-on-modules/phycore/phycore-imx-8m/
     or
   https://www.phytec.eu/product-eu/system-on-modules/phycore-imx-8m-download/

Handling the phyCORE-i.MX 8M

phyCORE Module Modifications

The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station, or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Integrating the phyCORE into a Target Application

Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. At a minimum, all GND pin neighboring signals which are being used in the application circuitry should be connected to GND.

phyCORE-i.MX 8M on the phyBOARD-Polaris

Hardware Overview

The phyBOARD‑Polaris for phyCORE-i.MX 8M is a low-cost, feature-rich software development platform supporting the NXP Semiconductors i.MX 8M microcontroller. Due to numerous standard interfaces, the phyBOARD‑Polaris i.MX 8M can serve as the bedrock for any application. At the core of the phyBOARD‑Polaris is the PCL-066/phyCORE-i.MX 8M System On Module (SOM) containing the processor, LPDDR4 RAM, eMMC Flash, power regulation, supervision, transceivers, WiFi/Bluetooth, and other core functions required to support the i.MX 8M processor. Surrounding the SOM is the PB-2419/phyBOARD‑Polaris carrier board, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals.

The PCL-066 System On Module connects to the phyBOARD‑Polaris carrier board using a Ball Grid Array (BGA). The PCL-066 SOM is directly soldered onto the phyBOARD‑Polaris using PHYTEC's Direct Solder Connect technology. This solution offers an ultra-low-cost Single Board Computer for the i.MX 8M processor, while maintaining most of the advantages of the SOM concept.

phyBOARD-Polaris Concept

PHYTEC phyCORE carrier boards are fully equipped with all mechanical and electrical components necessary for a fast, secure start-up. Subsequent communication to and programming of applicable PHYTEC System on Modules (SOM) is made easy. phyCORE carrier boards are designed for evaluation, testing, and prototyping of PHYTEC System on Modules in laboratory environments prior to their use in customer-designed applications.

This modular development platform concept includes the following components:

• The phyCORE-i.MX 8M Module populated with the i.MX 8M microcontroller and all applicable SOM circuitry such as LPDDR4 SDRAM, eMMC-Flash, Ethernet-PHY, PMIC, etc.
• The phyBOARD-Polaris Carrier Board offers all essential components and connectors for a start-up including a power supply for 24 V input voltage, and interface connectors such as HDMI, USB, and Ethernet, which enable the use of the SOM’s interfaces with a standard cable.

The carrier board can also serve as a reference design for developing custom target hardware in which the phyCORE SOM can be deployed. Carrier board schematics are available under a Non-Disclosure Agreement (NDA). Reuse of carrier board circuitry enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

SBCplus Concept

The SBCplus concept was developed to meet the many, small differences in customer requirements with little development effort. This greatly reduces the time-to-market. The core of the SBCplus concept is the SBC design library (a kind of construction set) that consists of a large number of function blocks (so-called "building blocks") that are continuously being refined and updated.

Recombining these function blocks allows PHYTEC to develop a customer-specific SBC within a short time. We are able to deliver production-ready custom Single Board Computers within a few weeks at very low costs. The already developed SBCs, such as the phyBOARD-Polaris, each represent a combination of different customer wishes. This means all necessary interfaces are already available on the standard versions, allowing PHYTEC SBCs to be integrated into a large number of applications without modification.

For any necessary detail adjustment, extension connectors are available which enable a wide variety of functions to be added.

phyBOARD-Polaris Features

The phyBOARD‑Polaris supports the following features :

• Developed in accordance with PHYTEC's SBCplus concept (SBCplus Concept)
• Populated with PHYTEC’s phyCORE-i.MX 8M SOM (via BGA mounting)
• Dimensions of 100 mm × 100 mm
• Boot from eMMC, SD Card, or over USB with the Serial Downloader
  
• Max. 1.3 GHz core clock frequency and up to four cores (at I-Temp Kit Version)
• 24 V power supply
• 2GB RAM (at Kit Version)
• 8GB eMMC (at Kit Version)
• 32MB NOR (at Kit Version)
• 4kB EEPROM
• 1x RJ45 jack for 10/100/1000 Mbps Ethernet

• 1x USB 3.0 host interface connected to a USB 3.0 4-port HUB. The 3.0 interface is brought out to an upright USB Standard-A connector. The other 3 ports are connected to the Mini PCI express connector, the Audio/Video connector, and the expansion connector^[3]
  

• 1x USB OTG interface available at a USB Micro-AB connector
• 1x Secure Digital / MultiMedia Memory Card interface brought out to a Micro-SD connector
• 1x HDMI interface brought out to a standard Type-A connector
• 1x MIPI-DSI brought out via an A/V Connector
• 2x MIPI-CSI-2 camera interfaces
• 1x PCI interface brought out to a Mini PCI Express connector
• RS-232 or RS-485 transceiver supporting UART3 including handshake signals with data rates of up to 1 Mbps (2×5 pin header 2.54 mm)
• Reset button
• ON/OFF button
• 1x multicolor LED
• SAI Audio brought out via an A/V connector
• Digital I/O via an Expansion Connector
• JTAG via an Evaluation Adapter connected to the Expansion Connector (X8)
• Expansion connector for different interfaces
  • I²C
  • SPI
  • UART
  • QSPI
  • USB
  • SPDIF
• RTC
  • Goldcap Backup supply for RTC

Block Diagram

phyBOARD-Polaris Block Diagram

phyBOARD-Polaris Components

phyBOARD-Polaris Component Placement Diagram

phyBOARD-Polaris Components (Top)

phyBOARD-Polaris Components (Bottom)

phyBOARD-Polaris Component Overview

The phyBOARD-Polaris features many different interfaces and is equipped with the components listed in table phyBOARD-Polaris Connectors and Pin Header. For a more detailed description of each component, refer to the appropriate section listed in the table below. phyBOARD-Polaris Components (Top) and phyBOARD-Polaris Components (Bottom) highlight the location of each component for easy identification.

Connectors and Pin Headers

The table below lists all available connectors on the phyBOARD‑Polaris.

LEDs

The phyBOARD-Polaris is populated with 2 LEDs. One to indicate the status of the USB VBUS voltages and the power supply voltage. The other is user-programable. phyBOARD-Polaris Components (Top) and phyBOARD-Polaris Components (Bottom) show the location of the LEDs. Their functions are listed in the table below:

Switches

The phyBOARD-Polaris is populated with two switches. The table below shows their functions:

Additionally, S1 is a 4-port dip switch bar populated for several functions:

• Boot Selection (see Boot Switch)
• SD Card or WIFI Selection
• UART3 Destination (FTDI or Expansion Connector) (see USB Debug)

Jumpers

The phyBOARD-Polaris comes pre-configured with several solder jumpers (J). The jumpers enable the flexible configuration of a limited number of features for development purposes.

phyBOARD-Polaris SBC Component Detail

This section provides a more detailed look at the phyBOARD‑Polaris components. Each subsection details a particular connector/interface and associated jumpers for configuring that interface.

phyCORE Connection (X31)

Power Supply (X33)

The phyBOARD‑Polaris is available with one power supply connector, a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector (X33) suitable for a single 24 V supply voltage. The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE mounted on the phyBOARD-Polaris, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board.

The permissible input voltage is +24 V DC if your SBC is equipped with a 2-pole Phoenix Contact MINI COMBICON base strip. A 24 V adapter with a minimum supply of 1.0 A is recommended to supply the board via the 2-pole base strip. The pin assignment for power supply connector X33:

RTC Backup Supply

The phyBOARD-Polaris has a Supercapacitor equipped (C450 or C352) to supply the VRTC rail of the phyCORE-i.MX 8M. Using the C450 (CG020) with 470mF plus D32 and unsoldering R616, a calculation and a measurement of the RTC hold time was performed. The RTC can hold the time as long as the supply voltage is above 1.1 V. The following graphic shows the measurement at about 25 degrees.

However, this can not be guaranteed. The theoretical value is far below the measurement. The following table shows the calculation:

So the theoretical value is 114,8 hours at 25 deg. The DCL can increase to 650 % of the 25 deg value at 85 deg.

UART (X8 and X9)

The phyCORE-i.MX 8M supports up to 4 UART units. On the phyBOARD-Polaris, TTL level signals of UART1 and UART3 (the standard console) are routed to expansion connector X8 (see Expansion Connector (X8) for more information). UART4 is available at pin header connector X9 at RS-232 level, or optionally at RS-485 level. UART2 is at X18 (Audio/Video Connectors).

Pin header connector X9 is located next to the Ethernet connector and provides the UART4 signals of the i.MX 8M at either the RS-232 or RS-485 level. The serial interface is intended to be used with data terminal equipment (DTE) and allows for a 5-wire connection including the signals RTS and CTS for hardware flow control. The table below shows the signal mapping of the RS-232 and RS-485 level signals at connector X9:

UART Debug Interface

The main debug interface is UART1. The UART is connected to a UART-to-USB Converter (U66) via a Multiplexer (U61). When a USB cable is plugged in at X30, the interface will be available at the connector. Otherwise, it is routed to the Expansion Connector (X8)

UART Design Consideration

When designing a custom carrier board, remember the TTL level is 3.3 V.

Ethernet (X1)

The phyBOARD‑Polaris is equipped with an RJ45 connector supporting a 10/100/1000Base-T network connection. The LEDs for LINK (green) and SPEED (yellow) indications are integrated into the connector. The Ethernet transceiver supports Auto MDI-X, eliminating the need for a direct connect LAN or cross-over path cable. They detect the TX and RX pins of the connected device and automatically configure the PHY TX and RX pins accordingly.

Ethernet Design Consideration

The data lanes should be routed with a differential impedance of 100 Ohm. The center taps of each pair's transformer have to be connected to GND through a 100nF capacitor. The LED pins are open-drain outputs of the SOM without a resistor, so they should be connected to the cathodes of the LEDs through a resistor.

USB

USB Interfaces (X2 and X13)

The phyBOARD-Polaris provides one USB host and one USB OTG interface. USB1 is accessible at connector X2 (USB Micro-AB) and is configured as USB OTG. USB OTG devices are capable of initiating a session, controlling the connection, and exchanging host and peripheral roles with each other. This interface is compliant with USB revision 2.0. USB2 is accessible at connector X13(USB3.0 Standard-A) and is configured as a USB host.

USB Debug (X30)

The phyBOARD-Polaris is equipped with a USB Debug interface for downloading program code into the external flash, internal controller RAM, or for debugging programs currently executing.

The table below shows the pinout of the USB Debug connector:

USB Design Consideration

The data lanes should be routed with a differential impedance of 90 Ohm.

Secure Digital Memory Card / MultiMedia Card (X4)

The phyBOARD‑Polaris provides a standard microSDHC card slot at X4 for use with SD/MMC interface cards. It allows for a fast, easy connection to peripheral devices like SD and MMC cards. Power to the SD interface is supplied by inserting the appropriate card into the SD/MMC connector. It also features card detection, a lock mechanism, and a smooth extraction function by pushing the card in and out.

DIP switch S1 provides a toggle between eMMC and SD card boot. In order to boot from the SD card, S1 must be switched ON (refer to Boot Switch for further information).

SD / MM Card Design Considerations

Series resistors are placed on the PCL-066 to adapt the i.MX 8's drive strength. Series resistors might be required to adapt the drive strength of the card. The trace length between CLK, CMD, and DATA lanes should be matched. The voltage of the SD2 signal lanes is NVCC_SD2 and can switch between 1.8 V and 3.3 V. The supply voltage of the SD card remains 3.3 V and should not be connected to NCVV_SD2. Even when the signal level is fixed to 3.3V, NVCC_SD2 can not provide enough power to supply an SD card as it is only a reference voltage.

PCIe (X6)

The 1-lane PCI express interface provides PCIe Gen. 2.0 functionality, which supports 5 Gbit/s operations. The interface is fully backward compatible with the 2.5 Gbit/s Gen. 1.1 specification. Various control signals are implemented with GPIOs. The PCIe interface is brought out at the Mini PCIe connector X6 shown above.

The table below shows in-depth information such as pin assignment and signals used to implement special features of the Mini PCIe interface.

PCIe Design Considerations

100nF AC-Coupling capacitors are placed at the output of the phyCORE-i.MX 8M in series to the TX-Lanes. No further TX coupling capacitors are needed. The differential impedance should be 85 Ohm for TX and RX lanes and 100 Ohm for the clock lane.

Camera Connectivity (X10 and X11)

The phyCORE-imMX 8M on the phyBOARD-Polaris offers 2 independent interfaces to connect digital camera boards with the MIPI CSI-2 interface. The 4-lane MIPI CSI-2 interfaces are brought out as phyCAM-M camera interfaces at connectors X10 and X11. The pin assignments of connectors X10 and X11 are given below.

Camera Design Considerations

Regarding camera connections when designing a customer carrier board:

1. phyCAM-M interfaces offer 3.3V or 5.0V supply voltages (selected by interface pin 26). Both voltages must be provided by the board.
2. Each phyCAM interface has a different I2C address. R570 for the CSI-1 address is not mounted; R569 for the CSI-2 address is mounted.
3. The strobe signal (CTRL1) of the CSI2 interface can be connected to the trigger signal (CTRL2) of the CSI1 interface. R542 has to be mounted for this to be possible.

General information and design guidelines for PHYTEC camera interfaces can be found here: https://www.phytec.de/fileadmin/user_upload/downloads/Manuals/L-748e_10.pdf → phyCAM Concept and Design-In
Specific information for each PHYTEC camera module can be found on that module's download page: https://www.phytec.de/produkte/embedded-imaging/phycam/

HDMI (X32)

The phyBOARD‑Polaris provides a High-Definition Multimedia Interface (HDMI) which is compliant with HDMI 2.0a and HDCP 1.4/2.2. It supports one display at a maximum pixel clock of up to 596 MHz and a maximum resolution of 4096x2160 at 60Hz. Other resolutions are 3840x2160p60, 1920x1080p60, 1280x720p60, 720x480p60, 640x480p60. Please refer to the i.MX 8M Applications Processor ReferenceManual for more information.

The HDMI interface is brought out at a standard HDMI type A connector (X32) on the phyBOARD‑Polaris and is comprised of the following signal groups:

• 3x pairs of data signals
• 1x pair of clock signals
• The Display Data Channel (DDC)
  
• The Consumer Electronics Control (CEC)
• The Hot Plug Detect (HPD) signal
• Audio Return Channel (ARC)

All signals are routed from the phyCORE‑Connector to the HDMI receptacle through ESD Protection Diodes.

HDMI Design Considerations

The DDC lanes need pull-up resistors between 1.5k and 2k to 5V. The CEC lane needs a 27k pull-up resistor connected to 3.3V through a diode. This prevents leaking current in a power-off state. HPD should be pulled low with a 1M resistor.

Audio Interface (X14 and X15)

The audio interface provides a method of exploring and using i.MX 8M's audio capabilities. The phyBOARD-Polaris is populated with an audio codec at U60. The audio codec is connected to the i.MX 8M's SAI interface to support stereo line input and output at connector X15. A direct mono speaker output (1 W) is available at Molex connector X14. The audio codec can be configured via I²C at address 0x18.

Additional signals are routed to the A/V connector X18. Refer to section Audio/Video Connectors (X16 and X18)for more information. For additional information regarding special interface specifications, refer to the audio codec reference manual.