Copyrighted products are not explicitly indicated in this manual. The absence of the trademark (™ or ®) and copyright (©) symbols does not imply that a product is not protected. Additionally, registered patents and trademarks are similarly not expressly indicated in this manual.

The information in this document has been carefully checked and is considered to be entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts any liability whatsoever for consequential damages resulting from the use of this manual or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the information contained herein without prior notification and accepts no responsibility for any damages that might result.

Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout and/or design of the hardware without prior notification and accepts no liability for doing so.

@ Copyright 2021 PHYTEC Messtechnik GmbH, D-55129 Mainz.

Rights - including those of translation, reprint, broadcast, photomechanical or similar reproduction and storage or processing in computer systems, in whole or in part - are reserved. No reproduction may occur without the express written consent from PHYTEC Messtechnik GmbH.

Information on this Manual

This hardware manual describes the PCL-070 System on Module, referred to as phyCORE®-i.MX 8M Plus, and the PBA-C-17, referred to as phyBOARD®-Pollux. This manual also specifies the phyCORE-i.MX 8M Plus and phyBOARD-Pollux' design and function. Precise specifications for the NXP® Semiconductor i.MX 8M Plus microcontrollers can be found in the i.MX 8M Plus Microcontroller Data Sheet/Reference Manual.

Both of these products are in the alpha stage. Due to this, there will be several changes and additions to this manual. New versions will be released in the future with no notice. Please make sure that you are using the latest version of this manual when working with your product.

Design Considerations

The schematics shown in this hardware manual are believed to be correct. However, correctness can not be guaranteed. The schematics have been pulled from PHYTEC's designs that have been built, tested, and is known to work. The schematics have been re-formatted to fit better in this hardware manual.

Many hardware examples and suggestions are given in the following pages. Designing the phyCORE System on Module on to a Carrier Board is generally straightforward. However, before committing to a particular active component selection when designing a carrier board, it is wise to check out the software driver support for those components. A particular device may be supported in, say, for example, Linux but not in Windows Embedded Compact 7. Your overall project may go smoother if you pick components that are already supported in your target OS. The made selections for our reference designs, for example our Single Board Computers, are typicaly focused on using components that are well supported under Linux.

Specific details may need to be considered when designing a customer-specific carrier board. For design information on carrier board components, please check the Design Considerations in each component section of phyCORE-i.MX 8M Plus on the phyBOARD-Pollux. Be aware that not all components need to be considered when designing your own carrier board.

Preface

As a member of PHYTEC's phyCORE® product family, the phyCORE‑i.MX 8M Plus is one of a series of PHYTEC System on Modules (SOMs) that can be populated with different controllers, various types of memory (RAM, NAND flash, eMMC), and many other features. This, in turn, offers increased types of functions and configurations. PHYTEC supports a variety of 8/16/32/64-bit controllers in two ways:

1. As the basis for Rapid Development Kits which serve as a reference and evaluation platform
2. As insert-ready, fully functional phyCORE® OEM modules, which can be embedded directly into the user’s peripheral hardware design.

Implementation of an OEM-able SOM subassembly as the "core" of your embedded design allows for increased focus on hardware peripherals and firmware without expending resources to "reinvent" microcontroller circuitry. Furthermore, much of the value of the phyCORE® module lies in its layout and test.

Production-ready Board Support Packages (BSPs) and Design Services for our hardware will further reduce development time and risk and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks. With this new innovative, full-system solution, new ideas can be brought to market in the most timely and cost-efficient manner.

For more information go to:

http://www.phytec.de/leistungen/entwicklungsunterstuetzung.html
or
http://www.phytec.eu/europe/oem-integration/evaluation-start-up.html

Ordering Information

The part numbering of the phyCORE PCM-070 has the following structure:

Product Specific Information and Technical Support

In order to receive product-specific information on all future changes and updates, we recommend registering at:
http://www.phytec.de/support/registrierung.html or http://www.phytec.eu/europe/support/registration.html

For technical support and additional information concerning your product, please visit the support section of our website which provides product-specific information, such as errata sheets, application notes, FAQs, etc.
https://www.phytec.de/produkte/system-on-modules/phycore-imx-8m-plus/
or
https://www.phytec.com/product/phycore-i-mx-8m-plus/

Declaration of Electro Magnetic Conformity of the PHYTEC phyCORE®‑i.MX 8M Plus

PHYTEC System on Modules are designed for installation in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype platform for hardware/software development) in laboratory environments.

PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity in accordance with the descriptions and rules of usage indicated in this hardware manual (particularly in respect to the pin header row connectors, power connector, and serial interface to a host-PC).

Product Change Management and Information Regarding Parts Populated on the SOM / SBC

With the purchase of a PHYTEC SOM / SBC, you will, in addition to our hardware and software possibilities, receive free obsolescence maintenance service for the hardware we provide. Our PCM (Product Change Management) team of developers is continuously processing all incoming PCN's (Product Change Notifications) from vendors and distributors concerning parts that are used in our products. Possible impacts on the functionality of our products due to changes in functionality or obsolesce of certain parts are constantly being evaluated in order to take the right measures either in purchasing decisions or within our hardware/software design.

Our general philosophy here is: We will never discontinue a product as long as there is a demand for it.

To fulfill this, we have established a set of methods to fulfill our philosophy:

Avoidance strategies:

• Avoid changes by evaluating the longevity of parts during the design-in phase.
• Ensure the availability of equivalent second source parts.
• Stay in close contact with part vendors to keep up with roadmap strategies.

Change management in the rare event of an obsolete and non-replaceable part:

• Ensure long term availability by stocking parts through last time buy management according to product forecasts.
• Offer long term frame contracts to customers.

Change management in cases of functional changes:

• Avoid impacts on product functionality by choosing equivalent replacement parts.
• Avoid impacts on product functionality by compensating changes through hardware redesign or backward-compatible software maintenance.
• Provide early change notifications concerning functional, relevant changes to our products.

We refrain from providing detailed part specific information within this manual, which can be subject to continuous changes, due to part maintenance for our products.
In order to receive reliable, up-to-date, and detailed information concerning parts used for our product, please contact our support team through the contact information given within this manual.

PHYTEC Documentation

PHYTEC will provide a variety of hardware and software documentation for all of our products. This includes any or all of the following:

• QS Guide: A short guide on how to set up and boot a phyCORE board along with brief information on building a BSP, the device tree, and accessing peripherals.
• Hardware Manual:  A detailed description of the System on Module and accompanying carrier board. 
• Yocto Guide:  A comprehensive guide for the Yocto version the phyCORE uses. This guide contains an overview of Yocto; introducing, installing, and customizing the PHYTEC BSP; how to work with programs like Poky and Bitbake; and much more.
• BSP Manual:  A manual specific to the BSP version of the phyCORE. Information such as how to build the BSP, booting, updating software, device tree, and accessing peripherals can be found here.
• Development Environment Guide:  This guide shows how to work with the Virtual Machine (VM) Host PHYTEC has developed and prepared to run various Development Environments. There are detailed step-by-step instructions for Eclipse and Qt Creator, which are included in the VM. There are instructions for running demo projects for these programs on a phyCORE product as well. Information on how to build a Linux host PC yourself is also a part of this guide.
• Pin Muxing Table:  phyCORE SOMs have an accompanying pin table (in Excel format). This table will show the complete default signal path, from processor to carrier board. The default device tree muxing option will also be included. This gives a developer all the information needed in one location to make muxing changes and design options when developing a specialized carrier board or adapting a PHYTEC phyCORE SOM to an application. 

On top of these standard manuals and guides, PHYTEC will also provide Product Change Notifications, Application Notes, and Technical Notes. These will be done on a case by case basis. Most of the documentation can be found in the applicable download page of our products.

These manuals and more can be found in the download section of the phyCORE-i.Mx 8M Plus Product page.

Conversions, Abbreviations, and Acronyms

Conventions

The conventions used in this manual are as follows:

• Signals that are preceded by an "n", "/", or “#”character (e.g.: nRD, /RD, or #RD), or that have a dash on top of the signal name (e.g.: RD) are designated as active low signals. That is, their active state is when they are driven low or are driving low.
• A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
• The hex-numbers given for addresses of I2C devices always represent the 7 MSB of the address byte. The correct value of the LSB, which depends on the desired command (read (1), or write (0)), must be added to get the complete address byte. For example, if the given address in this manual is 0x41 =>, the complete address byte = 0x83 to read from the device and 0x82 to write to the device
• Tables that describe all settings show the default position in bold, blue text.

Types of Signals

Different types of signals are brought out at the phyCORE-Connector. The following table lists the abbreviations used to specify the type of a signal.

Signal Types

Abbreviations and Acronyms

Many acronyms and abbreviations are used throughout this manual. Use the following table to navigate unfamiliar terms used in this document.

Abbreviations and Acronyms Used in this Manual

phyCORE-i.MX 8M Plus Introduction

The phyCORE‑i.MX 8M Plus belongs to PHYTEC’s phyCORE System on Module family. The phyCORE SOMs represent the continuous development of PHYTEC System on Module technology. Like its mini-, micro-, and nanoMODUL predecessors, phyCORE boards integrate all core elements of a microcontroller system on a subminiature board and are designed in a manner that ensures their easy expansion and embedding in peripheral hardware developments.

Independent research indicates approximately 70 % of all EMI (Electro-Magnetic Interference) problems are caused by insufficient supply voltage grounding of electronic components in high-frequency environments. The phyCORE board design features an increased pin package, which allows for the dedication of approximately 20 % of all connector pins on the phyCORE boards to Ground. This improves EMI and EMC characteristics and makes it easier to design complex applications meeting EMI and EMC guidelines using phyCORE boards, even in high noise environments.

phyCORE boards achieve their small size through modern SMT and multi-layer design. Due to the complexity of our modules, 0201-packaged SMT components and laser-drilled microvias are used on the boards, providing phyCORE users with access to this cutting edge miniaturization technology for integration into their own design.

The phyCORE‑i.MX 8M Plus is a subminiature (40 mm x 37 mm) insert-ready System on Module populated with the NXP® Semiconductor i.MX 8M Plus microcontroller. Its universal design enables it to be inserted into a wide range of embedded applications. All controller signals and ports extend from the controller to high-density pitch, or surface mount technology (SMT) connectors (all pitch 0.5 mm) aligning two sides of the board, allowing it to be plugged or soldered into any target application like a "big chip".

The descriptions in this manual are based on the NXP® Semiconductor i.MX 8M Plus. Descriptions of compatible microcontroller derivative functions are not included, as such functions are not relevant for the basic functioning of the phyCORE‑i.MX 8M Plus.

phyCORE-i.MX 8M Plus Features

The phyCORE‑i.MX 8M Plus offers the following features:

• Insert-ready, sub-miniature (40 mm x 37 mm) System on Module (SOM) subassembly in low EMI design, achieved through advanced SMD technology
• Mounted using Samtec Connectors
• Populated with the NXP® Semiconductor i.MX 8M Plus microcontroller (BGA548 packaging)
• Up to 4 ARM-A53 cores (clock frequency up to 1.8 GHz)
• Machine Learning Neuronal Processing Unit (NPU) with 2.3 TOPS
• One Cortex M7 core (800 MHz)
• Tensilica Hifi4 Audio DSP (800 MHz)
• 3D GPU GC7000UL and 2D GPU GC520L
• Boot from different memory devices (eMMC Flash standard)
• Single supply voltage of +3.3 V with onboard power management
• All controller-required supplies are generated onboard
• Improved interference safety achieved through multi-layer PCB technology and dedicated ground pins

• up to 8 GB^[1] LPDDR4 RAM

• up to 64 GB^[1] onboard eMMC in the commercial temperature range (up to 32 GB for I-Temp)
• up to 64 MB^[1]Quad SPI Nor Flash
• 4kB^[1]I²C EEPROM
• Two USB 3.0/2.0 Dual-Role interfaces with PHY
  

• Two 1Gbit Ethernet interfaces with TSN support (either one of them with Ethernet transceiver on the phyCORE-i.MX 8 M Plus enabling a direct connection to an existing Ethernet network; the second as RGMII Signals at logic-level at the signal pins instead)

• Three I²C interfaces
  
• Two SPI interfaces
• PCIe interface
• Four UART interfaces
• Two CAN-FD interfaces
• Four PWM outputs
• MIPI DSI-2 interface
• HDMI interface
• Two MIPI CSI-2 camera interfaces
• LVDS Tx interface 2 channels x4
• One 4-bit SD-Card interface
• One 8-bit SDIO interface
  
• Two SAI audio interfaces
• One SPDIF interface
• Extreme Low Power RTC Module
• Four temperature sensors to monitor the board's temperature profile
• Available for different temperature grades (see Product Temperature Grades)

phyCORE-i.MX 8M Plus Block Diagram

phyCORE-i.MX 8M Plus Block Diagram

phyCORE-i.MX 8M Plus Component Placement

phyCORE-i.MX 8M Plus Component Placement (Top View)

phyCORE-i.MX 8M Plus Component Placement (Bottom View)

phyCORE-i.MX 8M Plus Minimum Operating Requirements

Pin Description

All controller signals extend to surface mount technology (SMT) connectors (0.5 mm). These connectors line two sides of the module (referred to as phyCORE-Connectors). This enables phyCORE-i.MX 8 Plus to be plugged into any target application like a "big chip".

PHYTEC provides a complete pinout table for the phyCORE-i.MX 8M Plus Connector (X1). This table contains a complete signal path for the phyCORE‑i.MX 8M Plus and the carrier board phyBOARD-Pollux, including signal names, pin muxing paths, and descriptions specific to each pin. It also provides the appropriate voltage domain, signal type (ST), and a functional grouping of the signals. The signal type also includes information about the signal direction. A table describing the signal types can be found with the phyCORE-i.MX 8M Plus Pinout Table.

Jumpers

The phyCORE-i.MX 8M Plus is a jumperless SOM. There are, however, a few jumpers on the phyCORE-Pollux. Information on these jumpers can be found in Jumpers.

Power

The phyCORE‑i.MX 8M Plus operates off of a single power supply voltage. The following section discusses the primary power pins on the phyCORE i.MX 8M Plus Connector X1 in detail.

Primary System Power (VIN_3V3)

The phyCORE‑i.MX 8M Plus is powered by a primary voltage supply with a nominal value of +3.3 V. Onboard switching regulators generate the voltage supplies required by the i.MX 8M Plus MCU and onboard components from the primary 3.3 V supplied to the SOM.

For proper operation, the phyCORE‑i.MX 8M Plus must be supplied with a voltage source of 3.2 V...3.5 V with a maximum power consumption of a 4 A load at the VCC pins on the phyCORE.

                VIN_3V3:                        X1 → C1..C4, D1..D4

Connect all +3.3 V VCC input pins to your power supply and, at minimum, the matching number of GND pins.

                Corresponding GND:           X1 → C5..C7, C15, D5..D7, D13

Please refer to section Pin Description for information on additional GND Pins located at the phyCORE i.MX 8M Plus Connector X1.

For information on various power consumption scenarios that PHYTEC has run, go to phyCORE-i.MX 8M Plus Power Consumption.

Power Management IC (PMIC) (U3)

The phyCORE-i.MX 8M Plus provides an onboard Power Management IC (PMIC) at position U3 to generate different voltages required by the microcontroller and the onboard components. The PMIC supports many functions like different power management functionalities like dynamic voltage control, different low power modes, and regulator supervision. It is connected to the i.MX 8M Plus via the onboard I²C bus (I2C1). The I²C address of the PMIC is 0x25.

Power Domains

External voltages to supply the board:

• VIN_3V3 3.3 V main supply voltage (3.2 V...3.5 V / max. 4A)
  
• optional: VIN_SNVS_1V8 low power supply voltage input (1.8 V ±5% / 10mA; if left open, it is provided on-board if VIN_3V3 is present)
• VBAT backup supply voltage for the on-board I2C-Bus RTC U9 (RV-3028-C7)

External Logic IO Supply Voltage

The voltage level (VDD_IO) of the phyCORE’s logic interface circuitry is VDD_3V3 (3.3 V) or VDD_1V8 (1.8 V) which is determined by the configuration input signal X_VIO_Ctrl (X1-D8). Connect X_VIO_Ctrl to the module input supply voltage VIN_3V3 to configure VDD_IO=3.3 V interface voltage level or connect it to GND to select VDD_IO=1.8 V interface voltage level.

In order to follow the power-up and power-down sequencing mandatory for the i.MX 8M Plus, external devices connected to the phyCORE interface circuitry have to be supplied by an external power supply which is controlled by the output signal X_nPWR_READY (OD driver) which ist brought out at pin X1-C14. X_nPWR_READY should control the external supply voltage which is used to supply the external interface circuitry connected to the phyCORE's interfaces. X_nPWR_READY switches to GND to start the external voltage supply or to switch over a power switch. If the onboard interface voltage (VDD_IO) switches off, X_nPWR_READY is released to high-impedance. To raise the signal, an external pull-up resistor (eg. 4k7) is needed. It can be connected to voltage level up to max. 12V depending on the external power supply control signal requirement. Use of X_nPWR_READY ensures that external components are only supplied when the supply voltages of the i.MX 8M Plus is stable and avoids undefined return currents while the system is powered down.

Backup Power (VBAT / VIN_SNVS_1V8)

To back up the on-board I2C-Bus RTC U9 (RV-3028-C7), an external voltage source must be added at Pin X1-C9 (VBAT). The RTC has an extremely low backup current consumption of only 40nA (@3 V). It is also possible to supply the internal RTC and some critical registers of the i.MX 8M Plus' low power domain (NVCC_SNVS_1V8). NVCC_NSNVS_1V8 can be supplied over Pin X1-C8 if VIN_3V3 is not present.

Reset

The X_PMIC_RST_B signal (Pin X1-C11) on the phyCORE-Connector is designated as a "cold reset" input. Driving X_PMIC_RST_B to low (has weak pull-up to SNVS_1V8) will restart the system performing a complete power recycle. X_PMIC_RST_B has a 50ms debouncing circuit. This input can be used for a mechanical reset switch button. X_POR_B Signal (Pin X1-C13) can be used to prevent bootup of the i.MX 8M Plus. This can be used as a startup as described in the section Power Management IC. 

System Boot Configuration

Most features of the i.MX 8 Plus microcontroller are configured and/or programmed during the initialization routine. Other features, which impact program execution, must be configured prior to initialization via pin termination.

The system start-up configuration includes:

• Boot mode selection
• Boot device selection
• Boot device configuration

The internal ROM code is the first code executed during the initialization process of the i.MX 8M Plus after POR. The ROM code detects the boot mode by using the boot mode pins (BOOT_MODE[3:0]), while the boot device is selected and configured by determining the state of the eFUSEs and/or the corresponding GPIO input pins (X_BOOT_MODE[3:0]).

Boot Mode Selection

The boot mode of the i.MX 8M Plus microcontroller is determined by the configuration of four boot mode inputs BOOT_MODE[3:0] during the reset cycle of the operational system. These inputs are brought out at the phyCORE processor pins X_BOOT_MODE[3:0] (X1-D22, X1-D23, X1-D24, X1-D25). phyCORE-i.MX 8M Plus Boot Modes shows the possible settings of pins X_BOOT_MODE[3:0] and the resulting boot configuration of the i.MX 8M Plus.

 phyCORE-i.MX 8M Plus Boot Modes

The X_BOOT_MODE[3:0] lines have 100 kΩ pull-down resistors populated (and unpopulated pull-up resistors) on the module in parallel to the internal pull-down resistors of the i.MX8 M Plus. Leaving the four pins unconnected sets the controller to boot mode 0, boot from internal fuses. The boot configuration settings can be changed by populating the pull-up resistors R44 to R47 (4,7 kΩ 0201) on the module or by connecting configuration resistors (e.g. 4,7 kΩ pull-up) to the X_BOOT_MODE configuration signals. The pull-up resistors must be supplied by the right VDD_IO voltage level of 1.8 V or 3.3 V depending on the VDD_IO configuration (see section "External Logic IO Supply Voltage").

The BOOT_MODE is initialized by sampling the BOOT_MODE inputs on the rising edge of the POR_B. After these inputs are sampled, their subsequent state does not affect the contents of the BOOT_MODE internal register and the pins can be used for GPIO operation.

 phyCORE-i.MX 8M Plus Boot Configuration Pins

System Memory

The phyCORE‑i.MX 8M Plus provides three types of onboard memory:

Additionally, an I²C-EEPROM with 4 kB is mounted to every SOM. Details for each memory type used on the phyCORE‑i.MX 8M Plus are below.

LPDDR4-RAM (U1)

The RAM memory interface of the phyCORE‑i.MX 8M Plus supports one 32-bit LPDDR4-RAM chip (U1). The LPDDR4 memory is accessible starting at address 0x4000 0000 and 1 0000 0000.

Typically, the LPDDR4-RAM initialization is performed by a boot loader or operating system following a power-on reset and must not be changed at a later point by any application code. When writing custom code independent of an operating system or boot loader, the RAM must be initialized by accessing the appropriate RAM configuration registers on the i.MX 8M Plus controller. Refer to the NXP Semiconductor i.MX 8M Plus Reference Manual to access and configure these registers.

eMMC Flash Memory (U4)

The main flash memory of the i.MX 8M Plus is eMMC and is populated at U4. The eMMC device is programmable with 1.8 V. No dedicated programming voltage is required. The eMMC Flash memory is connected to the SD3 interface of the i.MX 8M Plus.

For more information about the eMMC Flash interface, please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual.

I²C EEPROM (U10)

The phyCORE‑i.MX 8M Plus is populated with a non-volatile 4 kB I²C EEPROM at U10. This memory can be used to store configuration data or other general-purpose data. This device is accessed through I²C port 1 on the i.MX 8M Plus. The control registers for I²C port 1 are mapped between addresses 0x30A2 0000 and 0x30A3 0000. Please see the NXP Semiconductor i.MX 8M Plus Reference Manual for detailed information on the registers.

The three lower address bits are fixed to zero which means that the EEPROM can be accessed at I²C address 0x51. The EEPROM has a second address on 0x59, which is called Identification Page, and is reserved for internal PHYTEC uses only.

QSPI NOR Flash (U5)

The QSPI NOR Flash memory of the phyCORE-i.MX 8M Plus at U5 can be used to store configuration data or any other general-purpose data. It can also be used as a boot device and recovery boot device. The device is accessed through QSPIA SS0 on the i.MX 8 Plus. The control registers for QSPI are mapped between addresses 0x30BB 0000 and 0x30BB FFFF. Please see the NXP Semiconductor i.MX 8M Plus Reference Manual for detailed information on the registers.

As of the printing of this manual, these SPI Flash devices generally have a life expectancy of at least 100,000+ erase/program cycles and a data retention rate of 20 years. This makes the QSPI Flash a reliable and secure solution to store the first and second level bootloaders.

Serial Interfaces

The phyCORE‑i.MX 8M Plus provides numerous dedicated serial interfaces, some of which are equipped with a transceiver to enable direct connection to external devices:

1. One 4-bit SDIO interface (SD2) with controlled IO voltage
   
2. One 8-bit SDIO interface (SD1)
   
3. Four high-speed UARTs
4. Two CAN-FD interfaces
5. Two USB 3.0/2.0 Dual-Role interfaces with PHY
6. Two 1Gbit Ethernet interfaces with TSN support (ENET1 with Ethernet transceiver on the phyCORE-i.MX 8 M Plus enabling a direct connection to an existing Ethernet network; ENET0 as RGMII Signals at logic-level at the signal pins instead)
7. Three I²C interfaces
8. Two Serial Peripheral Interfaces (SPI)
9. Two SAI audio interface
10. One SPDIF interface
11. PCI Express x1 interfaces
12. Two MIPI CSI-2 camera interfaces
13. One MIPI DSI-2 display interface

Detail for each of these serial interfaces and any applicable jumper configurations are below.

SDIO Interface

The SDIO interface can be used to connect external SD cards, eMMC, or any other device requiring SDIO interface (i.e WiFI, I/O expansion, etc.) The phyCORE bus features one SDIO interface. On the phyCORE‑i.MX 8M Plus, the interface signals extend from the first and second Ultra Secured Digital (SD1 and SD2) Host controller to the phyCORE-Connector. 

The table below shows the location of the different interface signals on the phyCORE-Connector. The MMC/SD/SDIO Host Controller is fully compatible with the SD Memory Card Specification 3.0. The interface supports SD cards with 3.3 V and 1.8 V I/O signals.

SDIO SD2 (4-bit)

SDIO SD2 is a 4-bit wide interface with controlled I/O-voltage to support high-speed modes that require 1.8 V I/O voltage. During runtime, the I/O voltage can be switched from 3.3 V (default) to 1.8 V by the processor via GPIO signal X_PMIC_SD_VSEL/GPIO1_IO04 which controls the PMIC integrated voltage regulator. X_VDDSW_SD2 will be used exclusively to supply an external SD or MicroSD memory card. X_VDDSW_SD2 is monitored by the PMIC load switch circuit for overcurrent and short circuit. For more details please refer to the PMIC data sheet provided by NXP.

SDIO Interface Pinout of SD2

SDIO SD1 (8-bit)

SDIO SD1 is an 8-bit wide interface. The I/O voltage is determined by VDD_IO which is statically configured for the system to 3.3 V or 1.8 V (refer to External Logic IO Supply Voltage).

SDIO Interface Pinout of SD1

Universal Asynchronous Interfaces (UARTs)

The phyCORE‑i.MX 8M Plus provides four high speed universal asynchronous interfaces. The following table shows the location of the signals on the phyCORE-Connector.

UART Signal Locations

USB Interfaces

The phyCORE‑i.MX 8M Plus provides two USB 3.0/2.0 dual role interfaces, which support super-speed (5Bbit/s), high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) operation. The applicable interface signals can be found on the phyCORE‑Connector X1. If overcurrent and power enable signals are needed for the USB host interface, the functionality can be easily implemented with GPIOs.

USB 1 Signal Locations

USB 2 Signal Locations

Ethernet Interfaces ENET0 and ENET1

The phyCORE‑i.MX 8M Plus provides two Ethernet Interfaces ENET0 and ENET1 with TSN support. Connection of the phyCORE‑i.MX 8M Plus to the world wide web or a local area network (LAN) is possible using the onboard GbE PHY at U6. It is connected to the RGMII interface of ENET1. The PHY operates with a data transmission speed of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. Additionally, the RGMII interface of ENET0, which is available on the phyCORE‑Connector, can be used to connect an external PHY. (ENET0 RGMII Interface).

ENET1 Ethernet PHY (U6)

With an Ethernet PHY mounted at U6, the phyCORE‑i.MX 8M Plus has been designed for use in 10Base-T, 100Base-T, and 1000Base-T networks. The 10/100/1000Base-T interface with its LED signals extends to the phyCORE‑Connector X1.

Ethernet PHY Signal Locations

Ethernet Signal Locations of ENET1

The onboard GbE PHY supports HP Auto-MDIX technology, eliminating the need for a direct-connect LAN or cross-over patch cable. It detects the TX and RX pins of the connected device and automatically configures the PHY TX and RX pins accordingly. The Ethernet PHY also features an auto-negotiation to automatically determine the best speed and duplex mode.

The Ethernet PHY is connected to the RGMII interface ENET1 of the i.MX 8M Plus. Please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual for more information about this interface.

In order to connect the module to an existing 10/100/1000Base-T network, some external circuitry is required. The required termination resistors on the analog signals (ETH_A±, ETH_B±, ETH_C±, ETH_D±) are integrated into the chip, so there is no need to connect external termination resistors to these signals. Connection to external Ethernet magnetics should be done using very short signal traces. The A+/A-, B+/B-, C+/C-, and D+/D- signals should be routed as 100 Ohm differential pairs. The same applies to the signal lines after the transformer circuit. The carrier board layout should avoid any other signal lines crossing the Ethernet signals.

Reset of the Ethernet Controller

The reset input of the Ethernet PHY at U6 is connected to the system reset POR_B.

MAC Address

In a computer network such as a local area network (LAN), the MAC (Media Access Control) address is a unique computer hardware number. For a connection to the internet, a table is used to convert the assigned IP number to the hardware’s MAC address. In order to guarantee that the MAC address is unique, all addresses are managed in a central location. PHYTEC has acquired a pool of MAC addresses. The MAC address of the phyCORE‑i.MX 8M Plus is located on the bar code sticker attached to the module. This number is a 12-digit HEX value.

ENET0 RGMII Interface

In order to use an external Ethernet PHY, the RGMII interface (ENET0) of the i.MX 8M Plus is brought out at phyCORE‑Connector X1. ENET0 is primarily used for TSN network operation. For that use case, an external TSN-ready ethernet switch device is used.

ENET0 RGMII Interface Signal Locations

SPI Interface

The Serial Peripheral Interface (SPI) is a four-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The phyCORE provides two SPI on the phyCORE‑Connector X1. The SPI provides one chip select signals for each interface. The Enhanced Configurable SPI (eCSPI) of the i.MX 8M Plus has three separate modules (eCSPI1, eCSPI2 and eCSPI3) which support clock rates of up to 60 MHz. The interface signals of the first and second modules (eCSPI1, eCSPI2) are made available on the phyCORE-Connector. These modules are master/slave configurable. The following table lists the SPI signals on the phyCORE-Connector.

SPI Interface Signal Locations

I²C Interface

The Inter-Integrated Circuit (I²C) interface is a two-wire, bidirectional serial bus that provides a simple and efficient method for data exchange among devices. The i.MX 8M Plus contains four identical and independent Multimaster fast-mode I²C modules. The interface of 3 modules is available on the phyCORE-Connector X1. I2C1 is reserved for controlling on the SOM. 

The following table lists the I²C ports on the phyCORE-Connector:

I²C Interface Signal Locations

Audio Interface

 The i.MX 8M Plus supports multiple audio interfaces as listed below:

phyCORE-i.MX 8M Plus Audio Interfaces

I²S Audio Interface (SAI)

The phyCORE-i.MX 8M Plus features a Synchronous Audio Interface that supports full-duplex serial interfaces with frame synchronization such as I2S, AC97, and TDM. The interface is divided into four sub-interfaces SAI1, SAI2, SAI3, and SAI5. All signals are routed directly to the phyCORE-Connector X1. 

The tables below show the signal locations for each SAI and SPDIF interface.

SAI1 Interface

SAI1 is originally an 8-bit wide interface, but some of the signals are used dedicated for the Ethernet RGMII interface of ENET1, which is connected to the on-board PHY U6.

SAI1 Interface Signal Locations

SAI2 Interface

SAI2 Interface Signal Locations

SAI3 Interface

SAI3 Interface Signal Locations

SAI5 Interface

SAI5 Interface Signal Locations

SPDIF Interface

SPDIF Interface Signal Locations

PCI Express Interface

The one 1-lane PCI Express interfaces of the phyCORE‑i.MX 8M Plus provides PCIe Gen. 2.0 functionality which supports 5 Gbit/s operations. Furthermore, the interfaces are fully backward compatible with the 2.5 Gbit/s Gen. 1.1 specifications. Additional control signals which might be required (e.g. “present” and “wake”) can be implemented with GPIOs. Please refer to the schematic of a suitable PHYTEC carrier board (e.g. phyBOARD‑Pollux) for a circuit example.

The position of the PCIe signals on the phyCORE‑Connector X1 is shown below:

PCIe Interface Signal Locations

General Purpose I/Os

All pins not used by any of the other interfaces specifically described in this manual and can be used as GPIO without harming other features of the phyCORE‑i.MX 8M Plus. These pins are shown below:

GPIO Pin Locations

Besides these pins, most of the i.MX 8M Plus signals which are connected directly to the module connector can be configured to act as GPIOs, due to the multiplexing functionality of most controller pins. Normally, pins with signal type I/O are able to work as a GPIO.

Debug Interface

The phyCORE‑i.MX 8M Plus is equipped with a JTAG interface to download program code into the external flash, internal controller RAM, or any debugging programs being executed. The location of the JTAG pins on the phyCORE-Connector X1 are below:

Debug Interface Signal Locations

UART Debug

The default debug UART Interfaces (TTL) is UART2 for Cortex-A53 Cores and UART4 for Cortex-M7 Core. UART2 is accessible on connector X1 pins B2 (RXD) and B3 (TXD) and UART4 on pins B4 (RXD) and B5 (TXD).

For more information also refer to Universal Asynchronous Interfaces (UARTs).

Display Interfaces

High Definition Multimedia Interface (HDMI)

The High Definition Multimedia Interface (HDMI) of the phyCORE-i.MX 8M Plus is compliant with HDMI 2.0a for up to 1920x1080 at 60 Hz display resolutions. Please refer to the NXP Semiconductor i.MX 8M Plus Reference Manual for more information.

The location of the HDMI signals on the phyCORE-Connector X1 are shown below:

 HDMI Interface Signal Locations

Low Voltage Differential Signal Display Interface (LVDS)

The phyCORE-i.MX 8M Plus offers one LVDS display interface which supports two output channels.

The locations of the LVDS signals are shown below:

Display Interface LVDS Signal Locations

MIPI-DSI Display Interface (DSI)

The phyCORE-i.MX 8M Plus offers one MIPI-DSI display interface. MIPI-DSI has 4 channels, supporting one display with a resolution of up to 1920 x 1080 at 60Hz.

The locations of the MIPI-DSI signals are shown below:

Display Interface MIPI / DSI Signal Locations

Camera Connections

The phyCORE-i.MX 8M Plus offers 2 MIPI-CSI interfaces to connect digital cameras with a resolution of up to 12MP. The two MIPI/CSI‑2 camera interfaces of the i.MX 8M Plus extends to the phyCORE‑Connector X1 with 4 data lanes and one clock lane.

The locations of the MIPI-CSI signals are shown below:

Camera Interface MIPI / CSI-2 Signal Locations

RTC

The i.MX 8M Plus has an onboard, externally mounted RTC. The RV-3028 is the newest generation of RTC from Micro Crystal with an extremely low backup current of typically 40nA at 25 degrees. PHYTEC uses the most optimal implementation in each phyCORE design to give the most optimal usage for all customers.

The RTC is accessible over I2C1 on Address 0x52. In a normal operation state, the RTC power is supplied from the SOM voltage VDD_3V3. If the SOM is not powered and RTC backup is needed, the VBACKUP Pin of the RTC can be supplied over the VBAT pin X1-C9.

CPU Core Frequency Scaling

The phyCORE-i.MX 8M Plus on the phyBOARD‑Pollux is able to scale the clock frequency and voltage. This is used to save power and reduce heat dissipation when the full performance of the CPU is not needed. Scaling the frequency and voltage is referred to as 'Dynamic Voltage and Frequency Scaling' (DVFS).

The phyCORE-i.MX 8M Plus BSP supports the DVFS feature. The Linux kernel provides a DVFS framework that allows each CPU core to have a min/max frequency as well as the applicable voltage and a governor that governs these values depending on the system load. Depending on the i.MX 8M Plus variant used, several different frequencies are supported. Further details on how to configure this governor can be found in the phyCORE-i.MX 8M Plus BSP Manual.

Technical Specifications

Additional specifications:

Technical Specifications

These specifications describe the standard configuration of the phyCORE‑i.MX 8M Plus as of the printing of this manual.

phyCORE-i.MX 8M Plus Power Consumption

The values listed in the table below are a guideline to determine the required dimensions of the power supply circuitry on a carrier board. They do not take application-specific load situations into account. These values have been generated by looking at the maximum power consumption measured using different load scenarios and adding a voltage source of 3.3 V.  These values are based on internal PHYTEC testing. Customers need to consider their application power requirements to ensure they do not generate a load greater than the values listed here. 

phyCORE-i.MX 8M Plus Power Consumption

For power measurement, a SOM with 2 GB RAM, 16GB eMMC, ETH0, and an IMX8ML8DVNLZAA was used together with PD19.1.0.

phyCORE-i.MX 8M Plus Power Consumption Test Scenarios

Additionally, there are some values that cannot be tested. Situations such as suspending to RAM, suspend freeze, and standby mode must be tested on a case by case basis to ensure the application's power consumption stays within the guideline stated above.

Product Temperature Grades

The feasible operating temperature of the SOM highly depends on the use case of your software application. Modern high-performance microcontrollers and other active parts as the ones described within this manual are usually rated by qualifications based on tolerable junction or case temperatures. Therefore, making a general statement about minimum or maximum ambient temperature ratings for the described SOM is not possible.

However, the above-mentioned parts are available in different temperature qualification levels by the producers. We offer our SOM's in different configurations, making use of those temperature qualifications. To indicate which level of temperature qualification is used for active and passive parts of a SOM configuration, we have categorized our SOMs into three temperature grades.

The table below describes these grades in detail. This table describes a set of components that, in combination, add up to a useful set of product options with different temperature grades. This enables us to make use of cost optimizations depending on the required temperature range.

In order to determine the right temperature grade and whether the minimum or maximum qualification levels are met within an application, the following conditions must be defined by considering the use case:

• Determined the processing load for the given software use case
• Maximum temperature ranges of components (table below)
• Power consumption resulting from a baseload and the calculating power required (in consideration of peak loads as well as time periods for system cooldown)
• Surrounding temperatures and existing airflow in case the system is mounted into a housing
• Heat resistance of the heat dissipation paths within the system along with the considered usage of a heat spreader or a heat sink to optimize heat dissipation

Product Temperature Grades

Connectors on the phyCORE-i.MX 8M Plus

Information on the receptacle sockets that correspond to the connectors populating the underside of the phyCORE-i.MX 8 is provided below. The given connector height indicates the distance between the two connected PCBs when the module is mounted on the corresponding carrier board. In order to get the exact spacing, the maximum component height (1 mm) on the bottom side of the phyCORE must be subtracted.

Mating Connector

Please refer to the corresponding data sheets and mechanical specifications provided by Samtec (www.samtec.com).

Hints for Integrating and Handling the phyCORE‑i.MX 8M Plus

Integrating the phyCORE-i.MX 8M Plus

Besides this hardware manual, more information is available to facilitate the integration of the phyCORE‑i.MX 8M Plus into customer applications.

1. The design of the phyBOARD‑Pollux can be used as a reference for any customer application.
2. Many answers to common questions can be found at: https://www.phytec.de/produkte/system-on-modules/phycore-imx-8m/#downloads
3. The link “Carrier Board” within the category Dimensional Drawing leads to the layout data phyCORE-i.MX 8M Plus Footprint. It is available in different file formats. The use of this data allows the user to integrate the phyCORE-i.MX 8M Plus SOM as a single component into their design.
4. Different support packages are available for support in all stages of embedded development. Please visit https://www.phytec.de/support/support-pakete/ or https://www.phytec.eu/support/support-packages/ or contact our sales team for more details.

Handling the phyCORE-i.MX 8M Plus

phyCORE Module Modifications

The removal of various components, such as the microcontroller or the standard quartz, is not advisable given the compact nature of the module. Should this nonetheless be necessary, please ensure that the board, as well as surrounding components and sockets, remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module inoperable. If soldered components need to be removed, the use of a desoldering pump, desoldering braid, an infrared desoldering station, desoldering tweezers, hot air rework station, or other desoldering method is strongly recommended.  Follow the instructions carefully for whatever method of removal is used.

Integrating the phyCORE into a Target Application

Successful integration in user target circuitry greatly depends on the adherence to the layout design rules for the GND connections of the phyCORE module. For maximum EMI performance, PHYTEC recommends, as a general design rule, connecting all GND pins to a solid ground plane. At a minimum, all GND pin neighboring signals which are being used in the application circuitry should be connected to GND.

phyCORE-i.MX 8M Plus on the phyBOARD-Pollux

Hardware Overview

The phyBOARD‑Pollux for phyCORE-i.MX 8M Plus is a low-cost, feature-rich software development platform supporting the NXP Semiconductors i.MX 8M Plus microcontroller. Due to numerous standard interfaces, the phyBOARD‑Pollux i.MX 8M Plus can serve as the bedrock for any application. At the core of the phyBOARD‑Pollux is the PCM-070/phyCORE-i.MX 8M Plus System On Module (SOM) containing the processor, LPDDR4 RAM, eMMC Flash, power regulation, supervision, transceivers, and other core functions required to support the i.MX 8M Plus processor. Surrounding the SOM is the PB-03123/phyBOARD‑Pollux carrier board, adding power input, buttons, connectors, signal breakout, and Ethernet connectivity along with other peripherals.

The PCM-070 System On Module connects to the phyBOARD‑Pollux carrier board using 3 Samtec BTH connectors. This solution offers a highly flexible Single Board Computer for the i.MX 8M Plus processor, while maintaining most of the advantages of the SOM concept.

phyBOARD-Pollux Concept

PHYTEC phyCORE carrier boards are fully equipped with all mechanical and electrical components necessary for a fast, secure start-up. Subsequent communication to and programming of applicable PHYTEC System on Modules (SOM) is made easy. phyCORE carrier boards are designed for evaluation, testing, and prototyping PHYTEC System on Modules in laboratory environments prior to their use in customer designed applications.

This modular development platform concept includes the following components:

• The phyCORE-i.MX 8M Plus Module populated with the i.MX 8M Plus microcontroller and all applicable SOM circuitry such as LPDDR4 SDRAM, eMMC-Flash, Ethernet-PHY, and PMIC, etc.
• The phyBOARD-Pollux Carrier Board offers all essential components and connectors for a start-up including: a power supply for 24 V input voltage, interface connectors such as HDMI, USB, and Ethernet, which enable the use of the SOM’s interfaces with a standard cable.

The carrier board can also serve as a reference design for developing custom target hardware in which the phyCORE SOM can be deployed. Carrier board schematics are available under a Non-Disclosure Agreement (NDA). Reuse of carrier board circuitry enables users of PHYTEC SOMs to shorten time-to-market, reduce development costs, and avoid substantial design issues and risks.

SBCplus Concept

The SBCplus concept was developed to meet the many, small differences in customer requirements with little development effort. This greatly reduces the time-to-market. The core of the SBCplus concept is the SBC design library (a kind of construction set) that consists of a large number of function blocks (so-called "building blocks") which are continuously being refined and updated.

Recombining these function blocks allows PHYTEC to develop a customer-specific SBC within a short time. We are able to deliver production-ready custom Single Board Computers within a few weeks at very low costs. The already developed SBCs, such as the phyBOARD-Pollux, each represent a combination of different customer wishes. This means all necessary interfaces are already available on the standard versions, allowing PHYTEC SBCs to be integrated into a large number of applications without modification.

For any necessary detail adjustment, extension connectors are available which enable a wide variety of functions to be added.

phyBOARD-Pollux Features

The phyBOARD‑Pollux supports the following features :

• Developed in accordance with PHYTEC's SBCplus concept (SBCplus Concept)
• Populated with PHYTEC’s phyCORE-i.MX 8M Plus SOM
• Dimensions of 160 mm × 73 mm
• Boot from eMMC, SD Card, or over USB with the Serial Downloader
  
• Max. 1.3 GHz core clock frequency and up to four cores (at I-Temp Kit Version)
• 24 V power supply
• 2GB RAM (at Kit Version)
• 8GB eMMC (at Kit Version)
• 32MB NOR (at Kit Version)
• 4kB EEPROM
• Two RJ45 jack for 10/100/1000 Mbps Ethernet

• One USB 3.0 host interface connected to a USB 3.0 4-port HUB. The 3.0 interface is brought out to an upright USB Standard-A connector. The other 3 port are connected to the Mini PCI express connector, the Audio/Video connector, and the expansion connector^[2]
  

• One USB 3.0 host interface connected to phyCORE-i.MX 8M Plus Module
• One Secure Digital / MultiMedia Memory Card interface brought out to a Micro-SD connector
• One HDMI interface brought out to a standard Type-A connector
• One MIPI-DSI brought out via an A/V Connector
• Two MIPI-CSI-2 camera interfaces brought out as phyCAM-M interface
• One PCI interface brought out to a Mini PCI Express connector
• RS-232 and RS-485 multiprotocol transceiver supporting RS-232 including handshake, RS-485 Half-Duplex, and RS-485 Full-Duplex signals with data rates of up to 20 Mbps (RS-485) / 1 Mbps (RS-232) (2×5 pin header 2.54 mm)
• Reset button
• ON/OFF button
• One multicolor LED
• SAI Audio brought out via an A/V connector
• Digital I/O via an Expansion Connector
• JTAG via an Evaluation Adapter connected to the Expansion Connector
  
• Expansion connector for different interfaces
  • I²C
  • SPI
  • UART
  • QSPI
  • USB
• RTC
  • Goldcap Backup supply for RTC

Block Diagram

phyBOARD-Pollux Block Diagram

phyBOARD-Pollux Components

phyBOARD-Pollux Component Placement Diagram

phyBOARD-Pollux Components (Top)

phyBOARD-Pollux Components (Bottom)

phyBOARD-Pollux Component Overview

The phyBOARD-Pollux features many different interfaces and is equipped with the components listed in table Connectors and Pin Header. For a more detailed description of each component, refer to the appropriate section listed in the table below. phyBOARD-Pollux Components (Top) and phyBOARD-Pollux Components (Bottom) highlight the location of each component for easy identification.

Connectors and Pin Header

The table below lists all available connectors on the phyBOARD‑Pollux.

phyBOARD-Pollux Connectors and Pin Header

LEDs

The phyBOARD-Pollux is populated with 6 LEDs. One to indicate the status of the USB VBUS voltage of USB Debug Interface, four to indicate main board voltages. The sixth (D24) is user-programable. phyBOARD-Pollux Components (Top) and phyBOARD-Pollux Components (Bottom)) show the location of the LEDs. Their functions are listed in the table below:

 phyBOARD-Pollux LED Descriptions

Switches

The phyBOARD-Pollux is populated with three switches. The table below shows their functions:

phyBOARD-Pollux Switches

Jumpers

The phyBOARD-Pollux comes pre-configured with several removable jumpers (JP) and solder jumpers (J). These jumpers enable the flexible configuration of a limited number of features for development purposes.

The function of the removable jumper on the phyBOARD‑Mira is shown below. More detailed information can be found in the appropriate section. The locations of the removable jumpers can be found in phyBOARD-Pollux Components (Top).

phyBOARD-Pollux Jumper Settings

phyBOARD-Pollux SBC Component Detail

This section provides a more detailed look at the phyBOARD‑Pollux components. Each subsection details a particular connector/interface and associated jumpers for configuring that interface.

phyCORE Connector (X36)

phyCORE Connector (X36)

Power Supply (X22/X23)

Power Supply Connectors (X22/X23)

The phyBOARD-Pollux can be powered either by a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector (X23) or by a USB Power Delivery Supply (X22).

The phyBOARD‑Pollux is available with one power supply connector, a 2-pole Phoenix Contact MINI COMBICON base strip 3.5 mm connector (X23) suitable for a single 12 V/24 V supply voltage. The required current load capacity for all power supply solutions depends on the specific configuration of the phyCORE mounted on the phyBOARD-Pollux, the particular interfaces enabled while executing software, as well as whether an optional expansion board is connected to the carrier board.

The permissible input voltage is 12 V to 24 V DC if your SBC is equipped with a 2-pole Phoenix Contact MINI COMBICON base strip. A 24 V adapter with a minimum supply of 1.0 A is recommended to supply the board via the 2-pole base strip. The pin assignment for power supply connector X23:

X23 Pin Assignment

USB Power Delivery Connector (X22)

The phyBOARD‑Pollux can be powered by a USB Power Delivery Supply. The phyBOARD-Pollux provides the needed voltage and current with the connected supply and enables the on-board voltages. A 30 W USB-PD supply is recommended to power the phyBOARD-Pollux.

RTC Backup Supply

The phyBOARD-Pollux has a supercapacitor equipped to backup the VRTC rail of the phyCORE-i.MX 8M Plus. There is a multi-footprint to provide the most suitable Supercapacitor for customer applications. Default a 220 mF type is mounted that can be replaced by a 470 mF type. Using the 220 mF type the calculated minimum backup time is 176 h at 25 °C ambient temperature or 313 h at 25 °C ambient temperature using the 470 mF type. The maximum permissible backup time can be much longer depending on the charging time, the actual dark current, and in particular, the ambient temperature.

UARTs

The phyCORE-i.MX 8M Plus supports up to 4 UART units. On the phyBOARD-Pollux, TTL level signals of UART1 (the standard console) and UART4 are routed to Silicon Labs CP2105 UART to USB converter expansion. This USB is brought out at Micro-USB connector X1. UART2 is connected to a multi-protocol transceiver for RS-232 and RS-485, available at pin header connector X2 at RS-232 level, or at RS-485 level. UART3 is at X6 (Expansion Connector) at TTL level.

UART Design Consideration

When designing a custom carrier board, remember the TTL level is 3.3 V.

RS-232 and RS-485 (X2)

RS-232 and RS-485 Connector (X2)

Pin header connector X2 provides the UART2 signals of the i.MX 8M Plus at either the RS-232 or RS-485 level. The RS-232 interface is intended to be used as data terminal equipment (DTE) and allows for a 5-wire connection including the signals RTS and CTS for hardware flow control. RS-232 is enabled by setting JP3 to 2+3. The RS-485 can be used as a Half-Duplex (3-wire) or Full-Duplex (5-wire). Set JP4 to 1+2 for Half-Duplex Mode or 2+3 for Full-Duplex Mode. The table below shows the signal mapping of the RS-232 and RS-485 level signals at connector X2. The pinout is choosen to fit to the official standard RS-232 pinout on a DE9 plug (D-Sub 9 pin). Were TXD is pin 3, RXD is pin 2, RTS is pin 7, CTS is pin 8 and GND is pin 5. The suitable cables can be found in the table below.

RS-232/RS-485 (X2) Pin Assignment

CAN FD (X3/X4)

CAN FD (X3/X4)

The phyCORE i.MX 8M Plus FLEXCAN1 and FLEXCAN2 interfaces are brought out at X3 and X4, each as CAN FD. The maximum permissible CAN FD datarate is 8 Mbit/s. A 5 V power output is available to power a CAN device if needed. For development purposes, a 120 Ohms termination can be added by closing JP1 (CAN1) or JP2 (CAN2). For standard use, it is possible to mount a more suitable split termination in a customer-specific BOM.

The pinout is chosen to fit the official standard CAN pinout on a DE9 plug (D-Sub 9 pin), where CAN_L is pin 2, CAN_H is pin 7, GND is pin 3 and VCC_5V is pin 9. The suitable cables can be found in the table below.

CAN FD1 (X3) Pin Assignment

 CAN FD1 (X4) Pin Assignment

Ethernet (X8/X9)

Ethernet Connectors (X8/X9)

The phyBOARD‑Pollux is equipped with 2 RJ45 connectors supporting a 10/100/1000Base-T network connection. The LEDs for LINK (green) and SPEED (yellow) indication are integrated into the connector. The Ethernet transceiver supports Auto MDI-X, eliminating the need for a direct connect LAN or cross-over path cable. They detect the TX and RX pins of the connected device and automatically configure the PHY TX and RX pins accordingly.

Ethernet Design Consideration (X8)

The data lanes should be routed with a differential impedance of 100 Ohm. The center taps of each pair's transformer have to be connected to GND through a 100nF capacitor. The LED pins are open-drain outputs of the SOM without a resistor, so they should be connected to the cathodes of the LEDs through a resistor.

USB Interfaces

USB 3.2 Gen1 Interfaces (X5)

USB 3.2 Gen1 Connectors (X5)

The phyBOARD-Pollux provides two USB 3.2 Gen1 (5 Gbps) interfaces. USB1 is accessible at the upper socket as a host. Using an A-plug to A-plug cable, it is possible to provide USB in dual role mode at this socket. USB dual role mode can be used for downloading program code into the external flash, internal controller RAM, or for debugging programs currently executing. The lower socket is connected via a USB 3.2 Gen 1 hub to USB2 of the phyCORE i.MX 8M Plus.

USB 3.2 Gen1 Considerations

100 nF series capacitors might be required on USB1_RX and USB2_RS lines. Take care to double-check the signal direction of the high-speed lines where TX is output and RX is input on phyCORE-i.MX 8M Plus. The TX and RX lines should be routed with an impedance of 50 Ohms to a ground plane and 100 Ohms differential impedance. Route USB D lines with 45 Ohms to Ground and 90 Ohms differential impedance.

USB Debug (X1)

USB Debug Connector (X1)

The main debug interface is UART1. UART4 is the debug interface for the M7 core. Both UART interfaces are connected to a UART-to-USB Converter (Silicon Labs CP2105). The USB interface is brought out at a Micro-USB-AB socket (X1). Use the following terminal settings to connect to phyBOARD-Pollux serial interfaces:

• Speed: 115200 baud
• Data bits: 8
• Stop bits: 1
• Parity: None
• Flow control: None

The table below shows the pinout of the USB Debug connector:

 X1 Pin Assignment

Secure Digital Memory Card / MultiMedia Card (X7)

SD / MM Card Connector (X7)

The phyBOARD‑Pollux provides a standard microSDHC card slot at X7 for use with SD/MMC interface cards. It allows for a fast, easy connection to peripheral devices like microSD and MMC cards. Power to the SD interface is supplied by inserting the appropriate card into the SD/MMC connector. It also features card detection, a lock mechanism, and a smooth extraction function by pushing the card in and out.

SD / MM Card Design Considerations

Series resistors might be required to adapt the drive strength of the card. SD interface should be routed with an impedance of 50 Ohms to a ground plane. The trace length between CLK, CMD, and DATA lanes should be matched and keep as short as possible. Avoid Vias and take care of the signal current return path.

PCIe (X10)

PCIe Connector (X10)

The 1-lane PCI express interface provides PCIe Gen. 2.0 functionality, which supports 5 GT/s operations. The interface is fully backward compatible with the 2.5 GT/s Gen. 1.1 specification. Various control signals are implemented with GPIOs. The PCIe interface is brought out at the Mini PCIe connector X10 shown above.

The table below shows in-depth information such as pin assignment and signals used to implement special features of the Mini PCIe interface.