RAM Configuration at PHYTEC i.MX8M Mini

02 17, 2026 09:31

PHYTEC’s i.MX8M Mini modules (e.g., phyCORE-i.MX8M Mini) use external RAM chips connected to the processor’s DDR controller. While the designs vary, here are the key details based on their product documentation and typical implementations:

Design-Specific Details

• Memory Layout:
  PHYTEC modules pre-configure DDR timings and voltages in U-Boot/device tree to match their PCB design and DRAM chips.

• Validation:
  PHYTEC rigorously tests RAM stability using NXP’s DDR Stress Test Tool before release.

• SOM Integration:
  RAM is soldered directly onto the System-on-Module (SOM), ensuring signal integrity and reducing design complexity for customers.

Comparison of RAM Types

RAM support on the NXP i.MX8M Mini 

Specific RAM Timings for i.MX8M M

RAM timings are not fixed values for every CPU. It depends on:

• Specific DRAM chip (RAM Type)
• Board design and layout
• Memory controller configuration
• Bootloader

Automatic RAM size detection

Normally, every different RAM size with it's specific timings need to be build in a different U-boot. At Phytec, we modified the U-boot to be able to build all possible RAM-Timings (for standard products). This means, you can use the same U-boot image for 2GB as well as for 4 GB. At SPL level, the Hardware introspection is read out and this will tell the U-boot which RAM-timings should be loaded.

Locate PHYTEC-Specific DDR Configuration Files

Find PHYTEC-Specific RAM Info

1. Product Datasheets:
   Check the phyCORE-i.MX8M Mini datasheet for exact RAM size, type, and speed.

   • Example:https://www.phytec.de/produkte/system-on-modules/phycore-imx-8m-mini/nano/#technische-details/

2. PHYTEC Documentation:

   • Hardware Manual: Lists DRAM part numbers  

   • BSP (U-Boot) Sources: uboot/board/phytec/phycore_imx8mm/lpddr4_timing.c

U-Boot Source Code

For i.MX8M Mini you can find the RAM timings in the U-boot bootloader. Open the U-boot sources via Yocto devshell or clone the git repository and navigate to u-boot-phytec-dev/board/phytec/phycore_imx8mm/.

Here you can find the lpddr4_timing.c. You can also take a deeper look into the spl.c, the boardfile (phycore_imx8mm.c) and also the ../common/imx8m_som_detection.c. 

Linux Device Tree

PHYTEC defines DDR settings in the device tree (e.g., phytec-imx8mm-phycore.dtsi):

&ddrc { 
	ddr-type = <0x1>; 							// LPDDR4=0x1, DDR4=0x2, DDR3L=0x3 
	operating-points-v2 = <&ddrc_opp_table>; 
	dram-timing = <&dram_timing>; 				// Points to timing structure }; 
     /* PHYTEC-specific values */ 
	&dram_timing { 
		clk = <1500>; 							// 1.5 GHz
		tcl = <18>; 							// CAS latency (cycles) 	
		trcd_rd = <21>; 						// RAS-to-CAS delay (read) 
		trcd_wr = <21>;							// RAS-to-CAS delay (write) 
		tras = <42>; 							// Row active time 
		trfc = <630>; 							// Refresh cycle time 
		txs = <32>; 							// Self-refresh exit time 
	};

Where to Find Configuration Data

• Official Docs:

  • i.MX8M Mini Reference Manual (NXP Doc: IMX8MMRM)

  • DRAM Datasheet (from your RAM vendor, e.g., Micron, Samsung, etc.)

• Tools:

  • NXP DDR Stress Test Tool (validation)

  • Linux Device Tree Bindings (imx8mm-ddrc node for timing parameters)

Tools for Validation

1. NXP DDR Stress Test Tool:
   PHYTEC uses this to validate timings. You can re-run tests with their configuration.

2. PHYTEC RPA (Register Programming Aid):
   A custom spreadsheet provided by PHYTEC to generate DDR register values. Contact support for the RPA (mentioned earlier).

Verify via Boot Logs

In U-Boot, enable DDR debug messages:

=> setenv ddr_debug 1 => reset

Look for lines like:

DRAM: 2 GiB (effective 1.5 GHz, 32-bit, LPDDR4) ddr_init: tCL=18, tRP=21, tRCD=21, tRAS=42

Key PHYTEC-Specific Settings

Security

Resource Domain Controller (RDC) supports four domains up to eight regions of DDR

Arm TrustZone (TZ) architecture

• Support Arm Cortex-A53 MPCore TrustZone
• On-chip RAM (OCRAM) secure region protection using OCRAM controller
  • On-Chip Memory controller
    • OCRAM module is designed as an interface between the system's AXI bus and the internal on-chip= SRAM memory module
      • OCRAM is used for controlling the 256 KB multimedia RAM trough a 64-bit AXI bus
• TZASC (Trust-Zone Address Space Controller)
  • TZASC (TZC-380 by Arm) provides security address region control functions required for intended application.

DDR I/O DC electrical characteristics

- DDR Memory Controller  (DDRMC) is designed to be compiled with JEDEC-compliant SDRAMs

Comparison: PHYTEC vs NXP Reference Designs

Need More Help?

• Contact PHYTEC Support: They provide tailored DDR timing files for custom designs.

• Check Schematics: If you have access to PHYTEC’s SOM schematics, trace the DDR lines to identify exact DRAM parts (e.g., Micron MT53D1024M32D4DT-053 WT:D).

• PHYTEC BSP Guides: Follow their Yocto/U-Boot documentation to modify DDR parameters safely.